of miss = 3
This stars ()) shows the misses. Hence (B) is correct option.
Question. 29
The microinstructions stored in the control memory of a processor have a width of 26 bits. Each
microinstruction is divided into three fields: a micro-operation field of 13 bits, a next address field (X),
and a MUX select field (Y). There are 8 status bits in the inputs of the MUX.
How many bits are there in the X and Y fields, and what is the size of the control memory in number of
words?
(A) 10, 3, 1024 (B) 8, 5, 256
(C) 5, 8, 2048 (D) 10, 3, 512
SOLUTION
MUX has 8 states bits as input lines so we require 3 select inputs to select & input lines.
No. of bits in control memory next address field
= 26 − 13 − 3
= 10
10 bit addressing, we have 210 memory size. So X, Y size = 10,3,1024
Hence (A) is correct option.
Question. 30
A hard disk with a transfer rate of 10 M bytes/second is constantly
201
transferring data to memory using DMA. The processor runs at 600 MHz.
and takes 300 and 900 clock cycles to initiate and complete DMA transfer
respectively. If the size of the transfer is 20 Kbytes, what is the percentage
of processor time consumed for the transfer operation?
(A) 5.0% (B) 1.0%
(C) 0.5% (D) 0.1%
SOLUTION
Transfer rate = 10 MB ps
Data = 20 KB
Time = 20 X210 = 2 X 10−3
10 X 220
= 2 ms
Processor speed = 600 MHz
= 600 cycles/sec.
Cycles required by CPU = 300 + 900
For DMA = 1200
1200
So time = = .002 ms
6
600 X 10
.002
%= X 100
2
= 0.1%
Hence (D) is correct.
Question. 31
A 4-stage pipeline has the stage delays as 150, 120, 160 and 140
nanoseconds respectively. Registers that are used between the stages have
a delay of 5 nanoseconds each. Assuming constant clocking rate, the total
time taken to process 1000 data items on this pipeline will be
(A) 120.4 microseconds (B) 160.5 microseconds
(C) 165.5 microseconds (D) 590.0 microseconds
SOLUTION
Delay = 5 ns/stage
Total delay in pipline.
202
= 150 + 120 + 160 + 140 = 570 Delay due to 4 stages.
Stage 1 delay 1 stage 2 delay 2 stage 3 stage 4 5 X 3 = 15
Total = 570 + 15 = 585
Total time = 1000 data items 585 ns
YEAR 2005
Question. 32
Which one of the following is true for a CPU having a single interrupt request line and a single interrupt
grant line?
(A) Neither vectored interrupt nor multiple interrupting devices are possible
(B) Vectored interrupts are not possible but multiple interrupting devices are possible
(C) vectored interrupts and multiple interrupting devices are both possible
(D) vectored interrupt is possible but multiple interrupting devices are not possible
SOLUTION
Here multiple request can be given to CPU but CPU interrupts only for highest priority interrupt so
option (A) & (D) are wrong.
But here in case of single interrupt lines definitely vectored interrupts are not possible.
Hence (B) is correct option.
203
Question. 33
Normally user programs are prevented from handing I/O directly by I/O
instructions in them. For CPUs having explicit I/O instructions, such I/O
protection is ensured by having the I/O instructions privileged. In a CPU
with memory mapped I/O, there is no explicit I/O instruction. Which one
of the following is true for a CPU with memory mapped I/O?
(E) I/O protection is ensured by operating system routine(s)
(F) I/O protection is ensured by a hardware trap
(G) I/O protection is ensured during system configuration
(H) I/O protection is not possible
SOLUTION
In memory mapped I/0 the complete system (memory + I/0 ports) hold the
same set of addresses. They are considered to be the part of that memory
only. This management is done by OS only.
Hence (A) is correct option.
Question. 34
What is the swap apace in the disk used for?
(E) Saving temporary html pages
(F) Saving process data
(G) Storing the super-block
(H) Storing device drivers
SOLUTION
Swap space is the memory pre allowed to store process’s data. This can be
compared with virtual memory. The data required to complete process is
kept here.
Hence (B) is correct option.
Question. 35
Increasing the RAM of a computer typically improves performance
because
(E) Virtual memory increases
(F) Larger RAMs are faster
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(C) Fewer page faults occur
(D) Fewer segmentation faults occur
SOLUTION
Due to increase in RAM size all the pages required by CPU are available in RAM so page fault chance
are less, so virtual memory access chances are less and latency is reduced for secondary memory. Hence
(C) is correct option.
Question. 36
Consider a three word machine instruction
ADD A [R0],@B
The first operand (destination) “A [R0]” uses indexed addressing mode with R0 as the index register.
The second operand (source) "@B" uses indirect addressing mode. A and B are memory addresses
residing at the second and the third words, respectively. The first word of the instruction specifies the
opcode, the index register designation and the source and destination addressing modes. During
execution of ADD instruction, the two operands are added and stored in the destination (first operand).
The number of memory cycles needed during the execution cycle of the instruction is
(A) 3 (B) 4
(C) 5 (D) 6
SOLUTION
ADD A [ R 0],@B
This is instruction has 3 computational parts. ADD instruction requires 1 machine cycle, A [ R0] here R0
is index register which has starting address of index then this index has the block address. This whole
operation require 3 machine cycles. Now @ B is indirect addressing. This takes 2 machine cycles. So
overall 1 + 3 + 2 = 6 machine cycles.
Hence (D) is correct option.
205
Question. 37
Match List-I with List-II and select the correct answer using the codes
given below the lists:
List-I List-II
A. A [1] = B [j]; 1. Indirect addressing
B. while [* A ++]; 2. Indexed addressing
C. int temp=*x ; 3. Auto increment
Codes:
A B C
(A) 3 2 1
(B) 1 3 2
(C) 2 3 1
S 123
SOLUTION
LIST-I LIST-II
(iv) A [1] = B [ J]; 2 Indexed addressing here the
indexing is used
(v) While [) A ++] 3. Auto increment the memory
locations is A are automatically
incriminated.
(vi) int temp=) X
1. Indirect addressing here temp
is assigned the value of int type
stored at the address contained
in X
A2
B3
C1
Hence (C) is correct option.
Question. 38
206
Consider a direct mapped cache of size 32 KB with block size 32 bytes. The CPU generates 32 bit
addresses. The number of bits needed for cache indexing and the number of tag bits are respectively
(A) 10,17 (B) 10,22
SOLUTION
So, 10, 17
Hence (A) is correct option.
Question. 39
A 5 stage pipelined CPU has the following sequence of stages
IF-Instruction fetch from instruction memory.
RD-Instruction decode and register read,
EX- Execute:ALU operation for data and address computation,
MA-Data memory access-for write access the register read at
RD stage it used,
WB-register write back.
Consider the following sequence of instruction:
I 1 : LR0,Locl; R0 <= M[Locl]
I 2 AR0,R0; R0 <= R0 + R0
I 3 AR2,R0; R2 <= R2 − R0
Let each stage take one clock cycle.
What is the number of clock cycles taken to complete the above sequence of instruction starting from
the fetch of I1?
207
(A) 8 (B) 10
(C) 12 (D) 15
SOLUTION
Order of phase in instruction cycle.
IF " A 3" E X MA " WB
1 2 3 4 5 6 7 8 9 10
R 0 ! M [ LOC] IF RD EX MA WB
R 0 ! R 0 + R0 IF RD EX MA WB
R 2 ! R 2 − R0 IF RD EX MA WB
Total cycles = 10
Hence (B) is correct option.
Question. 40
A device with data transfer rate 10 KB/sec is connected to a CPU. Data is
transferred byte-wise. Let the interrupt overhead be 4 μ sec.
The byte transfer time between the device interface register and CPU or
memory is negligible. What is the minimum performance gain of
operating the device under interrupt mode over operating it under program
controlled mode?
(A) 15 (B) 25
(C) 35 (D) 45
SOLUTION
208
Hence (B) is correct option.
Question. 41
16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is
operated in cycle stealing mode whereby whenever one byte word is ready it is sent to memory;
similarly, for writing, the disk interface reads a 4 byte word from the memory in each DMA cycle.
Memory cycle time is 40 nsec. The maximum percentage of time that the CPU gets blocked during
DMA operation is
(A) 10 (B) 25
(C) 40 (D) 50
SOLUTION
, 26%
209
The, ALU, the bus and all the registers in the data path are of identical
size. All operations including incrementation of the PC and the GPRs are
to be carried out in the ALU. Two clock cycle are needed for memory read
operation-the first one for loading data from the memory but into the
MDR.
Question. 42
The instruction “add R0,R1” has the register transfer in terpretation R0 <=
R0 + R1. The minimum number of clock cycles needed for execution
cycle of this instruction is
(A) 2 (B) 3
(C) 4 (D) 5
SOLUTION
R0 ! R 0 + R1
First cycle require to fetch operands two cycles required for this. The
next cycle required to use ALU to perform ADD operation.
So total cycles required = 3
Question. 43
The instruction “call Rn, sub” is a two word instruction. Assuming that PC
is incremented during the fetch cycle of the first word of the instruction,
its register transfer interpretation is
Rn <= PC = 1;
PC <= M [PC];
210
The minimum number of CPU clock cycles needed during the execution cycle of this instruction is
(A) 2 (B) 3
(C) 4 (D) 5
SOLUTION
Rn ! PC + 1 PC = M [ PC]
Program outer is itself a register so incremented in 1 cycle.
Now fetching the memory at PC & the value of at address stored in PC takes 2 cycles.
So total 1 + 2 = 3 cycles. Hence (B) is correct option.
Question. 44
A CPU has 24-bit instructions. A program starts at address 300(in decimal). Which one of the
following is a legal program counter (all values in decimal)?
(A) 400 (B) 500
(C) 600 (D) 700
SOLUTION
YEAR 2006
Question. 45
A CPU has a cache with block size 64 bytes. The main memory has k banks, each bank being c bytes
wide. Consecutive c-bute chunks are mapped on consecutive banks with warp-around. All the k banks
can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access
may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by
accessing all the k banks in parallel. Each iteration requires decoding
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the bank numbers to be accessed in parallel and this takes k /2 ns. The
latency of one bank access is 80 ns. If c = 2 and k=24, then latency of
retrieving a cache block starting at address zero
from main
memory is (B) 104 ns
(A) 92 ns (D) 184 ns
(C) 172 ns
SOLUTION
Question. 46
A CPU has five-stages pipeline and runs at 1GHz frequency. Instruction
fetch happens in the first stage of the pipeline. A conditional branch
instruction computes the target address and evaluates the condition in the
third stage of the pipeline. The processor stops fetching new instructions
following a conditional branch until the branch outcome is known. A
program executes 109 instructions out of which 20% are conditional
branches. If each instruction takes one cycle to complete on average, then
total execution time of the program is
(A) 1.0 second (B) 1.2 seconds
(C) 1.4 seconds (D) 11.6 seconds
SOLUTION
Given that 80% of 109 instruction require single cycle i.e. no conditional
branching & for 20% an extra cycle required.
Time taken by 1 cycle = 10−9 sec.
212
Total time = 10−9 b 10080 X 109 + 10020 X 2 X 109l
= 10−9 X 109 b 54 + 25 l
6
= 5 = 1.2 seconds.
Hence (B) is correct option.
Question. 47
Consider a new instruction named branch-on-bit-set (mnemonic bbs). The instruction “bbs reg, pos,
labbel” jumps to label if bit in position pos of register operand reg is one. a register is 32 bits wide and
the bits are numbered 0 to 31, bit in position 0 being the least significant. Consider the following
emulation of this instruction on a processor that does not have bbs implemented.
temp!reg and mask
Branch to label if temp is non-zero
The variable temp is a temporary register. For correct emulation the variable mask must be generated
by
(A) mask! 0x1 << pos (B) musk! 0x ffffffff >> pos
(C) mask! pos (D) msdk! 0xf
SOLUTION
Data for Q. 48 & Q. 49 are given below. Solve the problem and choose the correct answers.
Consider two cache organizations: The first one is 32 KB 2-way set associative with 32-bytes block
size. The second one is of the same
213
size but direct mapped. The size of an address is 32 bits in both cases A2-
to-1 multiplexes has latency of 0.6 ns where a k-bit comparator has a
latency of k /10ns. The hit latency of the set associative organization is h1
while that of the direct mapped one is h2.
Question. 48
The value of h1 is
(A) 2.4ns (B) 2.3ns
(C) 1.8ns (D) 1.7ns
SOLUTION
Tag index
h1 = 1810 + 0.6 ns
= 2.4 ns.
Question. 49
The value of h2 is
(A) 2.4ns (B) 2.3ns
214
(C) 1.8ns (D) 1.7ns
SOLUTION
Similarly to previous question. The CPU address is same but Direct coaching require for 32 KB 15 bits.
Which would be 10 + 5 = 17
17 10 5
h2 = 1710 + 0.6
= 2.3 ns Hence (B) is correct option.
Question. 50
The value of M1 is
215
(A) 0 (B) 2048
(C) 16384 (D) 262144
SOLUTION
Given loop P1 accesses array A row wise & P2 access column wise.
M1 = ?
Cache Capacity = 215 B.
1 element = 23 B
Total elements 512 X 512
Total data = 512 X 512 X 8 B =
221 B
Block size = 128 B
1 block can have = 1288 = 16 elements
512 X 512
So total blocks require = 16
= 1638 blocks
Since the memory is initially empty so all blocks are required at least
once.
So, M1 = 16384 Hence (C) is
correct option.
Question. 51
The value of the ratio M1/M2 is
(A) 0 (B) 1/16
(C) 1/8 (D) −16
SOLUTION
Now M2 =?
In the case (P2 loop) the array is accessed column wise, so even the block
brought for A [0][0] − A[0][15] would not be used for second column wise
access i.e. A[1][0] So new block need to swap, similarly for A[3][0] & So
on. This would continue for every element, since memory is contiguous.
So M2 = 512 X 512 = 262144
216
& M1 = 16384 = 1 M2 262144 16
YEAR 2007
Question. 52
Consider a 4-way set associative cache consisting of 120 lines with a line size of 64 words. The CPU
generates a 20-bit address of a word in main memory. The number of bits in the TAG, LINE and
WORD fields are respectively
(A) 9,6,5 (B) 7,7,6
(C) 7,5,8 (D) 9,5,6
SOLUTION
9 5 6
Question. 53
Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. 512 bytes of
data are stored in a bit serial manner in a sector. The capacity of the disk pack and the number of bits
required to specify a particular sector in the disk are respectively
(A) 256 Mbytes, 19 bits (B) 256 Mbyte, 28 bits
(C) 512 Mbytes, 20 bits (D) 64 Gbyte, 28 bits
217
SOLUTION
Question. 54
Consider a pipelined processor with the following four stages
IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Bank
The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock
cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle
and the MUL instruction need 3 clock cycles in the EX stage. Operand forwarding is used in the
pipelined processor. What is the number of clock cycles taken to complete the following sequence of
instructions?
SOLUTION
1 2 3 4 5 6 7 8
R 2 ! R 1 ! R0 IF ID EX WB
R 4 ! R 3 ! R2 IF ID EX EX EX WB
R 6 ! R 5 ! R4 IF ID - - EX WB
218
Represent wait in pipeline due to result dependently. Clock cycles require = 8
Hence (B) is correct option.
Consider the following program segment. Here R1, R2 and R3 are the
general purpose registers.
Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The
content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the
memory location 100. All the numbers are in decided.
Question. 55
Assume that the memory is word addressable. The number of memory references for accessing the data
in executing the program completely is
(A) 10 (B) 11
(C) 20 (D) 21
219
SOLUTION
1st memory reference R1 ! M 3000 and then in the loop which
^h
runs for 10 times there are 2 memory reference every iteration.
10 X 2 = 20
Instruction Words Location
Total 20 + 1 = 21
R2 ! M [ R3]
M [R3] ! R2
Hence (D) is correct option
Question. 56
Assume that the memory is word addressable. After the execution of this program, the content of memory
location 2010 is
(A) 100 (B) 101
(C) 102 (D) 110
SOLUTION
Program stores results from 2000 to 2010. It stores 110, 109, 108......100 at 2010 location.
DEC R1
Hence (A) is correct option.
Question. 57
Assume that the memory is byte addressable and the word size is 32 bits. If an interrupt occurs during the
execution of the instruction “INC R3”, what return address will be pushed on to the stack?
(A) 1005 (B) 1020
(C) 1024 (D) 1040
SOLUTION
220
MOV R1, (3000) 2 1000-1007
MOV R2, R1 1 1008-1011
ADD R2, R1 1 1012-1015
Interrupt occurs during execution of INC R3, So CPU will complete the execution of this instruction and then
Push the next address 1024 to the stack, so after interrupt service the program can be resumed from next
instruction.
Hence (C) is correct option.
Question. 58
How many data cache misses will occur in total?
(A) 48 (B) 50
(C) 56 (D) 59
SOLUTION
221
Question. 59
Which of the following lines of the data cache will be replaced by new
blocks in accessing the array
(A) line 4 to line 11 (B) line 4 to line 12
(C) line 0 to line 7 (D) line 0 to line 8
SOLUTION
YEAR 2008
Question. 60
For a magnetic disk with concentric circular track, the latency is not
linearly proportional to the seek distance due to
(A) non-uniform distribution of requests
(B) arm starting and stopping inertia
(C) higher capacity of tracks on the periphery of the platter
(D) use of unfair arm scheduling policies.
SOLUTION
Question. 61
Which of the following is/are true of the auto increment addressing mode?
1. It is useful in creating self relocating code
2. If it is included in an Instruction Set Architecture, then an
222
additional ALU is required for effective address calculation
3. The amount of increment depends on the size of the data item
accessed.
(A) 1 only (B) 2 only
(C) 3 only (D) 2 and 3 only
SOLUTION
In auto increment addressing mode the address where next data block to be stored is generated automatically
depending upon the size of single data item required to store. So statement 3 is correct.
Statement says that this mode is used for self relocating code, but this is false since self relocating code, takes
always some address in memory.
Statement 2 is also incorrect since no additional ALV is required. Hence (C) is correct option.
Question. 62
Which of the following must be true for the RFE (Return from Expectation) instruction on a general purpose
processor.
1. It must be a trap instruction
2. It must be a privileged instruction
3. An exception can not be allowed to occur during execution of an RFE instruction.
(A) 1 only (B) 2 only
(C) 1 and 2 only (D) 1, 2 and 3 only
SOLUTION
RFE (Return From Exception) is a privileged trap trap instruction which is executed when exception occurs, so
an exception is not allowed to execute.
Hence (D) is correct option.
Question. 63
For inclusion to hold between two cache level L1 and L2 in a multilevel cache hierarchy, which of the following
are necessary?
1. L1 must be a write-through cache
2. L2 must be write-through cache
223
3. The associativity of L2 must be greater that of L1
4. The L2 cache must be at least as large as the L1 cache
(A) 4 only (B) 1 and 2 only
(C) 1, 2 and 4 only (D) 1, 2, 3 and 4
SOLUTION
Level 1 (L1) & Level 2 (L2) cache are placed between CPV & they can be
both write through cache but this is not necessary. Associativity has no
dependence but L2 cache must be at least as large as L1 cache, since all
the words in L1 are also is L2.
Hence (A) is correct option.
Question. 64
Which of the following are NOT true in a pipe lined processor?
1. Bypassing can handle alll Raw hazards.
2. Register renaming can eliminate all register carried WAR hazards.
3. Control hazard penalties can be eliminated by dynamic branch
prediction.
(A) 1 and 2 only (B) 1 and 3 only
(C) 2 and 3 only (D) 1,2 and 3
SOLUTION
Question. 65
The use of multiple register windows with overlap causes a reduction in
the number of memory accesses for
1. Function locals and parameters
2. Register saves and restores
224
3. Instruction fetches
(A) 1 only (B) 2 only
(C) 3 only (D) 1,2 and 3
SOLUTION
Multiple register windows with overlap causes a reduction in the number of memory accesses for instruction
fetching.
Hence (C) is correct option.
Question. 66
In an instruction execution pipeline, the earliest that the data TLB (Translation Look aside Buffer) can be
accessed is
(A) before effective address calculation has started
(B) during effective address calculation
(C) after effective address calculation has completed
(D) after data cache lookup has completed
SOLUTION
225
data memory references made by the program are those to array APR.
Question. 67
The total size of the tags in the cache directory is
(A) 32 kbits (B) 34 kbits
(C) 64 kbits (D) 68 kbits
SOLUTION
Virtual (CPU) address has = 32 bits
2 way set associative cache size = 64 KB
Size of 1 set = 32 KB
Require 15 bits for indexing.
So Tag = 32 − 15 = 17
Size of block = 16 bytes
= 4 bits are required
Index = block + word
Block = 15 − 4 = 11
17 11 4
CPV address
17
Size of tags = There are 2 bytes of tags in every set of cache. So
total = 17 X 2 X 1024
= 34 KB.
Hence (B) is correct option.
Question. 68
Which of the following array elements has the same cache index as APR
[0][0]?
(A) APR[0][4] (B) APR[4][0]
(C) APR[0][5] (D) APR[5][0]
SOLUTION
Elements stored in row major order. Two elements should have same
cache index (15 bits) & their tags may be different (17 bits). SoAPR[%][
%] the MSB 17 bits will be changed.
226
APR[%][ %] APR[%][1]...............
APR[2][%]................................
APR[4][%]................................
So on.
This is virtual memory storage.
So 15 LSB of APR [%][ %] & APR [%][ %] are same so same index APR [%] & APR [4] 17 MSB are different
so tags differ.
Hence (B) is correct option.
Question. 69
The cache hit ratio for this initialization loop is
(A) 0% (B) 25%
(C) 50% (D) 75%
SOLUTION
No. of hits
Cache hit ratio =
Total accesses
1024
= = 1 = 0.5
1024 + 1024 2
or = 50%
Hence (C) is correct option.
Question. 70
For all delayed conditional branch instruction, irrespective of weather the condition evato true or false, A
(A) the instruction following the conditional branch instruction in memory is executed
(B) the first instruction in the fall through path is executed
(C) the first instruction in the taken path is executed
(D) the branch takes longer to execute that any other instruction
227
SOLUTION
Question. 71
The following code is to run on a pipe lined processor with one branch
delay slot
11: ADD R2 ! R7+R8
12: SUB R4 ! R5− R6
13: ADD R1 ! R2+ R3
14: STORE Memory [R4] ! R1
BRANCH to Label if R1==0
Which of the instruction 11,12,13 or 14 can legitimately occupy the delay
slot without any other program modification?
(A) 11 (B) 12
(C) 13 (D) 14
SOLUTION
YEAR 2009
Question. 72
How many 32KX1 RAM chips are needed to provide a memory capacity
of 356-bytes ?
(A) 8 (B) 32
(C) 64 (D) 128
228
SOLUTION
Question. 73
A CPU generally handles are interrupt by executing an interrupt service routine
(A) As soon as an interrupt is raised
(B) By checking the interrupt register at the end of fetch cycle
(C) By checking the interrupt register after finishing the execution of the current instruction
(D) By checking the interrupt register at fixed time intervals
SOLUTION
An interrupt is a signal delivered to CPU, which tells to stop its normal service routine & execute interrupt
service routine.
This interrupt service routine is checked as soon as CPU receives the interrupt but since CPU working unit is an
instruction so CPU can switch to ISR only after execution of current instruction.
Hence (C) is correct option.
Question. 74
Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions 11, 12, 13, 14 in
stages S1, S2, S3, S4 is shown below:
S1 S2 S3 S4
I1 2 1 1 1
I2 2 3 2 2
I3 2 1 1 3
229
I4 1 2 2 2
SOLUTION
We can see a single iteration of given for loop according to the cycles
required.
Cycle S1 S2 S3 S4 Completion
1 I1
2 I1
3 I2 I1
4 I3 I2 I1
5 I3 I2 I1 I1
6 I4 I2
7 I3 I2
8 I4 I2
9 I4 I3 I2
10 I4 I2 I2
11 I4 I3
12 I3
13 I3 I3
14 I4
15 I4 I4
Question. 75
Consider a 4 way set associative cache (initially empty) with total 16
cache blocks. The main memory consists of 256 blocks and the request for
memory blocks is in the following order :
230
0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155
Which one of the following memory block will NOT be in the cache if LRU replacement policy is used ?
(A) 3 (B) 8
(C) 129 (D) 216
SOLUTION
216 mod4 = 0 )
129 mod4 = 1 )
Set 2
63 mod4 = 3 )
8 mod4 = 0 )
255 155 98 mod4 = 0 )
3 3 32 mod4 = 0 )
Set 3
159 159 73 mod4 = 1 )
63 63 92 mod4 = 0 )
155 mod4 = 3 )
All ) are misses S1 is the first stage & S2 is second. In the second stage 216 is not present in
Cache Hence (D) is correct option.
Question. 76
The address 400,16,29 , corresponds to sector number:
(A) 505035 (B) 505036
(C) 505037 (D) 505038
SOLUTION
Question. 77
The address of 1039th sector is
(A) 0,15,31 (B) 0,16,30
(C) 0,16,31 (D) 0,17,31
SOLUTION
Question. 78
A main memory unit with a capacity of 4 megabytes is build using 1M X 1 − bit DRAM chips. Each DRAM
chip has 1K rows of cells with 1 K cells in each row. The time taken for a single refresh operation is 100
nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is
(A) 100 nanoseconds (B) 100)210nanoseconds
(C) 100)220nanoseconds (D) 3200)220nanoseconds
SOLUTION
= 32
1 DRAM has 1 K rows
1 ROW has 1 K cells
Total cells in 1 DRAM = K2 = 220
In 32 DRAM = 32 X 220 Cells 1 cell refresh take 100 ns.
So total refresh time
= 32 X 100 X 220 ns
= 3200 X 220 ns.
Question. 79
A-5 stage pipelined processor has Instruction Fetch. (IF), Instruction Decode (ID), Operand Fetch (OF),
Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle
each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instruction. The PO stage takes 1
stake clock cycle for ADD and SUB instructions 3 clock cycles for MUL instruction, and 6 clock cycles for
DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles
needed to execute the following sequence of instructions ?
233
Instruction Meaning of instruction
I0 : MUL R 2, R 0, R1 R 2 ! R 0)R1
I1: DIV R 5, R 3, R4 R 5 ! R 3 /R4
I2 : ADD R 2, R 5, R2 R 2 ! R 5 + R2
I3 : SUB R 5, R 2, R6 R 5 ! R 2 − R6
(A) 13 (B) 15
(C) 17 (D) 19
SOLUTION
Figure
Here A = (R 3 /R 4) + R 2, R6
So we can see that all the instruction can be executed in 17 clock cycles
using piplining.
Question. 80
The program below uses six temporary variables a, b, c , d, e, f a
=1
b = 10
c = 20
d=a+b
e=c+d
f = c + e
b=c+e
e = b + f
d=5+e
Assuming that all operations take their operands from register, what is the
minimum number of registers needed to execute this program
without spilling ?
(A) 2 (B) 3
(C) 4 (D) 6
234
SOLUTION
Replacement
R1 R2 R3
a b c
d b c
d e c
f e c
f b c
f e c
f e d
So all the operations done using 3 registers only.
Hence (B) is correct option.
A computer system has an L1 and L2 cache, an L2 cache, and a main memory unit connected as shown below.
The block size in L1 cache is 4 words. The block size is L2 cache is 16 words. The memory access times are 2
nanoseconds, 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory unity respectively.
Question. 81
When there is a miss in L1 cache and a hit in L2 cache, a block is transferred form L2 cache to L1 cache. What is
the time taken for this transfer ?
(A) 2 nanoseconds (B) 20 nanoseconds
(C) 22 nanoseconds (D) 88 nanoseconds
SOLUTION
Each block is L2 Cache is 4 times L1 Cache. So far 1 block miss in L1 Cache the block from L2 to L1 will be
transferred, but L2 block has size 16 words & L1 data bus of 4 words, so 4L2 & 4L1 access are
235
required.
4 X 2 + 4 X 20
8 + 80
88 ns
Hence (D) is correct option.
Question. 82
When there is a miss in both L1 cache and L2 cache, first a block is transferred from
memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is
the total time taken for these transfers ?
(A) 222 nanoseconds (B) 888 nanoseconds
(C) 902 nanoseconds (D) 968 nanoseconds
SOLUTION
Miss in both L1 & L2. Cause main memory to transfer that block in both cache.
1 block of Main memory has 16 words but data bus of L2 has only 4 words. So 4 access
of Main memory & 4 access of L2 Cache required to update L2
4 X 20 + 4 X 200
80 + 800 = 880 ns
YEAR 2013
92. Consider an instruction pipeline with five stages without any branch prediction:
Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute
Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and
WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate
storage buffers after each stage and the delay of each buffer is 1 ns. A program
consisting of 12 instructions I1 ,I2 ,I3 ,......I12 is executed in this pipelined
processor. Instruction I4 is the only branch instruction and its branch target is I9 .
If the branch is taken during the execution of this program, the time (in ns)
needed to complete the program is
(A) 132 (B) 165 (C) 176 (D) 328
236
Ans: (C)
Exp: Total clock slots taken are 16. Each slot will take maximum of {5, 7, 10, 8 ,7} =10.
DIGITAL DESIGN
YEAR 2001
Question. 1
Given the following Karnaugh map, which one of the following represents the minimal sum-of-Products
of the map ?
237
SOLUTION
Question. 2
Consider the following circuit with initial state Q 0 = Q1 = 0. The D flip-flops are positive edged
triggered and have set up times 20 nanosecond and hold times 0.
Consider the following timing diagrams of X and C ; the clock of C $ 40 nanosecond. Which one is the
correct plot of Y
238
SOLUTION
Question. 3
The 2’s complement representation of (− 539)10 is hexadecimal is
(A) ABE (B) DBC
(C) DE5 (D) 9E7
SOLUTION
(DES)16
Hence (C) is correct option.
Question. 4
Consider the circuit shown below. The output of a 2:1 Mux is given by the function (ac ' + bc).
SOLUTION
Question. 5
Consider the circuit given below the initial state Q 0 = 1,Q 1 = Q2 = 0. The state of the circuit is given by
the value 4Q 2 + 2Q 1 + Q0
240
Which one of the following is the correct state sequence of the circuit
?
(A) 1, 3, 4, 6, 7, 5, 2 (B) 1, 2, 5, 3, 7, 6, 4
(C) 1, 2, 7, 3, 5, 6, 4 (D) 1, 6, 5, 7, 2, 3, 5
SOLUTION
Initially Q0 Q1 Q2 Value 4Q 2 + 2Q 1 + Q0
Clk 1 0 0 1
1 0 1 0 2
2 1 0 1 5
3 1 1 0 3
4 1 1 1 7
5 0 1 1 6
6 0 0 1 4
YEAR 2002
Question. 6
241
(A) xz + y' z (B) xz' + zx'
(C) x' y + zx' (D) None of the above
SOLUTION
Question. 7
242
SOLUTION
Question. 8
The 2’s complement represent representation of the decimal value −15 is
(A) 1111 (B) 11111
(C) 111111 (D) 10001
SOLUTION
Given (− 15)10
Binary of 15 = (01111)2
2’s complement of 15 would represent (− 15).
01111
(10001)2
Hence (D) is correct option.
Question. 9
Sign extension is a step in
(I) floating point multiplication
(J) signed 16 bit integer addition
(K) arithmetic left shift
(L) converting a signed integer from one size to another.
SOLUTION
243
Question. 10
SOLUTION
In 2’s complement addition, overflow occurs when the carries from sign bit & previous bit doesn’t
match. So overflow can’t occur when a positive value is added to some negative value.
Hence (B) is correct option.
Question. 11
Consider the following logic circuit whose inputs are functions f1, f2, f3 and output is f
Given that
f1(x, y, z) = Σ(0,1,3,5)
f2(x, y, z) = Σ(6,7), and
f (x, y, z) = Σ(1,4,5)
f3 is
(A) Σ(1,4,5) (B) Σ(6,7)
(C) Σ(0,1,3,5) (D) None of the above
SOLUTION
f1 (x, y, z) = Σ(0,1,3,5)
244
= x' y' + y' z + x'
z f2 (x, y, z) = Σ(6,7)
= xy
f (x, y, z) = Σ(1,4,5)
= xy' + y' z
f (x, y, z) = f1 f2 : f3
(I) f1 : f2 + f3
(J)xy (x' y' + y' z + x' z) + (xy' + y' z)
f3 = xy' z + xy' z' + xy' z + x' y'
z f3 = Σ(1,4,5)
Hence (A) is correct option.
Question. 12
Consider the following multiplexor where 10, 11, 12, 13 are
four data input lines selected by two address line combinations
A1A0 = 00,01,10,11 respectively and f is the output of the
multiplexor. EN is the Enable input.
245
The function f (x, y, z) implemented by the above circuit is
(A) xyz' (B) xy + z
(C) x + y (D) None of the above
SOLUTION
A1 A0 EN (MUX) work
0 0 1 do not
0 1 0 (MUX) Work
1 0 1 do not
1 1 0
So MUX is ENABLED only if A0 = 0
So output should have Z'.
Consider xyz' option (A)
A, A0 = 1 0 gives correct answer.
Hence (A) is correct option.
Question. 13
Let f (A, B) = A' + B. Simplified expression for function f (f (x + y, y), z) is
(A) x' + z (B) xyz
(C) xy' + z (D) None of the above
SOLUTION
f (x + y, y) = (x + y)' + y & x + y + y
f (f (x + y, y), z) = x + y + y + z & (x + y : y ) + z
[(x + y) : y ] + z
246
[xy + yy ] + z
xy + z
Hence (C) is correct option.
Question. 14
What are the states of the Auxiliary Carry (AC) and Carry Flag (CY) after
executing the following 8085 program ?
MIV H, 5DH
MIV L, 6BH
MOV A, H
ADD L
(A) AC = 0 and CY = 0 (B) AC = 1 and CY = 1
(C) AC = 1 and CY = 0 (D) AC = 0 and CY = 1
SOLUTION
is the carry so CY = 0
(I) is auxillary carry AC = 1
Hence (C) is correct option.
Question. 15
SOLUTION
0(A) 1(B) 01
1(B) 0(A) 01
1(B) 1(C) 10
1(C) 1(C) 10
1(C) 0(A) 01
So output is always sum of the present and previous bits of input. Hence (A) is correct option.
YEAR 2003
Question. 16
Assuming all numbers are in 2’s complement representation, which of the following number is
divisible by 11111011?
(A) 11100111 (B) 11100100
(C) 11010111 (D) 11011011
SOLUTION
248
We can’t judge the no’s in 2’s complement first we need to convert them in decimal
Given no. 11111011"00000101=5
Question. 17
The following is a scheme for floating point number representation using 16 bits.
Let s, c and m be the number represented in binary in the sign, exponent, and mantissa fields
respectively. Then the flouting point number represented id
− 9 e−31
)(− 1) (1 + m # 2 )2
2
, if the exponent 111111 0 otherwise
SOLUTION
Question. 18
A 1-input, 2-output synchronous sequential circuit behaves as follows.
249
Let zk , nk denote the number of 0’s and 1’s respectively in initial k bits of the input (zk + nk = k). The
circuit outputs 00 until one of the following conditions holds.
1. nk − nk = 2. In this case, the output at the k -th and all subsequency clock ticks is 10.
2. nk − zk = 2. In this case, the output at the k -th and all subsequent clock ticks is 01.
What in the minimum number of states required in the state transition graph of the above circuit?
(A) 5 (B) 6
(C) 7 (D) 8
SOLUTION
The sequential circuit has 3 variables to decide the state in which input & 2 inputs are present. Output
for particular inputs decide states.
i/p op 1 op 2 State
0 0 0 Intial
0 0 1 nK−zK=2
0 1 0 zK−nK=2
0 1 1 Not applicable
1 0 0 Initial
1 0 1 nK−zK=2
1 1 0 zK−nK=2
1 1 1 is correct
Using 3 bits we require 23 − 1 = 7 states here.
Hence (C) is correct option.
Question. 19
The literal count of a boolean expression is the sum of the number of times each literal appears in the
expression. For example, the literal count of (xy + xz) is 4. What are the minimum possible literal
counts of the product-of-sum and sum-of-product representations respectively of the function given by
the following karnaugh map?
250
(A) (11,9) (B) (9,13)
(C) (9,10) (D) (11,11)
SOLUTION
Question. 20
Consider the following circuit composed of XOR gates and non-inverting buffers.
in the figure. both XOR gates and al wires have zero delay. Assume that all gate inputs, outputs and
251
wires are stable at logic level 0. If the following waveform is applied at input. A, how many transition
(s) (change of logic levels) occur (s) at B during the interval from 0 to 10 ns?
(A) 1 (B) 2
(C) 3 (D) 4
SOLUTION
Due to delays S1 = 2 & S2 = 4 the transitions would occur at time 1, 2 & 4.
Time Input (A) Output (B)
0 1 0
I 1 1 0 Transition
II 2 1 0 Transition
III 4 0 1 Transition
So total 3 transitions
Hence (C) is correct option.
YEAR 2004
Question. 21
The Boolean function x' y' + xy + x' y is equivalent to
252
(A) x' + y' (B) x + y
(C) x + y' (D) x' + y
SOLUTION
Question. 22
In an SR latch made by cross-coupling two NAND gates, if both S and R
inputs are set to 0, then it will result in
(A) Q = 0,Q' = 1 (B) Q = 1,Q' = 0
(C) Q = 1,Q' = 1 (D) Indeterminate states
SOLUTION
253
Hence (C) is correct option.
254
Question. 23
If 73x (in base-x number system) is equal to 54, (in base-y number system), the possible values of x and
y are
(A) 8, 16 (B) 10, 12
(C) 9, 13 (D) 8, 11
SOLUTION
(73)x = (54)y
7x + 3 = 5y + 4
(x', y) 7x + 3 5y + 4
8, 16 59 84
10, 12 73 64
9, 13 64 69
8, 11 59 59
Hence (D) is correct option.
Question. 24
What is the result of evaluating the following two expressions using three-digit floating point arithmetic
with rounding?
(113.+−111.)+7.51
113.+(−111.+7.51)
(A) 9.51 and 10.0 respectively (B) 10.0 and 9.51 respectively
(C) 9.51 and 9.51 respectively (D) 10.0 and 10.0 respectively
SOLUTION
Expression 1
(113.0 + (− 111.) + 7.51
(113.0 − 111.0) + 7.51
2.0 + 7.51
9.51
10 rounded off
Expression 2
113.0 + (− 111.0 + 7.51)
113.0 + (− 103.49)
113.0 − 103.00
10.0 rounded off Hence (D) is correct option
255
Question. 25
A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1
by 0001,...9 by 1001. A combinational circuit is to be diesigned which
takes these 4 bits as input and outputs 1 if the digit $ 5, and 0 otherwise. If
only AND, OR and NOT gates may be used, what is the minimum number
of gates required?
(A) 2 (B) 3
(C) 4 (D) 5
SOLUTION
CKT takes 4 bits as the input so K-Map will have 4 variable so 16 options
are available.
1 digit = 5
0 otherwise
Here for 0 to 4 we have 0 output, from 5 to 9 1 output & for 10 to 15 don’t
care. 1 octed & 2 pounds.
a + bd + bc
a + b (d + c)
Two OR gates
One AND gate
Total 3
Hence (B) is correct option.
Question. 26
Which are the essential prime implicates of the following Boolean
function?
f (a, b , c ) = a' c + ac ' + b ' c
256
(A) a' c and ac' (B) a' c and b ' c
257
(C) a' c only (D) ac' and bc'
SOLUTION
Question. 27
Consider the partial implementation fo a 2-bit counter using T flip flops following the sequence 0-2-3-
1-0, as shown below
SOLUTION
Counter counts the no. of signal inversion change of states. Sequence input is 0 − 2 − 3 − 1 −
0
258
Binary 00 − 10 − 11 − 01 − 00 to generate signals if we XOR gate then it outputs 1 if both are
different.
So output sequence would be. 0 − 1 − 0 − 1 − 0 & the sequence would be counted.
So. X = Q 1 5 Q2
Hence (D) is correct option.
Question. 28
A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT,
NAND, NOR gates only. Assuming that all the inputs are available in both complemented and
uncompensated forms and the delay of each gate is one time unit, what is the overall propagation
delay of the adder? Assume that the carry network has been implemented using two-level AND-OR
logic.
(A) 4 time units (B) 6 time units
(C) 10 time units (D) 12 time units
SOLUTION
Carry of any higher order bit is dependent upon previous order bit addition generated carry.
C out = g 0 + p0 C in
P3 P2 P1 P0 g 3 g 2 g 1 g0
c 3 c 2 c 1 c0
Question. 29
Let A = 11111010 and B 0000 1010 be two 8-bit 2’s complement numbers. Their product in 2’s
complement is
(A) 1100 0100 (B) 1001 1100
(C) 1010 0101 (D) 1101 0101
SOLUTION
259
A = 11111010
Binary = 00000110 = 6
2’s complement represent −ve number So A =− 6
B = 00001010
MSB is 0 so +ve no. decimal 10.
B = 10
A # B =− 6 # 10
=− 60 Binary of 60 = 00111100
2’s complement 11000100
Hence (A) is correct option.
YEAR 2005
Question. 30
260
SOLUTION
f =X:Y:Y:Z
= X:Y+Y:Z
= X:Y+Y:Z
For redundant check we need to draw K map to min terms.
XY (Z + Z ) + (X + X ) : YZ
XYZ + XY Z + XYZ + X YZ
XY + YZ + XZ
Hence (D) is correct option.
Question. 31
The range of integers that can be represented by an a bit 2’s complement
number system is
(A) − 2 n − 1 to (2n−1 − 1) (B) − (2 n − 1 − 1) to (2n−1 − 1)
(C) −2n − 1 to 2n−1 (D) − (2 n − 1 + 1) to (2n−1 − 1)
SOLUTION
n bit 2’s complement system must have corresponding bit binary system.
But to implement +ve & −ve nos. Both
we require MSB to be sign bit.
So maximum magnitude can be 2n−1 − 1 suppose we take n = 4.
261
Using 4 bits.
1 1 1 1,. . . . . .0 0 0 0, . . . . .01 1 1
−7 +7 This would be the range.
Question. 32
The hexadecimal representation of 6578 is
(A) 1AF (B) D78
(C) D71 (D) 32F
SOLUTION
(657)8 = (?)16 Making binary
S S=
0 0 010101111 (IAF)
16
A BBC
Hence (A) is correct option.
Question. 33
The switching expression corresponding to
f (A, B, C , D) = /(1,4,5,9,11,12) is
(A) BC' D' + A' C ' D + AB' D (B) ABC' + ACF + B' C ' D
(C) ACD ' + A' BC' + AC' D' (D) A' BD + ACD ' + BCD'
SOLUTION
f (A, B, C , D) = /(1,4,5,9,11,12) Drawing K map for min terms.
262
BC D + A C D + AB D
So min terms are
BC D + A CD + AB D
Hence (A) is correct option.
Question. 34
Consider the following circuit involving a positive edge triggered D -FF.
Consider the following timing diagram. Let Ai represent the logic level on
the line A in the i − th clock period.
SOLUTION
263
0 1 0 1 A0' A0'
1 1 0 1 A1' A0'
2 0 0 1 A2' A1'
3 1 0 1 A3' A1'
4 1 0 1 A4 ' A3'
5 0 0 1 A5' A4 '
Question. 35
The following diagram represents a finite state machine which takes as input a binary number from the
least significant bit
SOLUTION
Question. 36
Consider the following circuit
The flip-flops are positive edge triggered DFFs. Each state is designated as a two bit string Q0, Q1. Let
the initial state be 00. The state transition sequence is
(A) 00 " 11 " 01 (B) 00 " 11
A
BBBBBBBC A BBBC
(C) 00 " 10 " 01 " 11 (D) 00 " 11 " 01 " 10
A BBBBBBBBBBC A BBBBBBBBBBC
SOLUTION
Truth table for DFF
CP D Qn+1 Action
0 X Qn No change
1 0 0 Reset
1 1 1 Set
D here AX + X' Q'
Truth table for ckt
and so on.
265
Hence (D) is correct option.
Question. 37
The decimal number 0.239 # 213 has the following hexadecimal
representation without normalization and rounding off
(A) 0D 24 (B) 0D 4D
(C) 4D 0D (D) 4D 3D
SOLUTION
Sign bit 0
Exponent = 13
Excess 64 = 13 + 64 = 77 = 1001101
Binary of 239
266
We have 8 bits for Mantissa 0 0 1 1 1 1 0 1 So the floating point format.
0 1001101 00111101
0100 1101 0011 1101
4 D 3 D
Hence (D) is correct option.
Question. 38
The normalized representation for the above format is specified as
follows. The mantissa has an implicit 1 preceding the binary (radix) point.
Assume that only 0’s are padded in while shifting a field. The normalized
representation of the above number (0.239 # 213) is
(A) 0A 20 (B) 11 34
(C) 4D D0 (D) 4A E8
SOLUTION
267
Excess 64 exponent
1 0 0 1 0 1 0 = 74
Sign bit = 0
Floating Point Format
0 1001010 11101000
0100 1010 1110 1000
4 A E 8
GAE8
Hence (D) is correct option.
268
YEAR 2006
Question. 39
You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes
only at the negative edge of the clock. Which one of the following circuits (using clocked D flip flops)
will delay the phase of f by 180c ?
SOLUTION
269
So phase shift occurs.
Hence (B) is correct option.
Question. 40
Consider the circuit below. Which one of the following options correctly represents f (x, y, z)?
− − − −
(A) xz + xy + yz (B) xz + xy + yz
−− − −
(C) xz + xy + yz (D) xz + xy + yz
SOLUTION
MVXI
Selects X when Z = 0
Y' when Z = 0
MVX II
Selects (XZ' + Y' Z) when y = 0
X when y = 0 so (XZ' + YZ) Y' + XY
Simplifying = xz' y' + zy' y' + xy
= xz' y' + xy (z + z') + zy'
= xz' y' + xyz + xyz' + zy'(x + x') = xz' y' + xyz + xyz' + xy' z + x' y'
z
= y' z + xy' z + xyz' + xyz + xyz'[a + a = a] = y' z + xz'(y + y') + xy (z + z')
= y' z + xz' + xy
270
Hence (A) is correct option.
Question. 41
Given two three bit numbers a2 a1 a0 and b2 b1 b0 and c, the carry in, the function that represents the
carry generate function when these two numbers are added is
(E) a2 b2 + a1 a1 b1 + a2 a1 a0 b0 + a2 a0 b1 b0 + a1 b2 b1 + a1 a0 b2 b0 + a0 b2 b1 b0
(F) a2 b2 + a2 b1 b0 + a2 a1 b1 b0 + a1 a0 b21 b1 + a1 a0 b2 + a1 a0 b2 b0 + a2 a0 b1 b0
(G) a2 + b2 + (a2 5 b2)[a1 + b1 + (a1 5 b1)(a0 + b0)]
(H) a2 b2 + a2 a1 b1 + a2 a1 a0 b0 + a2 a0 b1 b0 + a1 b2 b1 a1 a0 b2 b0 + a0 b2 b1 b0
SOLUTION
a2 a1 a0 b2 b1 b0 C
0 0 0 0 0 0 0
0 0 1 0 0 1 1
0 1 0 0 1 0
0 1 0 0 1 1
1 0 1 1 0 0
1 0 0 1 0 1
1 1 1 1 1 0
1 1 0 1 1 1
Case I These are the possible value of a 2 a 1 a0 & b 2 b 1 b0 when a2 = 1
c=1
Case II b2 = 1 c = 1 so a 2 + b2
Case III If any 1 of a2 or b2 is 1 a 2 5 b2
then if a1 = 1 c = 1
b1 = 1 c = 1 so a 2 5 b 2 [ a 1 + b1]
Case IV If any of a2 or b2 is 1 & any of a2 or b1 is 1
then if a0 = 1 c = 1 or if b0 = 1 then c = 1 so overall.
a 2 + b 2 + [(a 2 5 b 2){a 1 + b 1 + (a 1 5 b 1)(a 0 + b0)}]
Hence (C) is correct option.
Question. 42
Consider a boolean function f (w, x, y, z). Suppose that exactly one of its inputs is allowed to change at a
time. If the function happens to be true for two input vectors i1 +< w1, x1, y1, x1 > and i2 +< w2, x2, y2, z2
>
271
, we would like the function to remain true as the input changes from i1 to
i2 (i1 and i2 differ in exactly one bit position), without becoming false
momentarily. Let f (w, x, y, z) = /(5,, 711,12,13,15). Which of
the following cube covers of f will ensure that the required property
is satisfied?
(A) wxz, wxy, xyz, xyz, wyz (B) wxy, wxz, wyz
(C) wxyz , xz, wxyz (D) wzy, wyz, wxz, wwxz , xyz, xyz
SOLUTION
Given function f (w, x, y, z) = Σ(5,7,11,12,13,15) draw K-map of the above
function.
Question. 43
We consider addition of two 2’s complement numbers bn − 1 bn −2 .....b0
and an − 1 an −2 ....a0. A binary adder for adding unsigned binary numbers
is used to add the two numbers. The sum is denoted by cn − 1 cn −2 ....c0 and
the carryout by cout . Which one of the following options correctly
identifies the overflow condition?
(B) an − 1 bn − cn − an − 1 bn − 1
(A) cout (an − 1 5 bn−1) 1 1 +cn−1
SOLUTION
272
Binary adder generates C out only if
1 C in 1 0 1
0a 1 1 1
1b 0 1 1
1 C out 1 1 1
C out in this case is Cn−1 generated carry.
C in is Cn−2
So
b ' n − 1 a' n − 1 c n − 2 + b n − 1 a n − 1 c'n−2
f = Cout 5 Cn−1
Hence (C) is correct option.
Question. 44
Consider number represented in 4-bit gray code. Let h3 h2 h1 h0 be the gray code representation of a
number n and let g3 g2 g1 g0 be the gray code of (n + 1) (modulo 16) value of the number. Which one of
the following functions is correct?
E g0 (h1 h2 h1 h0) = /(1,2,3,6,10,13,14,15)
E g1 (h1 h2 h1 h0) = /(4,9,10,11,12,,13,14,15)
E g2 (h1 h2 h1 h0) = /(2,4, 5,6,7,12,,13,15)
E g3 (h1 h2 h1 h0) = /(0,1,6,7, 10,11,12,,13,)
SOLUTION
g3g2g1
Binary h h 3 h 2 h 1 h0 (n + 1) g0
mod 16
0000 0 0000 1 0001
0001 1 0001 2 0011
0010 2 0011 3 0010
0011 3 0010 4 0110
0100 4 0110 5 0111
0101 5 0111 6 0101
0110 6 0101 7 0100
0111 7 0100 8 1100
1000 8 1100 9 1101
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1001 9 1101 10 1111
1010 10 1111 11 1110
1011 11 1110 12 1010
1100 12 1010 13 1011
1101 13 1011 14 1001
1110 14 1001 15 1000
1111 15 1000 0 0000
This gives the solution option (B)
g 1 (h 3, h 2, h 1, h0) = /(4,9,10,11,12,13,14,15)
YEAR 2007
Question. 45
What is the maximum number of different Boolean
functions involving
n Boolean variables? (B) 2n
(A) n2 (D) 2n2
(C) 22n
SOLUTION
Question. 46
How many 3-to-8 line decoders with an enable input are needed to
construct a 6-to-64 line decoder without using any other logic gates?
(A) 7 (B) 8
(C) 9 (D) 10
SOLUTION
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Total output lines required = 64 We need to use 3 to 8 decoders.
So decoders required 648 = 8 decoders for output.
But we need one more decoder i.e for combining result. 8 + 1 = 9 decoders.
Hence (C) is correct option.
Question. 47
Consider the following Boolean function of four variables f (w, x,, y, z) =
/(1,3,4,6,9,11,12,14)
The function is
(I) independent of one variable
(J) independent of two variables
(K) independent of three variables
(L) dependent on all the variables
SOLUTION
f (w, x, y, z) = /m(1,3,4,6,9,11,12,14)
2 qlead
1st qlead xz'
2nd qlead x' z
xz' + x' z xz' + x' z
So independent of 2 variables.
Hence (B) is correct option.
Question. 48
Let f (w, x, y, z) = /(0,4,5,7,8,9,13,15). Which of the following
expressions are NOT equivalent to f ?
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(A) x' y' z + w' xy' + wy' z + xz (B) w' y' x' + wx' y' + xz
(C) w' y' z' + wx' y' + xyz + xy' z (D) x' y' z + wx' y' + w' y
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SOLUTION
f (w, x, y, z) = /m(0,4,5,7,8,9,13,15)
Drawing K-map.
Question. 49
Define the connective* for the boolean variable X and Y as: X * Y
= XY + X' Y'
Let Z = X * Z
Consider the following expression P, Q and R.
P: X = Y * ZQ: Y = X * Z
R: X * Y * Z = 1
Which of the following is TRUE?
(A) only P and Qare valid (B) Only Qand Rare valid
(C) Only P and Rare valid (D) AllP, Q,Rare valid
SOLUTION
Question. 50
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean
function of nvariables. What is the minimum size of the multiplexer needed?
(A) 2n line to 1 line (B) 2n+1 line to 1 line
(C) 2n−1 line to 1 line (D) 2n−2 line to 1 line
SOLUTION
To select 2n lines we need a select function with n bits.
Here with n variables we have (n − 1) select bits thus 2n−1 data lines. So MUX has 2n−1 lines to 1.
Hence (C) is correct option.
Question. 51
In a look-ahead carry generator, the carry generate function Gi and the carry propagate function Pi for
inputs, Ai and Bi are given by
Pi = Ai 5 Bi and Gi = Ai Bi
The expressions for the sum bit S and carry bit Ci+1 of the look ahead carry adder are given by
Si + Pi 5 Ci and Ci + 1Gi + Pi Ci , Where C0 is the input carry.
Consider a two-level logic implementation of the look-ahead carry generator.. Assume that all Pi and Gi
are available for the carry generator circuit and that the AND and OR gates can have any number of
inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator
for a 4-bit adder with S3, S2, S1, S0 and C4 as its outputs are respectively
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(A) 6,3 (B) 10,4
(C) 6,4 (D) 10,5
SOLUTION
Question. 52
The control signal functions of 4-bit binary counter are given below
(where X is “don’t care”)
0 - 1 X Load input
0 - 0 1 Count next
The counter is connected as follows
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Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through
the following sequence
(A) 0,3,4 (B) 0,3,4,5
(C) 0,1,2,3,4 (D) 0,1,2,3,4,5
SOLUTION
From the truth table for the counter ckt we can see that when counter = 1. & load = 0, count next is the
function.
So it would count from 0 to 4 & then clear to 0 & again start if clock input is increasing.
Hence (C) is correct option.
YEAR 2008
Question. 53
In the IEEE floating point representation the hexadecimal value 0x00000000 corresponds to
(A) the normalized value 2−127 (B) the normalized value 2−126
(C) the normalized value +0 (D) the special value +0
SOLUTION
Question. 54
In the karnaugh map shown below, X denoted a don’t care term. What is the nominal form of the
function represented by the karnaugh map
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−− −− −− −− −−−
(A) b .d + a. d (B) a. b + b . d + a.b . d
−− −−− −− −− −−
(C) b .d + a. b. d (D) a. b + b . d + a. d
SOLUTION
Given K-map is
Question. 55
Let a denote number system radix. The only value(s) of r that satisfy
the equation 121 + 11, is/are
(A) decimal 10
(C) decimal 10 and 11
(B) decimal 11
SOLUTION (D) any value> 2
(121)r = (11)r
If r = 10 it is true it can’t be 2 since bit value can’t be 2 then. It is not true for r
= 11
It is true for 3 to 10.
So it is true for r > 2
Hence (D) is correct option.
Question. 56
Give f1, f3 and f in canonical sum of products form (in decimal) for the circuit
281
f1 = /m(4,5,6,7,8) f3 = /m(1,6,15)
f = /m(1,6,8,15)
Then f2 is
(A) /m(4,6) (B) /m(4,8)
(C) /m(6,8) (D) /m(4,6,8)
SOLUTION
Question. 57
− − −− −
If P , Q, R are Boolean variables, (P + Q) (P.Q + P. R) (P. R + Q)
simplifies to
− −
(A) P. Q (B) P. R
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− −
(C) P. Q + R (D) P. R + Q
SOLUTION
S (P + Q ) : (P Q + PR) : (P R + Q)
S (PPQ + PPR + PQ Q + PQR)(P R + Q)
S (P Q + PR + PQ + PQR)(P R + Q)
S (PQ + PR + PQR)(P R + Q)
S [ PQ (1 + R ) + PR](P R + Q)
S P (Q + R)(P R + Q)
S (P P R + PQ )(Q + R)
S PQ : (Q + R)
S PQ + PQR
S PQ (1 + R)
S PQ
Hence (A) is correct option.
YEAR 2009
Question. 58
(1217)8 is equivalent to
(A) (1217)16 (B) (028F)16
(C) (2297)10 (D) (0B17)16
SOLUTION
(vii) (1217)8
(viii) 001010001111SSS
(ix) (028F)1
6 Hence (B) is correct option.
Question. 59
What is the minimum number of gates required to implement the Boolean
function (AB + C) if we have to use only 2-input NOR gates
?
(A) 2 (B) 3
(C) 4 (D) 5
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SOLUTION
AB+C implementation through NOR gate (X + Y ) We require one AND gate & 1 OR
gate
YEAR 2010
Question. 60
The minterm expansion of f (P, Q, R) = PQ + QR + PR is
(A) m 2 + m 4 + m 6 + m1 (B) m 0 + m 1 + m 3 + m5
(C) m 0 + m 1 + m 6 + m1 (D) m 2 + m 3 + m 4 + m5
SOLUTION
Given expression is
f (P, Q, R) = PQ + QR + PR
For min term expansion we add the remaining variables in the expression.
2. PQ (R + R ) + (P + P ) QR + P (Q + Q ) R
3. PQR + PQR + PQR + PQR + PQR + PQR
4. PQR + PQR + PQR + PQ R
5. m 7 + m 6 + m 2 + m4
6. 111 + 110 + 010 + 100
So = m 2 + m 4 + m 6 + m7
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Hence (A) is correct option.
Question. 61
P is a 16-bit signed integer. The 2’s complement representation of P is (F
87B)16. The 2’s complement representation of 8)P is
(A) (C 3D8)16 (B) (187B)16
(C) (F878)16 (D) (987B)16
SOLUTIO
N
P’s 2’s complement.
= (F87B)16 Is
complement= F 87B − 1 =
(F87A)16
In base 16 complement is done by subtracting from 15 i.e F.
= = (0785)16
(0000 01111000 0101)2
1 # 2c + 1 # 2 2 + 1 # 2 7 + 1 # 2 8 + 1 # 2 9 + 1 # 210
= = 1925
8 # P = 8 # 1925 = 15400
Its binary 0011110000101000SSSS
For hexadecimal make pairs of 4 i.e. (3C28)16
2’s complement P = 1100 0011 1101 1000
C 3 D 8
2’s complement of P = (C 3D8)16
Hence (A) is correct option.
Question. 62
The Boolean expression for the output f of the multiplexer shown below is
(A) P 5 Q 5 R (B) P 5 Q 5 R
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(C) P + Q + R (D) P + Q + R
SOLUTION
S1 & so are the select bits which are used to select any 1 of the 4 inputs.
Selection table
S 1 (P) S 0 (Q) Input
0 0 0R
0 1 1R
1 0 2R
1 1 3R
The expression has 3 variables
So K-map
Question. 64
In the sequential circuit shown below, if the initial value of the output Q 1 Q0 is 00, what
are the next four values of Q 1 Q0 ?
286
(A) 11, 10, 01, 00 (B) 10, 11, 01, 00
(C) 10, 00, 01, 11 (D) 11, 10, 00, 01
SOLUTION
There are 2 T-toggle flip flops in the ckt. Truth table for TFF.
CP T Qn+1
0 X Qn Qn previous state
1 0 Qn CP clock pulse
(A) (B)
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(C) (D)
Answer: - (D)
Consider the following circuit involving three D-type flip-flops used in a certain type
of counter configuration.
P
D Q
Clock
Q
Q
D Q
Clock
Q
R
D Q
Clock
Q
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68. If all the flip-flops were reset to 0 at power on, what is the total number of distinct
outputs (states) represented by PQR generated by the counter?
(A) 3 (B) 4 (C) 5 (D) 6
Answer: - (B)
Exp: -
D2
D1 D3 R P Q R
1 0 1 0 0 1 0
2 0 1 1 0 1 1
3 1 0 0 1 0 0
4 0 0 0 0 0 0
69. If at some instance prior to the occurrence of the clock edge, P. Q and R have a
value 0, 1 and 0 respectively, what shall be the value of PQR after the clock
edge?
(A) 000 (B) 001 (C) 010 (D) 011
Answer: - (D)
Exp: -From the Table Shown in the explanation of question 50, if first state is 010 next
State is 011
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YEAR 2013
73. Which one of the following expressions does NOT represent exclusive NOR of x and
y?
Exp:
⊕
⊕
⊕ ⊕y
74. In the following truth table, V = 1 if and only if the input is valid.
Inputs Outputs
D0 D1 D2 D3 X0 X1 V
0 0 0 0 X X 0
1 0 0 0 0 0 1
0 1 0 0 1 1
1 X 1 0 0 1
X X X 1 1 1 1
What function does the truth table represent?
(A) Priority encoder (B) Decoder
(C) Multiplexer (D) Demultiplexer
Ans: (A)
Exp: 4 to 2 priority encoder.
75. The smallest integer than can be represented byan 8-bit number in 2’s
complement form is
(A) -256 (B) -128 (C) -127 (D) 0
Ans: (B)
Exp: − 28 −1 −128. Range is -2(n-1) to +2(n-1)-1
76. A RAM chip has a capacity of 1024 words of 8 bi ts each 8 . The number of
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decoders with enable line needed to construct a
16
Number of chips required = 2 [16 chips vertically with each
291