Olts T1 Ee

TEST ID: 201
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ESE- 2018 (Prelims) - Offline Test Series-Test-1

ELECTRICAL ENGINEERING
SUBJECT: ANALOG AND DIGITAL ELECTRONICS + BASIC ELECTRONICS

ENGINEERING – SOLUTIONS
01. Ans: (c) Step (2):

Sol: The given circuit is a wein-bridge oscillator  VA =–12V, D is OFF  V0 = 0V
The condition for sustained oscillations (or)
the minimum voltage gain required to 03. Ans: (d)
maintain the oscillations in a wein-Bridge Sol: Step (1): KCL at collector node of Q1
oscillator is IRef  I C1  I B1  I B2
R1 C2
AV = 1   ------- (1) [where R1 =  I C1  2I B2
R 2 C1
2I C 2
2R, R2 = R, C1 = C and C2 = 2C in the given  I C2 

circuit]
 2
R
1 f 1
2R 2C
  5 -------- (2)  I C2 1  
R1 R C  
I Re f I Re f 2
 Rf/R1 = 4 ------- (3)   1  1.04
I C2 I0 50
 Rf = 4R1 ------(4)
04. Ans: (b)

02. Ans: (c)
Sol: Step (1):
Sol: Step (1):
fL 2kHz
When Vi = –2V, VA = –12V f Lf    181.818Hz
1  A 1  1000  0.01
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:2: Electrical Engineering
Step (2): 09. Ans: (a)

f Hf  f H 1  A  10. Ans: (d)
 20kHz  1  1000  0.01  220kHz Sol: R
AC
o/p
05. Ans: (b) i/p
Sol:
Gain
11. Ans: (a)

1=AV
AV  R2 
Sol: VH  2Vsat  
2
f  1
R  R 2 
1MHz
 1 
 2  10   2V
Bandwidth = fH = 1MHz 1 9 
1
At fH, Gain of the amplifier, A V 
2 12. Ans: (c)
V0 1 Sol: V0= gain  input voltage
 AV   V
Vi 2  A  Vm sin t (i.e., A  Vm = Vx)
Vi 2
V0    2V dV0
 Vx cos t  
2 2 dt
dV0
SR   Vx 2f
06. Ans: (a) dt max
07. Ans: (b) 100106 = Vx220106

100 5
08. Ans: (b) Vx   V
40 2
Sol: In negative feedback amplifiers
Voltage gain 
13. Ans: (c)
Bandwidth 
Sol: V0= –2(2)= – 4V
Noise 
V0   V0 
I0    
Distortion  2k  1k 
Amplitude fluctuations  = 2  10–3 + 4  10–3
= 6 mA
:3: ESE - 2018 (Prelims) Offline Test Series
14. Ans: (a) V0 = 7.4V + +

Sol: both the diodes are OFF 0.7V
I=0 6V
15V V0
D1 0.7V
0.67k – –
+
3k I – 2.33V
16. Ans: (b)
17. Ans: (d)

D2
R2
Sol: V0   V1  V2 
R1
15. Ans: (c)
V1 – V2 = – 2V
Sol: D  F B
V0 = 5(–2)
Z1  operated in break down region = –10V
Z2  F B then

18. Ans: (a) 23. Ans: (a)

Sol: For negative feedback, gain factor is reduces Sol: The transistor with comparatively small  is
by (1 + A) for shunt-series, Rin is decreased used in power amplifier because to handle
by a factor of (1+A), R0 is increased by a large currents base of the
factor of (1 + A) transistor is made thicker. Hence  should
be small
19. Ans: (a)
Sol: Here the base emitter voltage is greater 24. Ans: (b)
than 0.7 V and the base collector voltage
is less than 0.7 V. Sol:
Hence base emitter junction is in forward 10k
bias and collector-base junction is in Vi 0V
reverse bias. –
output
 Transistor is in forward active region Ii 10k
+
R0
20. Ans: (d) Ri
Sol: Here ICBO doubles for every 100 raise in V 0

Input resistance (R i )  i   0
temperature VBE decreases at the rate of Ii 0.5m
2.5 mV/0C For output resistance, input current 0.5mA is
open circuited & connected 1A current
21. Ans: (d) source at output as show in below figure.
Sol: P  RC coupled amplifier  Audio 10k
0A
Q  Differential amplifier  DC and audio 0V
– Io
0A Vo=0V
R  Cascode amplifier  Video 10k
+
1A
S  Tuned amplifier  Narrow band Ro
22. Ans: (d) V 0

 Output resistance (R o )  o   0
Sol: The oscillation frequency in crystal Io 1
oscillator is determined by the crystal

dimensions. This means that crystal 25. Ans (c)
oscillator frequency depends on all of the Sol: The Common Emitter current gain –
above parameters i.e. thickness of crystal, bandwidth product of a transistor (fT ) is
angle of cut and physical size of crystal defined as the frequency at which Beta of
the transistor falls to unity
gm
Unity gain frequency (fT) =
2  (C   C  ) 31. Ans: (a)
1
Sol: Junction capacitance 
26. Ans: (a) Junction Voltage
Sol: The bias stability of an Emitter-Bias
1 1
Step: C j  
Amplifier circuit improves by decreasing the VS 2
value of RB and increasing the value of RE.
1 1
Linear: C j  
3 VS 3
27. Ans: (d)
1 1
Sol: AV = –gm r01 Diffused = C j  
2.5 V 2.5
 I EE / 2  VA 
S
Vt  I EE / 2 
=
32. Ans: (b)
VA 5
=  = –192.31 Sol: Voltage shunt feed back
Vt 0.026
33. Ans: (b)

28. Ans: (d) 2
 Vgs 
Sol: ID = IDss 1  
Sol: In current series feedback output current is  Vp 
 
proportional to input voltage. Hence it is
Transconductance of (gm) FET is
Transconductance amplifier.
 V 
gm = I D  2I Dss 1  gs 
Vgs 
 Vp   Vp 
29. Ans: (a)
  V 2 I 
Sol: When two pure conductors are added then  1  gs   D 
  Vp  I Dss 
resistivity increases at all time  
30. Ans: (c) 2

gm = I D .I Dss
vp
1.24
Sol:  max  m
E G (eV)
1.24
 m = 0.496 m = 4960 Ao
2.5

34. Ans: (d) 36. Ans: (a)

Sol: Once an SCR is turned on, it will remain so Sol: The auto correlation function of White
until the anode current goes below to Noise is a delta function.
holding current value. (t) 
FT
Pair
1
N0 N
So (t) 
FT
 0
35. Ans: (d) 2 Pair
2
Sol: LED is made by a direct band gap material.
hc 37. Ans: (c)
Eg =
 Sol: Pc = 1.8 KW
The colour of the light has a particular
PC  2
wavelength  according to the band gap PSB   200 W
4
energy of semiconductor material 1.8  103   2
 200 W
4
2 = 4/9

4 2 41. Ans: (b)

   0.666
9 3 Sol: The signal is received using the pre-
%  = 66.66% selection stage, i.e. an RF amplifier. It is
mixed with local oscillator and IF is
38. Ans: (c) generated. It is amplified by the IF amplifier
Sol: modulation index of AM and the amplitude variations are removed by
 = kaAm which is independent of frequency amplitude limiter. Then, it is applied to the
kf Am FM demodulator. The demodulated signal is

FM f 
fm amplified by an audio amplifier.
fm doubled, f is half
PM p = kpAm, independent of frequency 42. Ans: (c)
Sol: Typical Uplink & Downlink frequencies
39. Ans: (b) used in satellite communication are
Sol: For entropy of source Uplink Downlink

6 GHz 4 GHz
S1  log 2 4  2 log 2 2
14 GHz 12 GHz
=2 bits/symbol
30 GHz 24 GHz
For entropy or source
S 2  log 2 16  4 log 2 2
43. Ans: (d)
= 4 bits/symbol
Sol: Flash memory takes more number of
Read/Write cycles
40. Ans: (b)
Sol: If L = 2  Data word length n= 1bit.
Data rate = n fs b/sec
44. Ans: (a)
= fs bits/sec,
Sol: In PLA  both “AND” and “OR”
Where fs is the sampling rate.
programmable
If L = 8  n = 3 bits.
(iii) Represents Fan out
Data rate = 3fs bps.
Since (B.W)  data rate, B.W requirement 45. Ans: (b)
gets tripled. Sol: 2N  (no of digits in sequence) + 1
N: number of flip-flops
2N  5 + 1 X = D4 + D5 + D6 + D7
N=3 Y = D2 + D3 + D6 + D7
So number of flip-flops = 3 Z = D1 + D3 + D5 + D7
46. Ans: (a)
49. Ans: (c)
Sol: Using SOP form
Sol:
Y  A B 1  A B 1  A B  ABB T1 T2
 A B  A B  A B AB
=1 (Vin). T1 = (Vref). T2
Using POS form (1) (1020msec) = (2) T2
Y  A  B  1 A  B  1A  B  A A  B  B T2 = 100msec
= (1) (1) (1) (1) Total time = T1+T2 = 0.3sec
=1
50. Ans: (c)
47. Ans: (b) Sol: Implementation is as shown
Sol: x  y = x y I0
I1
 xy  x y S0
I2
0xy  xy =x +y I3
S0 S1
OR gate I4 Y
I5 S2
S0 S3
I6
S1
48. Ans: (a) I7
S0
Sol: I8
D7 D6 D5 D4 D3 D2 D1 D0 X Y Z
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

51. Ans: (d) r=5 or –1.5 (invalid)

Sol: X  P  Q  R P  Q  R 
53. Ans: (b)
 PQ  PR  PQ  Q  QR  PR  QR
Sol: XOR operation gives output HIGH, when
 Q1  P  P  R  R   PR  PR
odd no. of input variables are HIGH. So, by
 P  R   Q
looking at the truth table. Option 1 and 3 are
correct.
52. Ans: (b)
CD
Sol: 3r 2  r  1  r  4 AB
00 01 11 10
00 1 1
3r 2  r  1  r 2  8r  16
01 1 1
2r 2  7 r  15  0
11 1 1
2r 2  10r  3r  15  0
10 1 1
2r (r  5)  3(r  5)  0
(r – 5) (2r + 3) = 0
: 10 : Electrical Engineering
54. Ans: (a) Q1 is fed as input in Johnson counter

Sol: Cache memory is a very high speed memory
that is placed between the CPU and main 58. Ans: (a)
memory. The cache stocks the copies of the Sol:
data from frequently used main memory clk
locations
Inter leaving: main memory is divided into Q1
two or more sections. The CPU can access

Q2
alternate sections immediately without
waiting for memory to catch up (through Output (f)
wait states)
Output is same as clk
55. Ans: (c)
 The frequency of output is 50MHz
Sol: CMOS inverter is formed by the series
connection of one n-channel and one p-
59. Ans: (c)
channel MOS transistor
Sol: F1.F2 = m(4,6) + d(1, 2, 3, 7)
Whereas transmission gate is formed by the

parallel connection of one p-channel and one (common minterms of F1,F2)
n-channel MOS transistors

F1+F2 = m(0, 1, 2, 3, 4, 6) + d(7)
56. Ans: (a) (F.F2) + (F1+F2) = m(0,1,2,3,4,6)+d(7)
57. Ans: (b) d.0 = 0
Sol: d.d = d
Clk pulse Input Q3 Q2 Q1 1.d = d
0 0 0 0 d+d=d
1 1 1 0 0 1+d=1
2 1 1 1 0 0+d=d
3 1 1 1 1
4 0 0 1 1
5 0 0 0 1
6 0 0 0 0

: 11 : ESE - 2018 (Prelims) Offline Test Series
60. Ans: (c) 63. Ans: (a)

Sol: the time taken for SIPO is Sol: Given A + A B + A B C
T1 = NT
= A (1 + B + B C) = A
The time taken for SISO is
No NAND gate is required to implement the
T2 = (2N–1) T
expression
T2–T1 = (N–1) T
64. Ans: (d)

61. Ans: (c)
Sol:
Sol: (a),(b) are operations Performed when
RESETIN is made low
C I0
(c) is performed when RESET out is made I1
4 to 1 F
high I2 MUX
C I3 S
1 S0
(d) is performed during DMA data transfer
A B
62. Ans: (d)

F  A B C  A B C  A B C  ABC
Sol: 0100 MVI A, 00H
0102 LXI H, 0105H  
F  AC B  B  AC B  B  
0105 OUT 00H
F  AC  AC = A  C
0106 INR A
0107 PCHL
0108 HLT
A  00
HL  0105 01  [00] 02  [00]
A  [00] A  02 A  03
A  01 PC  0105 PC  0105
PC  0105
Infinite Loop


: 13 : ESE - 2018 (Prelims) Offline Test Series
65. Ans: (c) 67. Ans: (c)

Sol: Sol: TRAP has both edge & level sensitive.
Q3 Q2 Q1 Q0
Clock 68. Ans: (c)
0 1 1 0
Sol: Vector Address for RST 4.5 = 4.5  8
= 36
Serial - In
= 0024 H
Serial In = Q1  Q0 69. Ans: (d)

Sol: though oscillations are there when switch is
Serial
CLK Q3 Q2 Q1 Q0 closed, we need to get constant waveform
In
without oscillations (bounce)
0 1 1 0
S
1 1 1 0 1 1 1 Q
2 0 0 1 0 1
3 1 1 0 1 0
A Q
R
66. Ans: (c) Fix ‘S’ at logic ‘1’, connect A to ‘R’ input
Sol: The state diagram to detect the sequence of S-R NAND latch
1011 is given below. When A = 0  R = 0  Q  1  Q = 0
Now, even if A = 1 (due to bounce) i.e R = 1
1/0 0/0  Q remains in previous state i.e., (Q = 0)
0/0
1/0
0/0 A B 0/0 C 1/0 D
1/1
Total no. of states are = 4.

 2 flip flops are required to detect the
sequence 1011

70. Ans: (d) 71. Ans: (a)

Sol: In BJT as temperature increasing Ico Sol: Using A S C I I, we can represent data in
increases So, Ic increases. both numbers and characters
Where in FET, As temperature increases
mobility decreases So ID decreases and as 72. Ans: (a)
temperature increases carrier concentration
73. Ans: (d)
ni increases so ID increases.
So overall ID will not get changed.
74. Ans: (b)
Thermal stability in FET is more than BJT
Sol: The gain of the CE amplifier at low
Parameter variation with temperature change
frequencies depend on the coupling, bypass
is less.
and blocking capacitors and independent of
interelectrode capacitances.
75. Ans: (a)

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TEST ID: 201

ESE- 2018 (Prelims) - Offline Test Series-Test-1

SUBJECT: ANALOG AND DIGITAL ELECTRONICS + BASIC ELECTRONICS

01. Ans: (c) Step (2):

04. Ans: (b)

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Step (2): 09. Ans: (a)

11. Ans: (a)

07. Ans: (b) 100106 = Vx220106

14. Ans: (a) V0 = 7.4V + +

17. Ans: (d)

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18. Ans: (a) 23. Ans: (a)

Sol: Here ICBO doubles for every 100 raise in V 0

22. Ans: (d) V 0

oscillator is determined by the crystal

33. Ans: (b)

30. Ans: (c) 2

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34. Ans: (d) 36. Ans: (a)

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4 2 41. Ans: (b)

kf Am FM demodulator. The demodulated signal is

39. Ans: (b) used in satellite communication are

Sol: For entropy of source Uplink Downlink

47. Ans: (b) Sol: Implementation is as shown

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51. Ans: (d) r=5 or –1.5 (invalid)

54. Ans: (a) Q1 is fed as input in Johnson counter

two or more sections. The CPU can access

n-channel MOS transistors

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60. Ans: (c) 63. Ans: (a)

64. Ans: (d)

62. Ans: (d)

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65. Ans: (c) 67. Ans: (c)

Serial In = Q1  Q0 69. Ans: (d)

Total no. of states are = 4.

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70. Ans: (d) 71. Ans: (a)

75. Ans: (a)

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