Professional Documents
Culture Documents
2018
SESSION
27
Power-‐‑Converter
Techniques
A 0.22-to-2.4V-Input Fine-Grained Fully Integrated
Rational Buck-Boost SC DC-DC Converter Using
Algorithmic Voltage-Feed-In (AVFI) Topology
Achieving 84.1% Peak Efficiency at 13.2mW/mm2
Yang Jiang1, Man-Kay Law1, Pui-In Mak1 and Rui P. Martins1,2
1State-Key
Laboratory of Analog and Mixed-Signal VLSI
University of Macau, Macao, China
2Instituto Superior Técnico, Universidade de Lisboa, Portugal
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 1 of 52
Outline
• Motivation
• Algorithmic Voltage-Feed-In (AVFI) Topology
Power Cell Characterization
Topology Determination
• SC Converter Implementation
Converter architecture
Reference-Selective Bootstrapping Driver
• Measurement Results
• Conclusion
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 2 of 52
Motivation
Wireless Energy VH IoE SoC/SiP
RF Sensor
Harvesters DC Power VDD Processor
Conversion A/D Digital
VL
Requirements: Fully integrated SC converters in bulk CMOS
• Wide conversion range
95
• High efficiency Few-VCR
ηpeak (%)
• Small form factor 85
Multiple-VCR
(≥4)
Fully integrated SC 75
power converter (SCPC) Current S-o-t-A
65
with multiple voltage 10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
10
4
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 3 of 52
Fully Integrated Multiple-VCR SCPCs in bulk CMOS
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 4 of 52
Fully Integrated Multiple-VCR SCPCs in bulk CMOS
95 ISSCC’16 (79)
(14) ISSCC’15
ηpeak (%)
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 5 of 52
Fully Integrated Multiple-VCR SCPCs in bulk CMOS
Target:
95 ISSCC’16 (79) • Rational FVCR
(14) ISSCC’15 • Optimal losses:
ηpeak (%)
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 6 of 52
Outline
• Motivation
• Algorithmic Voltage-Feed-In (AVFI) Topology
Power Cell Characterization
Topology Determination
• SC Converter Implementation
Converter architecture
Reference-Selective Bootstrapping Driver
• Measurement Results
• Conclusion
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 7 of 52
Conventional Topology Based Rational FVCR Design
Hybrid topology: suboptimal parasitic loss & RSSL
Integer VCR Fractional VCR Rational VCR
Hybrid
1:N Y:X X
N+
(Dickson)
Y
(S-P)
(Series-Parallel) (Dickson-SP)
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 8 of 52
Cell Extraction from Existing Dickson Topologies
Unique cell
QFC: mi = 1 configuration
by bi & mi
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 12 of 52
Topology Model for AVOUTFI (boost)
Si,O = Si,I + VIN – biVOUT Algorithmic VOUT feed-in (AVOUTFI) Topology Model
VOUT
bi
-
Si,I Si,O
VIN
Algorithmic Model
VOUT 1+n
=
VIN 1 + Σb1~(n-1)
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 13 of 52
Topology Model for AVOUTFI (boost)
Algorithmic VOUT feed-in (AVOUTFI) Topology Model
Shortcut to
verify min. RSSL
VOUT 1+n
=
Optimal RSSL for VIN 1 + Σb1~(n-1)
AVFI topology
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 14 of 52
Topology Model for AVOUTFI (boost)
DC QFC
TT BB BT TB
C1 C2 Cn-1 Cn Topology
VOUT
b1 b2 bn-1 implementation
- - - with optimal
… parasitic loss?
VIN
DC/QFC DC/QFC DC/QFC DC/QFC
(m1) (m2) (mn-1) (mn)
n-stage AVOUTFI Topology Model
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 15 of 52
Coefficient Algorithm for bi
Level Bounded Rule (LBR) (boost): S1~(n-1),O (VSS, VOUT).
bi algorithm
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 16 of 52
Derivation for mi
(Boost)
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 18 of 52
Coefficient Algorithm for mi
mi algorithm
• Cell-to-cell Q-transfer of
CTOP-CTOP / CBOT-CBOT
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 19 of 52
Summary: Proposed AVOUTFI Topology (Boost)
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 20 of 52
Summary: Proposed AVINFI Topology (Buck)
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 21 of 52
Summary: Proposed AVFI Topology (Buck-Boost)
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 22 of 52
Q-Conduction Loss Comparison
(Proposed) (Existed) (Existed)
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 23 of 52
Parasitic Loss Comparison
(Proposed) (Existed) (Existed)
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 24 of 52
Specific Topology Comparison
3:5 4:3
Liu ISSCC’15 (Hybrid) AVFI Lu ISSCC’15 (SP) AVFI
Q 2Q C1 C2 C3 C4 Q C1 C2 C3 C4 Q C1 C2 C3 Q C1 C2 C3
VOUT VOUT VIN VIN
Φ1 V
Φ1 VIN Φ1 VIN OUT Φ1 VOUT
VSS VSS VSS
VOUT
VOUT VOUT Φ2 VIN
Φ2 VIN Φ2 VIN Φ2 VOUT
VSS VSS VSS
MPAR = 0.63 MPAR ≈ 0.37 MPAR ≈ 0.219 MPAR ≈ 0.047
Le Q C1 C2 C3 C4 Teh Q 2Q C1 C2 C3
AVFI Q C1 C2 C3 C4
VIN VIN VIN
ISSCC’13 Φ1 ISSCC’16 Φ1 VOUT Φ1 VOUT
5:2 (Hybrid) VOUT (Custom.) VSS VSS
VOUT VIN
Φ2 Φ2 VOUT Φ2 VOUT
VSS VSS VSS
MPAR = 0.176 MPAR = 0.104 MPAR = 0.08
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 25 of 52
Simulation Results & Comparison
η (%)
(Proposed)
(Existed)
0.2V < VIN < 2.3V, VOUT = 1V, Iload = 20mA RSSL: AVFI = NSC = RSC < S-P
CBot-par = 8%, Acap = 1mm2 RPAR: AVFI < NSC ≤ RSC < S-P
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 26 of 52
Outline
• Motivation
• Algorithmic Voltage-Feed-In (AVFI) Topology
Topology Generation
Coefficients Selection
• SC Converter Implementation
Converter architecture
Reference-Selective Bootstrapping Driver
• Measurement Results
• Conclusion
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 27 of 52
Converter Overview
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 31 of 52
Adaptive Driving Behaviors for ST3 (Buck)
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 32 of 52
Adaptive Driving Behaviors for ST3 (Buck)
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 33 of 52
Adaptive Driving Behaviors for ST3 (Buck)
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 34 of 52
Reference-Selective Bootstrapping Driver (RSBD) Oprt.
RSBD Three-state Dual Phase Operations for ST3
States Buck VIN > VOUT (VDD) Boost VIN < VOUT (VDD) Disable
(for T3) (en = 1, lv = 0) (en = 1, lv = 1) (en = 0)
SP VGP,on = Vpass − VDD VGP,off = VDD (buck)
Φ1 VGP,dis = VIN
SN VGN,off = VDD VGN,on = Vpass + VDD
VGN,dis = VDD
Vn if Vn > Vn+1
SP VGP,off = VGP,off = VDD
Vn+1 if Vn+1 > Vn (boost)
Φ2
Vn if Vn < Vn+1 VGP,dis = VDD
SN VGN,off = VDD VGN,off =
Vn+1 if Vn+1 < Vn VGN,dis = VSS
Vpass VDD < Vpass < VIN_MAX VIN_MIN < Vpass < VDD --
• 2 enables states (buck/boost) + 1 disable state.
• Dual phase (Ф1,2) ST3 on/off in enable states.
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 35 of 52
Proposed RSBD Circuit (for ST3)
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 36 of 52
RSBD for ST3 (Buck): Ref. Selection for ΦOFF Ctrl.
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 37 of 52
RSBD for ST3 (Buck): ФOFF Ctrl.
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 38 of 52
RSBD for ST3 (Buck): Int. Driving for Vpass Sensing
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 39 of 52
RSBD for ST3 (Buck): ΦON Ctrl.
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 40 of 52
RSBD for ST3 (Buck): Φdis Ctrl.
enP enP
Buck Φdis
enN enN V VIN
VGP,dis
enP enP
Vi+1 Vi
VGP0 enN enN VOUT
0°
Vi_0 Vi+1_0 clk0 clk180
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 42 of 52
Chip Implementation
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 43 of 52
Measured Conversion Efficiency over VIN (VOUT = 1V)
η (%)
70
6:5 7:5 4:3 80 2:5 1:3
5:3 2:1 40 3:4
5:3 1:1 75 1:4
60 1:5
7:4 70 1:6
50 60 70 80 20
2:1 1:7
50
0 10 20 30 40 0 10 20 30
POUT (mW) POUT (mW)
• Max. POUT > 80mW with buck 2:1
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 45 of 52
Measured Load Transient Waveforms
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 46 of 52
Performance Summary and Comparison
D. Lutz C. K. Teh M. Saadat X. Hua J. Jiang
This work
ISSCC'16 ISSCC'16 ASSCC'15 CICC'15 JSSC'17
Technology 65nm CMOS 0.35μm HVCMOS 65nm CMOS 0.25μm CMOS 65nm CMOS 130nm CMOS
Conv. type Buck-Boost Buck-Boost Buck-Boost Buck-Boost Buck-Boost Buck
No. of VCR 11 buck + 13 boost 8 buck + 9 boost 5 buck + 1 boost 4 buck + 4 boost 3 buck + 3 boost 6 buck
Integrated Cfly MOS + MIM MIM MOS + off-chip 1μF MIM N/R Off-chip 4μF
VIN [V] 0.22 ~ 2.4 2 ~ 13 0.85 ~ 3.6 0.6 ~ 2.4 0.5 ~ 3.3 1.6 ~ 3.3
VOUT [V] 0.85 ~ 1.2 5 0.1 ~ 1.9 1.2 ~ 1.5 1 0.5 ~ 3
IOUT_MAX [mA] 80.1 4 10 0.1 0.0033 120
Buck: 84.1 Buck: 81.5 Buck: 95.8
ηpeak [%] 76 70.4 91
Boost: 83.2 Boost: 70.9 Boost: 90.5
P-den@ηpeak Buck: 13.2 *Buck: 0.96
2 N/R *0.062 *0.0069 N/A
[mW/mm ] Boost: 10.2 *Boost: 0.15
*
Estimated from the corresponding literature
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 47 of 52
Performance Summary and Comparison
D. Lutz C. K. Teh M. Saadat X. Hua J. Jiang
This work
ISSCC'16 ISSCC'16 ASSCC'15 CICC'15 JSSC'17
Technology 65nm CMOS 0.35μm HVCMOS 65nm CMOS 0.25μm CMOS 65nm CMOS 130nm CMOS
Conv. type Buck-Boost Buck-Boost Buck-Boost Buck-Boost Buck-Boost Buck
No. of VCR 11 buck + 13 boost 8 buck + 9 boost 5 buck + 1 boost 4 buck + 4 boost 3 buck + 3 boost 6 buck
Integrated Cfly MOS + MIM MIM MOS + off-chip 1μF MIM N/R Off-chip 4μF
VIN [V] 0.22 ~ 2.4 2 ~ 13 0.85 ~ 3.6 0.6 ~ 2.4 0.5 ~ 3.3 1.6 ~ 3.3
VOUT [V] 0.85 ~ 1.2 5 0.1 ~ 1.9 1.2 ~ 1.5 1 0.5 ~ 3
IOUT_MAX [mA] 80.1 4 10 0.1 0.0033 120
Buck: 84.1 Buck: 81.5 Buck: 95.8
ηpeak [%] 76 70.4 91
Boost: 83.2 Boost: 70.9 Boost: 90.5
P-den@ηpeak Buck: 13.2 *Buck: 0.96
2 N/R *0.062 *0.0069 N/A
[mW/mm ] Boost: 10.2 *Boost: 0.15
*
Estimated from the corresponding literature
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 48 of 52
Benchmarking with Fully Int. SCPCs (No. of VCR ≥ 4)
SC DC-DC w/ VCR ≥ 4 in bulk CMOS
100 Bulk CMOS
(Number of VCR labeled in bracket)
Buck-Boost
95 Buck Boost
(79) Ferro-cap
(4)
90 HD-MIM
(14) (45) This Work Buck-Boost
85 (16) x13 (24)
(4) HD-MIM + TriGate
(17) Buck
80 [Lutz ISSCC’16] (4) HD-MIM
(4) Ferro-cap
75 (8) Buck
(117) (5) (8) SOI
(4) SOI
70 (6) Buck
Boost
65
-3 -2 -1 0 1 2 3 4
10 10 10 10 10 10 10 10
Power density @ ηpeak (mW/mm2)
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 49 of 52
Outline
• Motivation
• Algorithmic Voltage-Feed-In (AVFI) Topology
Topology Generation
Coefficients Selection
• SC Converter Implementation
Converter architecture
Reference-Selective Bootstrapping Driver
• Measurement Results
• Conclusion
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 50 of 52
Conclusion
AVFI topology
• Systematic topology design technique
• Rational FVCRs
• Optimal RSSL & ∆VCB
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 51 of 52
Acknowledgement
© 2018 IEEE Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI)
International Solid-State Circuits Conference Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2 52 of 52
A 10MHz Time-Domain-Controlled Current-Mode
Buck Converter with 8.5% to 93% Switching
Duty Cycle
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 1 of 27
Contents
• Introduction
• Time-Domain-Controlled Current Mode Buck Converter
• Implementation Details
• Experimental Results
• Conclusion
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 2 of 27
Contents
• Introduction
• Time-Domain-Controlled Current Mode Buck Converter
• Implementation Details
• Experimental Results
• Conclusion
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 3 of 27
Current Mode Buck Converter – Conventional
IL
① Fast transient response
VIN MP VSW VOUT
L ② Simple freq. compensation
IL RL Type-II compensation network
COUT
Gate
Driver MN ③ Still large silicon area and power
Ri
③ Inductor current sensor
Sensitive to noise
VPWM
VRAMP Switching freq. limited
① ④
_
④ Sub-harmonic oscillation
Q R Slope compensation required
VC
S VCLK EA
⑤ R1
② VREF ⑤ Limited duty cycle due to
C1 comparator delay
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 4 of 27
Motivation of Time-Domain Current-Mode Control
• Introduction
• Time-Domain-Controlled Current Mode Buck Converter
• Implementation Details
• Experimental Results
• Conclusion
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 6 of 27
Proposed Architecture
• Time-domain control
– Voltage information converted to the
phases of CLKSET and CLKRST
– Voltage-controlled oscillator (VCO)
Output phase = control voltage
– Voltage-controlled delay line (VCDL)
Output phase ∝ control voltage
+ −
( )=
− −
=
+ ( − )
COUT
+ Gate RL
MN
− Driver
VPWM
KVCO2
CLKRST
( RST)
VCO2
PD VREF
VCDL KVCO1
CLKSET
( SET)
KVCDL
VCO1
-1
• Conventional • Proposed
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 11 of 27
Sub-Harmonic Oscillation with Current-Mode Control
• Conventional IL
Ipeak
−
∆ = ∆ = ∆
a IIND,orig
Current b S2
perturbation
∆ = ∆ =− ∆ at t=0 S1 IIND,pert
IL(0)
∆ >∆ if duty > 50% Current
IL(Tsw) perturbation
t
Sub-harmonic oscillation at t=TSW
Tsw
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 12 of 27
Sub-Harmonic Oscillation with Current-Mode Control
• Proposed time-domain
∆ = ∆
= + − ∆
∆ = ∆
= − ∆
No sub-harmonic oscillation
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 13 of 27
Contents
• Introduction
• Time-Domain-Controlled Current Mode Buck Converter
• Implementation Details
• Experimental Results
• Conclusion
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 14 of 27
Fully Differential Implementation
IL
VIN MP VSW VOUT
L
COUT
Gate RL
Driver MN
VPWM
KVCO2
CLKRST
VCO2
PD VREF
VCDL KVCO1
CLKSET
KVCDL
VCO1
-1
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 16 of 27
Input Offset of GM
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 17 of 27
Phase Detector
• PD = edge detector + SR-latch + cycle slip detector
– Cycle slip detector
Phase difference < 0 Duty = 0%
Phase difference > 2π Duty = 100%
SET
PWM
RST
SET RST
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 18 of 27
Contents
• Introduction
• Time-Domain-Controlled Current Mode Buck Converter
• Implementation Details
• Experimental Results
• Conclusion
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 19 of 27
Chip Microphotograph
VOUT=1V
VPWM 100ns
57ns Duty=57%
IIND
Input 1.8-V
VOUT=1.69V
Output 0.15~1.69-V
VPWM 100ns
Duty cycle 8.5~93-%
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 24 of 27
Performance Comparison
[1] VLSI 2012 [2] JSSC 2011 [3] JSSC 2015 This work
Technology 350-nm CMOS 350-nm CMOS 65-nm CMOS 65-nm CMOS
Voltage-domain Voltage-domain Time-domain Time-domain
Control scheme
current mode current mode voltage mode current mode
VIN (V) 2.7~3.6 2.7~4.2 1.8 1.8
VOUT (V) 2 0.5~2.6 0.6~1.5 0.15~1.69
Maximum IOUT (A) 0.6 0.5 0.6 0.6
Switching frequency (MHz) 1 5 11~25 10
Inductor (μH) 4.7 1 0.22 0.22
Capacitor (μF) 10 4.7 4.7 4.7
Die 3.8 0.54 5 2.118
Area (mm2)
Controller 0.217* 0.148* 0.037 0.036
Peak efficiency (%) 93 91 94 94.9
Load step 400mA / N.A. 200mA / N.A. 500mA / N.A. 480mA / 0.1μs
Load transient
Up 6 6 3 3.5
settling time (μs)
Down 12 8 3.5 3.5
Dynamic voltage Up 3
N.A. N.A. N.A.
scaling (μs) Down 3.5
*Controller size is estimated from the chip microphotograph
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 25 of 27
Contents
• Introduction
• Time-Domain-Controlled Current Mode Buck Converter
• Implementation Details
• Experimental Results
• Conclusion
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 26 of 27
Conclusion
• Time-domain-controlled current-mode buck converter proposed
– Time-domain PI-compensator
Smaller silicon area and power consumption
– Inductor current sensing with VCO
No resistor and wideband amplifier
No sub-harmonic oscillation
– PWM signal generation with phase detector
Wide range of duty cycle and thus wide range of output voltage
© 2018 IEEE
International Solid-State Circuits Conference 27.2 : A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle 27 of 27
An 86% Efficiency SIMO DC-DC Converter
with One Boost, One Buck, and a Floating
Output Voltage for Car-Radio
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 1 of 43
Outline
Introduction
Design Targets
Proposed Architecture
Experimental Results
Conclusion
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 2 of 43
Automotive class-D audio amplifier system
Vbat Vboost
n-channels
VfloatH Vboost
Vbat
VfloatL
Power
Vreg-low Reg Vbat
Management
Level 0
VfloatH
Shift HS Driver Npow-HS
High
Speaker
Analog VPWM Lf
Digital
Processing
Core
and PWM VReg-low Cf
Level
VfloatL
Shift LS Driver
Npow-LS
Low
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 3 of 43
Automotive class-D audio amplifier system
Vbat Vboost
n-channels
VfloatH Vboost
Vbat
VfloatL
Power
Vreg-low Reg Vbat
Management
Level 0
VfloatH
Shift HS Driver Npow-HS
High
Speaker
Analog VPWM Lf
Digital
Processing
Core
and PWM VReg-low Cf
Level
VfloatL
Shift LS Driver
Npow-LS
Low
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 4 of 43
Power management in state-of-the-art car-radio
100 Supplies generated by linear
Datasheet- FDA801
regulators*.
80 Increased pin-count and BoM.
Efficiency (%)
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 6 of 43
Load current profile of the channel drivers in car-radio
4 Ch
2 Ch
1 Ch
Q
80
channel driver
Average:
IAvg= 80 mA
IAvg= 40 mA 40
IAvg= 20 mA
20
IQ= 2 mA
2
TSW time 1 2 4
# of Channels
TSW= Switching period of class-D amplifier
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 7 of 43
Design target
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 8 of 43
Switching frequency of the SIMO dc-dc converter
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 10 of 43
Proposed SIMO Architecture
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 11 of 43
Proposed schematic of the power stage
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 12 of 43
Proposed schematic of the power stage
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 13 of 43
Proposed schematic of the power stage
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 14 of 43
Proposed schematic of the power stage
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 15 of 43
Proposed schematic of the power stage
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 16 of 43
Implementation of the proposed power stage
TSW
IL
T1 T2 T3 T4
t
Vboost +∆1
Vreg-low +∆2 with sync-sw
VL1 and dead-time
Vbat
VfloatH+∆3
Vbat
2
VL2 VfloatL- ∆3
t
- Vth
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 17 of 43
Implementation of the proposed power stage
TSW
IL
T1 T2 T3 T4
t
Vboost +∆1
Vreg-low +∆2 with sync-sw
VL1 and dead-time
Vbat
VfloatH+∆3
Vbat
2
VL2 VfloatL- ∆3
t
- Vth
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 18 of 43
Implementation of the proposed power stage
TSW
IL
T1 T2 T3 T4
t
Vboost +∆1
Vreg-low +∆2 with sync-sw
VL1 and dead-time
Vbat
VfloatH+∆3
Vbat
2
VL2 VfloatL- ∆3
t
- Vth
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 19 of 43
Implementation of the proposed power stage
TSW
IL
T1 T2 T3 T4
t
Vboost +∆1
Vreg-low +∆2 with sync-sw
VL1 and dead-time
Vbat
VfloatH+∆3
Vbat
2
VL2 VfloatL- ∆3
t
- Vth
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 20 of 43
Implementation of the proposed power stage
TSW
IL
T1 T2 T3 T4
t
Vboost +∆1
Vreg-low +∆2 with sync-sw
VL1 and dead-time
Vbat
VfloatH+∆3
Vbat
2
VL2 VfloatL- ∆3
t
- Vth
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 21 of 43
Implementation of the floating output
9
VfloatH Vbat/2 VfloatL
8
Voltage
1.6V 1.8V
7
6
Linear Regulation
5
T1 T2
SIMO ON
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 22 of 43
Schematic of the Regulated Floating Dual-
Slope (RFDS) driver
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 23 of 43
Schematic of the Regulated Floating Dual-
Slope (RFDS) driver
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 24 of 43
Schematic of the Regulated Floating Dual-
Slope (RFDS) driver
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 25 of 43
Schematic of the Regulated Floating Dual-
Slope (RFDS) driver
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 26 of 43
Schematic of the Regulated Floating Dual-
Slope (RFDS) driver
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 27 of 43
Error processor in the proposed SIMO converter
A B
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 30 of 43
Micrograph of the SIMO converter
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 31 of 43
Unique startup sequence of the SIMO converter
Boost Only ON SIMO ON Vboost
6.5V
Vbat =14.4V
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 32 of 43
SIMO converter output response to battery transients
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 33 of 43
Steady-state performance of the SIMO converter
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 34 of 43
Steady-state performance of the SIMO converter
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 35 of 43
Load transient performance of the SIMO converter
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 37 of 43
Impact of the SIMO converter
on car-radio performance
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 38 of 43
Car-radio performance with SIMO converter
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 41 of 43
Conclusion
An automotive-class SIMO dc-dc converter with a battery -
tracking floating, boost and a ground referred buck outputs
is introduced.
The SIMO converter is integrated with a state-of-the-art car-
radio.
The converter offers an efficiency exceeding 80% at the
nominal battery voltages driving up to 4 audio channels.
The performance of the car-radio with SIMO dc-dc converter
and its advantages are presented.
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 42 of 43
Thank You
© 2018 IEEE 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
International Solid-State Circuits Conference 43 of 43
A 97% High-Efficiency 6μs Fast-Recovery-
Time Buck-Based Step-Up/Down Converter
with Embedded 1/2 and 3/2 Charge-Pumps
for Li-Ion Battery Management
Min-Woo Ko1, Ki-Duk Kim1, Young-Jin Woo2, Se-Un Shin1, Hyun-Ki Han,
Yeunhee Huh1, Gyeong_Gu Kang1, Jeong-Hyun Cho1, Sang-Jin Lim1, Se-
Hong Park1, Hyung-Min Lee3
and Gyu-Hyeong Cho1
1Korea Advanced Institute of Science and Technology, Daejeon, Korea
2Siliconworks, Daejeon, Korea
3Korea University, Seoul, Korea
© 2018 IEEE 27.4: A 97% High-Efficiency 6μs Fast-Recovery-Time Buck-Based Step-Up/Down Converter
International Solid-State Circuits Conference with Embedded 1/2 and 3/2 Charge-Pumps for Li-Ion Battery Management 1 of 28
Outline
Motivation
Measurement Results
Conclusion
© 2018 IEEE 27.4: A 97% High-Efficiency 6μs Fast-Recovery-Time Buck-Based Step-Up/Down Converter
International Solid-State Circuits Conference with Embedded 1/2 and 3/2 Charge-Pumps for Li-Ion Battery Management 2 of 28
Motivation
Energy density characteristic of various batteries
4.2
4.0
3.8 Required Regulated
Voltage (V) Supply Voltage
3.6
3.4
3.2 Step-Down Step-Up
3.0 Mode Mode Application
2.8 Circuits
2.6
Li-ion
Battery
100 80 60 40
State-Of-Charge (%)
20 0 [Ref : Ju, ISSCC 2017]
© 2018 IEEE 27.4: A 97% High-Efficiency 6μs Fast-Recovery-Time Buck-Based Step-Up/Down Converter
International Solid-State Circuits Conference with Embedded 1/2 and 3/2 Charge-Pumps for Li-Ion Battery Management 4 of 28
Prior Arts
[ Zheng, ISSCC 2010 ] < Pros >
DTS
Well-known buck-
VX VY VOUT
boost topology
VBAT D'TS
S1 S3
Simple buck/boost
VBAT S2 S4 b) Pseudo-buck mode mode control
D'TS
< Cons >
VBAT DTS Poor efficiency
a) Conventional non-inverting buck- (60%~90%)
boost converter
c) Pseudo-boost mode
Slow transient
© 2018 IEEE 27.4: A 97% High-Efficiency 6μs Fast-Recovery-Time Buck-Based Step-Up/Down Converter
International Solid-State Circuits Conference with Embedded 1/2 and 3/2 Charge-Pumps for Li-Ion Battery Management 5 of 28
Prior Arts
[ Ju, ISSCC 2017 ] < Pros >
DTS
Superior efficiency
VX VOUT
(86%~96%)
VBAT D'TS
S1
S3 Suitable for Li-Ion
VBAT S2 b) Step-down mode battery application
+ VBAT -
S4
D'TS DTS < Cons >
VBAT Voltage stress
a) Flying-Capacitor Buck-Boost D'TS problem
(FCBB)
c) Step-up mode
Slow transient
© 2018 IEEE 27.4: A 97% High-Efficiency 6μs Fast-Recovery-Time Buck-Based Step-Up/Down Converter
International Solid-State Circuits Conference with Embedded 1/2 and 3/2 Charge-Pumps for Li-Ion Battery Management 6 of 28
Key Concept
Step-up
VX VOUT
Step-down
3VBAT/2 VBAT VBAT/2
S4 S3
S7 S6
© 2018 IEEE 27.4: A 97% High-Efficiency 6μs Fast-Recovery-Time Buck-Based Step-Up/Down Converter
International Solid-State Circuits Conference with Embedded 1/2 and 3/2 Charge-Pumps for Li-Ion Battery Management 8 of 28
Operation Principles
Step-down mode : Charging-phase
ɸc(charging) T
S1 VX=VBAT VOUT ɸc ɸd
+
1/2VBAT S5 DT
VBAT - +
S2 1/2VBAT IL
- VBAT VOUT
S4 S3
S7 S6 VBAT/2
VX,VOUT
Inductor : Energized
ɸd(down) T
VX=VBAT/2 VOUT ɸc ɸd
S1 +
1/2VBAT S5 DT
VBAT - +
S2 1/2VBAT IL
- VBAT VOUT
S4 S3
S7 S6 VBAT/2
VX,VOUT
Inductor : De-energized
ɸc(charging) T
S1 VX=VBAT VOUT ɸc ɸu
+
1/2VBAT S5 DT
VBAT - +
S2 1/2VBAT 3VBAT/2 IL VOUT
-
S4 S3 VBAT
S7 S6
VX,VOUT
Inductor : De-energized
ɸu(up) T
VX= 3VBAT/2 VOUT ɸc ɸu
S1 +
1/2VBAT S5 DT
VBAT - +
S2 1/2VBAT 3VBAT/2 IL VOUT
-
S4 S3
S7 S6
VX,VOUT
Inductor : Energized
Step-
−( ) Buck-like feature in
Up −
Proposed both step-up and
Step- step-down mode
Down +
© 2018 IEEE 27.4: A 97% High-Efficiency 6μs Fast-Recovery-Time Buck-Based Step-Up/Down Converter
International Solid-State Circuits Conference with Embedded 1/2 and 3/2 Charge-Pumps for Li-Ion Battery Management 13 of 28
Switch Size Optimization
IL ICF1, ICF2
T
ILT/4 when D is 0.5
ɸd S1 IL
CF1 βR
S
0.5T
VBAT ICF1 2
IL t
CF2
ICF2
IL
βR βR IS1
S7 S6
αR IS1 t
IL
DT
ɸc S5 ICF1, ICF2 t
CF1
βR
VBAT IL IL
CF2 ILT when D is 1
IS1
S4 βR
S7 S6 t
2R
Size optimization
ɸ1
Cf1 ɸ5 Hysteretic control
VBAT
ɸ2 Cf2
ɸ4 ɸ3
VFB :
ɸ7 ɸ6 output voltage
ɸ1~7 Gm information +
current ripples
A
DTC Pi
P
Control VFB information
&Gate d Edge Detector VOUT_D
Pu VREF
Driver Logic Differentiator
CLK
Reset Controller
© 2018 IEEE 27.4: A 97% High-Efficiency 6μs Fast-Recovery-Time Buck-Based Step-Up/Down Converter
International Solid-State Circuits Conference with Embedded 1/2 and 3/2 Charge-Pumps for Li-Ion Battery Management 16 of 28
Detailed Operation
Step-down mode BS VX VOUT
IL ɸc ɸd ɸ4 ɸ3
ɸ7 ɸ6
ɸ1~7 Gm
A
DTC Pi Control VFB
VBAT P VOUT_D
VX 1/2VBAT
&Gate d
Driver
Pu
Logic
Edge Detector
VREF
Differentiator
CLK
Reset Controller
VFB
Upper Boundary Reference boundary :
VOUT_D VREF VFB Charging-phase
VOUT_D
VREF Upper boundary :
Down-phase
© 2018 IEEE 27.4: A 97% High-Efficiency 6μs Fast-Recovery-Time Buck-Based Step-Up/Down Converter
International Solid-State Circuits Conference with Embedded 1/2 and 3/2 Charge-Pumps for Li-Ion Battery Management 17 of 28
Detailed Operation
Step-up mode BS VX VOUT
IL ɸc ɸu ɸ4 ɸ3
ɸ7 ɸ6
ɸ1~7 Gm
VBAT P VOUT_D
VX &Gate d
Driver
Pu
Logic
Edge Detector
VREF
Differentiator
CLK
Reset Controller
RESET RESET ɸ1
Cf1 ɸ5
IL ɸ4 ɸ3
ɸ7 ɸ6
ɸ1~7 Gm
A
3/2VBAT DTC Pi
P
Control VFB
VX VBAT &Gate d
Driver
Pu
Logic
Edge Detector
VREF
VOUT_D
Differentiator
1/2VBAT CLK
Reset Controller
© 2018 IEEE 27.4: A 97% High-Efficiency 6μs Fast-Recovery-Time Buck-Based Step-Up/Down Converter
International Solid-State Circuits Conference with Embedded 1/2 and 3/2 Charge-Pumps for Li-Ion Battery Management 19 of 28
Differentiator
BS VX VOUT
Cf1 ɸ5
ɸ1
VBAT
ɸ2 Cf2
ɸ4 ɸ3
ɸ7 ɸ6
ɸ1~7 Gm
A
DTC Pi Control VFB
P VOUT_D
&Gate d Edge Detector
Pu VREF
Driver Logic Differentiator
CLK
Reset Controller
© 2018 IEEE 27.4: A 97% High-Efficiency 6μs Fast-Recovery-Time Buck-Based Step-Up/Down Converter
International Solid-State Circuits Conference with Embedded 1/2 and 3/2 Charge-Pumps for Li-Ion Battery Management 20 of 28
Chip Micrograph
96
92
90.4%
30 200 400 600 800 1000
Load current (mA)
VOUT = 3.4V
Max. Efficiency of 97.0% at VBAT=3.8V with ILOAD=200mA
Min. Efficiency of 90.4% at VBAT=2.7V with ILOAD=30mA,
© 2018 IEEE 27.4: A 97% High-Efficiency 6μs Fast-Recovery-Time Buck-Based Step-Up/Down Converter
International Solid-State Circuits Conference with Embedded 1/2 and 3/2 Charge-Pumps for Li-Ion Battery Management 25 of 28
Comparison to Prior Works
[1] ISSCC ‘11 [2] ISSCC ‘12 [3] TPE ‘16 [4] ISSCC ‘17 This work
Process 0.5µm CMOS 0.18µm CMOS 0.35µm CMOS 0.18µm BCD 0.18µm BCD
Topology Buck-Boost Buck-Boost Buck-Boost FCBB FUDC
4.7µH / 22µF 2.2µH / 10uF
Inductor/Capacitor 2.2µH / 10µF 1µH / 33µF 1µH / 10µF
(10µF*) (2×20µF*)
Input Voltage (V) 3 – 5.5 2.7 – 5.5 2.5 - 5 2.7 - 4.2 2.7 – 4.2
Output Voltage (V) 3.6 0-5 3.3 3.4 3.4
Load current range (A) 0.6 – 1.2 0.1 – 2.0 0.01 – 0.4 0.25 – 2.0 0.03 – 1.0
Switching frequency 2MHz 2.5MHz ≤1.66MHz 1MHz 1MHz
Continuous current
supply
No No No No Yes
Max: 90.7% Max: 91% Max: 98.1%** Max: 96.6% Max: 97.0%
Efficiency
Min: 61% Min: 81% Min: 80.4% Min:86.1% Min: 90.4%
Recovery 50µs / 50µs 112µs / - 6µs / 12µs
Time @ VIN = 4.2V @ VIN = 4.2V @ VIN = 4.2V
Load - -
Transien
(Within 1% of (10mA→400mA) (500mA→1000m (0mA → 700mA)
VOUT) (400mA→10mA) A) (700mA → 0mA)
t
Undershoot / 50mV / 50mV 200mV / -
overshoot
- -
@ VIN = 5V @ VIN = 4.2V
100mV / 150mV
* the value of flying capacitors **measured at very low switching frequency
© 2018 IEEE 27.4: A 97% High-Efficiency 6μs Fast-Recovery-Time Buck-Based Step-Up/Down Converter
International Solid-State Circuits Conference with Embedded 1/2 and 3/2 Charge-Pumps for Li-Ion Battery Management 26 of 28
Conclusion
The FUDC is a buck-boost converter, but always operates in
the buck mode
- Conventional non-inverting buck-boost : RHP-zero exists at boost mode
Reducing design complexity
Better transient performance (6µs settling)
© 2018 IEEE 27.4: A 97% High-Efficiency 6μs Fast-Recovery-Time Buck-Based Step-Up/Down Converter
International Solid-State Circuits Conference with Embedded 1/2 and 3/2 Charge-Pumps for Li-Ion Battery Management 27 of 28
Thank you
© 2018 IEEE 27.4: A 97% High-Efficiency 6μs Fast-Recovery-Time Buck-Based Step-Up/Down Converter
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Paper 27.5
Overall Architecture
Measurement Results
Conclusions
© 2018 IEEE
27.5: A 95.2% Efficiency Dual-Path Step-Up Converter with Continuous Output Current Delivery and Low Voltage Ripple 2 of 26
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Motivation
܂܃۽܄
• M(D) = = (0 D 1) VIN < VOUT
܄۷ۼ ି۲
t
© 2018 IEEE
27.5: A 95.2% Efficiency Dual-Path Step-Up Converter with Continuous Output Current Delivery and Low Voltage Ripple 5 of 26
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Conventional Boost Converter (CBC)
IL L RDCR VX ID VOUT IL ID Φ1 Φ2
S2 COUT ILOAD IL,AVG
VIN S1 RESR
LESL
IL,AVG = MILOAD ILOAD
S2 COUT ILOAD
VIN S1 RESR
ΔVOUT LESL t
Discontinuous ID
=ΔVC+ΔVR+ΔVL
VOUT ΔVOUT
Large VOUT Ripple
Large Switching Spike
Performance degradation of loading blocks Switching spike
( large dv/dt )
t
Over-voltage stress on the loading blocks
Large ΔVOUT
© 2018 IEEE
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Proposed Dual-Path Step-Up Converter
S3 S4
IC
CF VF=VOUT-VIN
IL L ID VOUT
S1 S2 S5
VIN COUT ILOAD
܂܃۽܄ ିࡰ
• M(D) = = (0 D 1) VIN < VOUT
܄۷ۼ ି۲
IC
t
• IL is increased
VX
• C-Path delivers the current to the output
t
VOUT
as an additional path
CF is discharged (-∆VCF) t
© 2018 IEEE
27.5: A 95.2% Efficiency Dual-Path Step-Up Converter with Continuous Output Current Delivery and Low Voltage Ripple 9 of 26
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Proposed Dual-Path Step-Up Converter
Operation : Φ2 S1,S3,S5 : OFF state
Φ1 Φ2
S3
IC S4
S2,S4 : ON state
IL
+ΔVCF CF t
IL L VX S2 S5 ID VOUT ID L-Path
ILOAD
VIN S1 L-Path COUT t
Charge Balance
IC
t
• IL is decreased
VX
• L-Path delivers the current to the output
t
VOUT
CF is charged (+∆VCF)
Charge balance on CF t
© 2018 IEEE
27.5: A 95.2% Efficiency Dual-Path Step-Up Converter with Continuous Output Current Delivery and Low Voltage Ripple 10 of 26
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Proposed Dual-Path Step-Up Converter
CBC DPUC
1.9 IL
1.7 CBC: MILOAD
1.5
Normalized IL
(= IL/ILOAD)
1.3
Small IL
1.1 t
0.9 ID C-Path L-Path
0.7 DPUC: (M-0.5) ILOAD
0.5
1 1.2 1.4 1.6 1.8 2
M Conversion ratio : VOUT/VIN Continuous ID
t
VOUT
• IL = (M-0.5) ILOAD ΔVout
Reduced IL by factor of (M-0.5)
Small ΔVOUT
t
© 2018 IEEE
27.5: A 95.2% Efficiency Dual-Path Step-Up Converter with Continuous Output Current Delivery and Low Voltage Ripple 11 of 26
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Top Structure
S3 VZ S4
: LDMOS
: CMOS
VS3 VS2 VF CF VS4
L VX S2 S5 VOUT
VY ILOAD
VIN VS1 S1 VS5 COUT
RS RF1
Current Sensor
CLK
Φ1 Q S VSEN
Slope Compensator
VFB
R VC
VS1 VS2 VS3 VS4 VS5
CC VREF
Φ1,Φ3,Φ2 2P / 3P Phase CLK RF2
Gate Driver & Level RC
Shifter Mode Selector Φ1
XSM Zero Current VX
Detector VS2
© 2018 IEEE
27.5: A 95.2% Efficiency Dual-Path Step-Up Converter with Continuous Output Current Delivery and Low Voltage Ripple 12 of 26
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Conduction Loss
8 20
18
(= Conduction Loss/IL2 )
(= Conduction Loss/IL2 )
16
6
14
CBC
5 12
CBC
10
4
DPUC 8
DPUC
3
6
2 4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
M Conversion ratio : VOUT/VIN M Conversion ratio : VOUT/VIN
18
(= Conduction Loss/IL2 )
(= Conduction Loss/IL2 )
16
6
14
CBC
5 12
CBC
10
4
DPUC 8
DPUC
3
6
2 4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
M Conversion ratio : VOUT/VIN M Conversion ratio : VOUT/VIN
• When conversion ratio is low, conduction loss
increase again due to large peak capacitor current
© 2018 IEEE
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3-Phase Mode Operation
Operation : Φ1 Operation : Φ2
S3 S4 S3 IC S4
IC
-ΔVCF CF +ΔVCF CF
IL L S5 ID IL L VX S2 S5 ID VOUT
VX VOUT
S2 ILOAD ILOAD
VIN S1 C-Path COUT VIN S1 L-Path COUT
Operation : Φ3
S3 IC S4
CF
IL L RDCR S2 S5 ID VOUT
COUT
VIN S1 L+C Path RESR ILOAD
LESL
© 2018 IEEE
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3-Phase Mode Operation
IC : DPUC(2P)
Start-up DPUC(2P)
: DPUC(3P) 2phase
operation(Φ1,Φ2)
IL
0 t Φ2 TS-Φ1 Φ1 Φ2
Φ3 0 t
TS
Φ1 Φ3 Φ2=0.5TS YES
Φ1 > 0.5TS ?
ID Reduced RMS current DPUC(3P)
NO
& Ripple
3phase operation IL
(Φ1,Φ3,Φ2)
ILOAD Φ1 Φ3 Φ2
t
t Keep Φ2 0.5TS
TS Insert Φ3Φ1-Φ2
• Reduced peak current of C-Path
Despite short Φ1, improved efficiency and voltage ripple
© 2018 IEEE
27.5: A 95.2% Efficiency Dual-Path Step-Up Converter with Continuous Output Current Delivery and Low Voltage Ripple 16 of 26
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3-Phase Mode Operation
8 20
18
Normalized Conduction Loss
(= Conduction Loss/IL2 )
16
6
CBC
DPUC(2P)
CBC
14
CBC
5 12
DPUC(2P)
10
4 DPUC(2P) DPUC(2P)
8
3
DPUC(3P) 6 DPUC(3P)
DPUC(3P) DPUC(3P)
2 4
1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2
M Conversion ratio : VOUT/VIN M Conversion ratio : VOUT/VIN
s
(1- )
vˆ o (s) wz
G vd (s) = = G vd0 2
ˆd(s) s s
+ +1
w 02 Qw 0
IL(t)
(1-D)2 R R ID(t)
wz = = 2
L LM ID,AVG(t) t
D=0.5 D=0.7
DPUC(3P)
CBC
DPUC(2P)
Normalized Positive Zero (= ωz*(L/R) )
• Fabricated in 180nm
BCDMOS Process
© 2018 IEEE
27.5: A 95.2% Efficiency Dual-Path Step-Up Converter with Continuous Output Current Delivery and Low Voltage Ripple 20 of 26
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Measurement
2-Phase Mode (DPUC) CBC
VIN=2.8V
VOUT=4.2V
fSW=1MHz
ILOAD=600mA
VOUT : 2V/Div
VOUT,AC : 50mV/Div
IL : 500mA/Div
VX : 5V/Div
VOUT : 2V/Div
VOUT,AC : 50mV/Div
IL : 500mA/Div
VX : 5V/Div
© 2018 IEEE
27.5: A 95.2% Efficiency Dual-Path Step-Up Converter with Continuous Output Current Delivery and Low Voltage Ripple 21 of 26
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Measurement
DPUC (DCM) Transient Response
VIN=2.8V
VOUT=4.2V
fSW=700kHz
ILOAD=40mA
VOUT : 2V/Div
VOUT,AC : 10mV/Div
IL : 200mA/Div
VX : 5V/Div
DCM (DPUC)
VX Waveform
VX : 2V/Div
© 2018 IEEE
27.5: A 95.2% Efficiency Dual-Path Step-Up Converter with Continuous Output Current Delivery and Low Voltage Ripple 22 of 26
International Solid-State Circuits Conference
Measurement
Power Conversion Efficiency (%) VIN=3V, VOUT=4.2V
100 95.2%
90
80
70 DPUC(3P) w/ RDCR=200mΩ
CBC w/ RDCR=200mΩ
60
0 100 200 300 400 500 600 700 800
ILOAD (mA)
• Even though RDCR is 200mΩ, the DPUC has the peak efficiency of
95.2% which allows the use of a cheaper and smaller size inductor
© 2018 IEEE
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Performance Summary and Comparison
This Work 2014JSSC [1] 2012 TPE [2] TPS6107 [3] 2013JSSC [4]
Process 0.18μm BCD 0.35μm BCD 0.3μm CMOS N/A 0.35μm CMOS
Input voltage 2-4.2V 2.7~4.5V 3.1~3.3V 0.9-5.5V 1.8~3.2V
Output voltage 3-5V 8V 4.5V 1.8-5.5V 3-4.2V
Inductor (L) 4.7μH 10μH 470nH/470nH 1.5-2.5μH 1μH
Capacitor 10μF/10μF* 10μF 20μF 10μF 10μF
1MHz : CCM 1MHz/N
Switching frequency 1MHz 5MHz 1.2MHz
(<1MHz : DCM) (N=2i and i=0-5)
Load current 10-800mA 20-300mA 400mA 5-600mA 5-800mA
Topology DPUC CBC 2-Phase CBC CBC CBC
Output delivery current Continuous Discontinuous Discontinuous Discontinuous Discontinuous
Reduced inductor current YES NO YES NO NO
Ripple Voltage < 15mV 90mV 20mV N/A 80mV
Peak Efficiency (RDCR of L) 95.2% (200mΩ) 90% (11mΩ) N/A 92% 94.8% (9mΩ)
© 2018 IEEE
* The value of flying capacitor
27.5: A 95.2% Efficiency Dual-Path Step-Up Converter with Continuous Output Current Delivery and Low Voltage Ripple 24 of 26
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Conclusions
Dual-Path Structure : Reduced inductor current (IL)
Efficiency improvement by reduced conduction loss
Allow small inductor with large RDCR
Continuous output delivery current (ID)
Reduced output voltage ripple
Reduced switching spikes
Hybrid structure
No limitation of conversion ratio with single flying capacitor
Improved performance in wide conversion ratio by mode selector
Alleviated RHP-zero effect
Easy to design compensator of PWM controller
Improved transient response
© 2018 IEEE
27.5: A 95.2% Efficiency Dual-Path Step-Up Converter with Continuous Output Current Delivery and Low Voltage Ripple 25 of 26
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© 2018 IEEE
27.5: A 95.2% Efficiency Dual-Path Step-Up Converter with Continuous Output Current Delivery and Low Voltage Ripple 26 of 26
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An 87.1% Efficiency RF-PA Envelope-Tracking
Modulator for 80MHz LTE-Advanced Transmitter and
31dBm PA Output Power for HPUE in 0.153μm CMOS
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 1 of 48
Outline
• Motivation of 80MHz High-efficiency ETM
• ET System and AC-coupled ETM Architecture
• ETM Circuit Blocks
– Dual-mode AC Feed-forward Class-AB Linear Amplifier
– Buck-Boost Convertor
– Dual Power Line(DPL) Buck Convertor
• Measurement Results
• Conclusions
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 2 of 48
Outline
• Motivation of 80MHz High-efficiency ETM
• ET System and AC-coupled ETM Architecture
• ETM Circuit Blocks
– Dual-mode AC Feed-forward Class-AB Linear Amplifier
– Buck-Boost Convertor
– Dual Power Line(DPL) Buck Convertor
• Measurement Results
• Conclusions
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 3 of 48
Envelope Tracking Technology - Efficiency
PAE improve > 30%
Efficiency up
• APT ET
• Tracking bandwidth ≥ up-link carrier frequency
• ET enhance intrinsic efficiency of RF-PA and PAE
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 4 of 48
Envelope Tracking Technology- Temperature
Temp. 20% reduction
RF-PA RF-PA
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 9 of 48
Outline
• Motivation of 80MHz High-efficiency ETM
• ET System and AC-coupled ETM Architecture
• ETM Circuit Blocks
– Dual-mode AC Feed-forward Class-AB Linear Amplifier
– Buck-Boost Convertor
– Dual Power Line(DPL) Buck Convertor
• Measurement Results
• Conclusions
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 10 of 48
Why AC-coupled ETM Architecture
Buck regulator
VDD VDD
VDD LBUCK
Vref
VENVP
VPA
VENVN
AC-path AC-path
TX IN TX OUT
PA
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 12 of 48
High-efficiency AC-coupled ETM Strategy
• Increase DC-DC power
and reduce LA power
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 13 of 48
High-efficiency AC-coupled ETM Strategy
• Increase DC-DC power
and reduce LA power
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 14 of 48
High-efficiency AC-coupled ETM Strategy
• Increase DC-DC power
and reduce LA power
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 15 of 48
Proposed Hybrid AC-coupled ETM
L=0.68μH C=4.7μF
BB BB
DBB2 DBB1
TYPE III VCOMP
MP2 MP1
• Buck-Boost fast transient and
BAT H
H
VCTL_P2 VCTL_P1
setting for power switching
DAC VCTL_P1
Controller
LA_OUT - VCTL_P2 VGN
D2S and Level Shifter VCTL_N
VCTL_N
PA +
MN • Dual Power Line High-
efficiency Buck
DAC
BB
L=1μH
ENV_IP
LPF + LA_OUT PA
ENV_IN
-
LPF
R1=1ohm
RLA
TX IN External TX OUT
PA
CLA C1=2.2nF
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 16 of 48
Hybrid AC-coupled ETM ET-Mode
L=0.68μH C=4.7μF
BB BB
DBB2 DBB1
TYPE III VCOMP
MP2 MP1
• An additional Buck-Boost is used
BAT H
H
VCTL_P2 VCTL_P1
to provide the Class-AB LA with
VCTL_P1
an optimized supply voltage
DAC
Controller
LA_OUT - VCTL_P2 VGN
D2S and Level Shifter VCTL_N
PA + VCTL_N
MN
BB
L=1μH the power path VH, VBAT or VBB
ENV_IP
LPF + LA_OUT PA
ENV_IN
-
LPF
R1=1ohm
RLA
TX IN External TX OUT
PA
CLA C1=2.2nF
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 17 of 48
Hybrid AC-coupled ETM ET-Mode
L=0.68μH C=4.7μF
BB BB
DBB2 DBB1
TYPE III VCOMP
MP2 MP1
• An additional Buck-Boost is used
BAT H
H
VCTL_P2 VCTL_P1
to provide the Class-AB LA with
VCTL_P1
an optimized supply voltage
DAC
Controller
LA_OUT - VCTL_P2 VGN
D2S and Level Shifter VCTL_N
PA + VCTL_N
MN
BB
L=1μH the power path VH, VBAT or VBB
ENV_IP
LPF + LA_OUT PA
ENV_IN
-
LPF
R1=1ohm
RLA
TX IN External TX OUT
PA
CLA C1=2.2nF
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 18 of 48
Hybrid AC-coupled ETM ET-Mode
L=0.68μH C=4.7μF
BB BB
DBB2 DBB1
TYPE III VCOMP
MP2 MP1
• An additional Buck-Boost is used
BAT H
H
VCTL_P2 VCTL_P1
to provide the Class-AB LA with
VCTL_P1
an optimized supply voltage
DAC
Controller
LA_OUT - VCTL_P2 VGN
D2S and Level Shifter VCTL_N
PA + VCTL_N
MN
BB
L=1μH the power path VH, VBAT or VBB
ENV_IP
LPF + LA_OUT PA
ENV_IN
-
LPF
R1=1ohm
RLA
TX IN External TX OUT
PA
CLA C1=2.2nF
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 19 of 48
Outline
• Motivation of 80MHz High-efficiency ETM
• ET System and AC-coupled ETM Architecture
• ETM Circuit Blocks
– Dual-mode AC Feed-forward Class-AB Linear Amplifier
– Buck-Boost Convertor
– Dual Power Line(DPL) Buck Convertor
• Measurement Results
• Conclusions
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 20 of 48
Hybrid AC-coupled ETM
L=0.68μH C=4.7μF
VBB
VBAT VODAS Maximum Power
Selection Circuit
• High speed AC Feed-Forward
Buck-Boost
Converter
VBB_P1
VBB_N1
VBB_N2
VBB_P2
VBAT Class-AB Linear Amplifier for
80MHz envelope tracking
VBB
VGP2 VGP1
ᵝ VPWM VODAS DBB2 DBB1
VCOMP
ILPC standard
Analog VCTL_P1
DIG
ISEN_MP1
DPL-Buck ISEN_MP2 Mode PWM/PFM Gate Driver MN
ISEN_MN
Converter
• Dual Power Line High-
DAC
BB
L=1μH efficiency Buck
ENV_IP
LPF + LA_OUT PA
ENV_IN
-
LPF
R1=1ohm
RLA
TX IN External TX OUT
PA
CLA C1=2.2nF
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 21 of 48
Dual-mode AC Feed-forward Class-AB Linear Amplifier
Class-AB Stage
VBB
Gm-AC Vgp
AC Response
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 22 of 48
HGM AC Feed-forward Class-AB Linear Amplifier
Rc1 Cc1
Vgp
Vp2
Rc2 Cc2 VLAout
Vp1 Vgn
Vp1 Rc3 Cc3
Von1
VIN VIP Vgp Vgn
M1 M2 Vctrlp
Vgp Vctrlp Vgn
Vcasn
Vcasn
SMODE1 SMODE2
Von1/2 Vop1/2 Vop1/2
Vop2 Vop1 Von1 Vip Vin Vip
Von2
M5 M6 M3 M4 M7 M8 M9
HBM HGM AC Feed-forward
• High-loop-gain configuration to suppress receiver band noise for FDD-LTE
• AC feed-forward path from M7~M9 to output stage
• Core devices for all the signal paths, cascode I/O devices are used for all
amplifier stages and the Class-AB output stage
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 23 of 48
HBM AC Feed-forward Class-AB Linear Amplifier
Rc1 Cc1
Vgp
Vp2
Rc2 Cc2 VLAout
Vp1 Vgn
Vp1 Rc3 Cc3
Von1
VIN VIP Vgp Vgn
M1 M2 Vctrlp
Vgp Vctrlp Vgn
A B Vcasn
Vcasn
SMODE1 SMODE2
Von1/2 Vop1/2 Vop1/2
Vop2 Vop1 Von1 Vip Vin Vip
Von2
M5 M6 M3 M4 M7 M8 M9
HBM AC Feed-forward
• Push the dominant pole at node A/B to higher frequency
• 3dB frequency above 100MHz
• For all above intra-band 2CCA (40MHz) applications (TD-LTE)
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 24 of 48
Class-AB Output Stage Auto-detect Selection (ADS)
VBB
VBB
Vgp
Vgp
M12
Vgcp • When VBB > Vth Vgcp
M12 • When VBB < Vth
- M10
+ SW1 M10
GND VLAout
SW1 • Buffer is utilized GND VLAout • SW1/SW2 are on
SW2 VBB
VBB
to drive cascode and operate as
-
+ M11 device M10/M11 SW2 M11 small resistors
Vgcn Vgcn
Vgn M13 M13
Vgn
GND GND
Vrefp VBB
MP1
-
+ M11
Vgcn Vgcn • Ensures the Vds across the core devices
Vrefn
Vgn M13 Vds M12 and M13 < 1.8V
MP2
Vb2 GND
GND
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 27 of 48
Hybrid AC-coupled ETM
L=0.68μH C=4.7μF
BB
VGP2 VGP1
DBB2 DBB1
TYPE III VCOMP
• Buck-Boost fast transient and
MP2 MP1
DDS
Gate Driver
VBAT
mipi DAC
Analog
VH
VCTL_P1 VH
VCTL_P2 VCTL_P1
ISEN_MN
setting for power switching
DIG
DPL-Buck
Converter
ISEN_MP1
ISEN_MP2
ISEN_MN
Mode PWM/PFM Gate Driver MN
• Dual Power Line High-
Dual-mode
efficiency Buck
mipi DAC AC Feed-forward L=1μH
VENV_IP VBB Class-AB LA
C=4.7μF VPA
LPF + VLA_OUT
VENV_IN
-
LPF
R1
RLA R=1ohm
C1 TX IN TX OUT
C=2.2nF External
PA
CLA
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 28 of 48
Self-Compensated Ramp Generator (SCRG) (1/2)
C2
∆VC slope=1
VCOMP
VCOMP
C1 R2 slope=1
VBAT = 2.5V
SCRG SCRG
Buck-mode Boost-mode
VAVDD
(β-1)*R1 VBB = VBAT
βVout
VOUT -
VCOMP VBAT = 5.0V VBB > VBAT
VREF
R1 + Step down Step down
∆VC slope=1
VCOMP
VCOMP
C1 R2 slope=1
VBAT = 2.5V
SCRG SCRG
Buck-mode Boost-mode
VAVDD
(β-1)*R1 VBB = VBAT
βVout
VOUT -
VCOMP VBAT = 5.0V VBB > VBAT
VREF
R1 + Step down Step down
VAVDD VAVDD
VBAT
ITAIL2 ITAIL1
Reset VAVDD
VAVDD
(β-1)*R
VRAMP_BUCK
VRAMP_BOOST + Reset
X1 VR_BUCK
-
C2
VCCS
R
C1
V2I
Boost Buck
VAVDD VAVDD
VBAT
ITAIL2 ITAIL1
Reset VAVDD
VAVDD
(β-1)*R
VRAMP_BUCK
VRAMP_BOOST + Reset
X1 VR_BUCK
-
C2
VCCS
R
C1
V2I
Boost Buck
VBAT VBAT
VODAS VODAS
VBB VBB
VBB_P1 VBB_P1
VBB_N1 VBB_N2 C=4.7μF VBB_N1 VBB_N2 C=4.7μF
VBB_P2 VBB_P2
mipi DAC Mode det. ODAS mipi DAC Mode det. ODAS
VPWM VODAS VPWM VODAS
VBB_P2 VBB_P2
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 33 of 48
Output Dependent Auxiliary Switch (ODAS)
Buck Mode L=0.68μH Boost Mode L=0.68μH
(P2&ODAS on) (P2 on)
VBAT VBAT
VODAS VODAS
VBB VBB
VBB_P1 VBB_P1
VBB_N1 VBB_N2 C=4.7μF VBB_N1 VBB_N2 C=4.7μF
VBB_P2 VBB_P2
mipi DAC Mode det. ODAS mipi DAC Mode det. ODAS
VPWM VODAS VPWM VODAS
VBB_P2 VBB_P2
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 34 of 48
Hybrid AC-coupled ETM
L=0.68μH C=4.7μF
BB
VBAT VODAS Maximum Power
Selection Circuit
• High speed AC Feed-Forward
Buck-Boost
Class-AB Linear Amplifier for
VBB_P1
Converter VBB_N1 BAT
VBB_N2
VBB_P2
VRAMP
SCRG mipi DAC Mode det. ODAS H
VGP2 VGP1
PWM
BAT H
H
VCTL_P2 VCTL_P1
setting for power switching
DAC VCTL_P1
Controller
LA_OUT - VCTL_P2 VGN
D2S and Level Shifter VCTL_N
PA + VCTL_N
MN • Dual Power Line High-
efficiency Buck
Dual-mode
mipi DAC AC Feed-forward
VBB L=1μH
VENV_IP Class-AB LA
C=4.7μF
LPF + VLA_OUT PA
VENV_IN
-
LPF
R1
RLA R=1ohm
C1
C=2.2nF
TX IN External TX OUT
PA
CLA
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 35 of 48
Dynamic Body Bias
• DBB automatically sense
VBAT VBB VBAT VBB
and choose suitable body
VPG12 VPG11 VPG12 VPG11 voltage
VH VH VH
0V toggling power MOS to
VH 0V
acquire lowest Ron
VDBB1 VDBB1 non-toggling MOS with
VBAT VBB VBAT VBB highest bulk voltage
VPG21 VPG22 VPG21 VPG22
VH VH • DDS technique chooses the
0V VH VH 0V highest voltage level VH to
VDBB2
drive power MOS and the
VDBB2
VBAT>VBB VBB>VBAT control circuits
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 36 of 48
Dynamic Driving Switch
VBB
Maximum Power
• DBB automatically sense
Selection Circuit and choose suitable body
VBAT voltage
toggling power MOS to
VGP2 H VGP1
acquire lowest Ron
VBAT VH non-toggling MOS with
DBB2 DBB1
Controller
VCTL_P1 MP2 MP1 highest bulk voltage
VCTL_P2
and Level Shifter
VCTL_N VCTL_P2 VCTL_P1
• DDS technique chooses the
H
highest voltage level VH to
VGN
VCTL_N drive power MOS and the
MN
control circuits
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 37 of 48
Outline
• Motivation of 80MHz High-efficiency ETM
• ET System and AC-coupled ETM Architecture
• ETM Circuit Blocks
– Dual-mode AC Feed-forward Class-AB Linear Amplifier
– Buck-Boost Convertor
– Dual Power Line(DPL) Buck Convertor
• Measurement Results
• Conclusions
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 38 of 48
Die Micrograph
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 39 of 48
ETM Measurement
Efficiency
MAX 87.1%
ETM Efficiency (%)
-148.2
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 41 of 48
Internal Loop Power Control (ILPC) Measurement
VBAT=3.6V VBAT=2.8V
VPA VPA
0.5V 4.2V
VBAT=3.6V VBAT=2.8V
VPA VPA
4.2V 0.5V
for 3G/4G cellular system, power < +/-0.5dB within time slot 18us
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 42 of 48
B41 ETM+PA 40/60MHz ET Measurement
PA out PA out
PA out
4CCA LTE-80MHz
HBM-Mode
• Maximum power reduction (MPR) is 2dB
• RF Front-end loss ~ 5dB
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 44 of 48
ETM ET/APT Efficiency Comparison B41 LTE-20MHz
APT-Mode
ET-Mode
DC=3.8V
lowest 1.5V VBB 450mA
@ 18dBm RF-PA out @31dBm
Crossing
Point
@18dBm
HPUE
MPR *RF Front-end loss ~ 5dB*
ET-Mode Dynamic Range
BW (MHz) 80 20 40 20 10 10
Band41 Band1 Band41 Band3 Band3
LTE Band 2.4GHz
2.593GHz 1.95GHz 2.535GHz 1.75GHz 1.75GHz
ETM 87.1 @ 20MHz
Efficiency (%) 85.5 @ 40MHz 88.7 @ 80 @
83 @ 10MHz 83 @ 20MHz 86.2 @ 10Mz
(Fix-load) 82.3 @ 60MHz 20MHz 10MHz
(peak) 81.2 @ 80MHz
-41.5 @ 40MHz
ACLR (dBc) -32 -41 -38.5 -39 -39.4
-39.9 @ 60MHz
(ETM+PA) @ 20MHz @ 40MHz @ 20MHz @ 10MHz @ 10MHz
-38.1 @ 80MHz
7.54 @ 40
PAPR(dB) 8.29 @ 60 NA NA 6.7 6.7 NA
8.30 @ 80
RF Pout (dBm) 26 @ 80MHz* 1 26.5
23.9 28.3 26.3 26
(ETM+PA) 31 @ 20MHz**
* 26dBm = power class 3 (23dBm) - MPR (2dB) + Front-end loss (5dB)
** 31dBm = power class 2 (26dBm) + Front-end loss (5dB)
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 46 of 48
Outline
• Motivation of 80MHz High-efficiency ETM
• ET System and AC-coupled ETM Architecture
• ETM Circuit Blocks
– Dual-mode AC Feed-forward Class-AB Linear Amplifier
– Buck-Boost Convertor
– Dual Power Line(DPL) Buck Convertor
• Measurement Results
• Conclusions
© 2018 IEEE 27.6 : An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced
International Solid-State Circuits Conference Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS 47 of 48
Conclusions
• ETM system
– Present a 80MHz ETM supporting 4G LTE-A intra-band 4CCA
– Digital algorithm assists ETM by ET shaping waveform (de-trough) and PA
gain compression to optimize efficiency
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 1 of 33
Outline
▪ Introduction
▪ Recent LTE Standards and Requirements
▪ Uplink Carrier Aggregation
▪ Power Class-2 HPUE for Band41
▪ Proposed 2TX SM Techniques
▪ Size-efficient Architecture with Capacitor Swapping
▪ High Power Output with Return to Battery Switching
▪ Experimental Results
▪ Conclusion
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 2 of 33
Outline
▪ Introduction
▪ Recent LTE Standards and Requirements
▪ Uplink Carrier Aggregation
▪ Power Class-2 HPUE for Band41
▪ Proposed 2TX SM Techniques
▪ Size-efficient Architecture with Capacitor Swapping
▪ High Power Output with Return to Battery Switching
▪ Experimental Results
▪ Conclusion
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 3 of 33
Supply Modulator(SM)
Envelope
Average Power
Tracking (ET)
Traditional PA Tracking(APT)
Dynamic supply
Fix supply Stepwise supply
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 5 of 33
Uplink Carrier Aggregation(UL-CA)
Intra-band contiguous CA
SM
20 20 PCC
M M PA
SCC
Band A Band B
Intra-band non-contiguous CA PCC: Primary
SM1 SM2
Component Carrier
20 20 PCC SCC
M M PA PA SCC: Secondary
Band A Band B Component Carrier
20 20 PA PCCSCC PA
M M
Band A Band B
Conventional SM
Inter-band CA SM
20 20 PA PCCSCC PA
M M
Band A Band B
Proposed SM
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 7 of 33
LTE Subframe structure & UL-CA power requirement
0V
SM
INENV
OUTSM=1.6W
η=80% 29dBm 26dBm
(800mW) Duplexer (400mW)
PA + Switch
INRF OUTPA (3dB loss) OUTRF
η=50%
HPUE requires 26dBm antenna output power and 1.6W SM output power.
SM needs high voltage, high power buck-boost converter.
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 9 of 33
Requirements for 2TX SM
Item Contents
UL-CA Independent TX operation
HPUE Boost level envelope
Multi-band GSM/WCDMA/LTE
Multi-mode ET/APT operation
Bandwidth 40MHz ET operation
Efficiency >80% max. with ET operation
Noise Low RX band noise for FDD
Size Small die size
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 10 of 33
Outline
▪ Introduction
▪ Recent LTE Standards and Requirements
▪ Uplink Carrier Aggregation
▪ Power Class-2 HPUE for Band41
▪ Proposed 2TX SM Techniques
▪ Size-efficient Architecture with Capacitor Swapping
▪ High Power Output with Return to Battery Switching
▪ Experimental Results
▪ Conclusion
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 11 of 33
High voltage, hybrid SM structure
Dual-supply
Buck
VBATT 800
Linear Amplifier
with BK 600 IPA
Class AB buffer Isw
(mA)
Current [mA]
ILinear ISW 400
Envelope LA TX
200
VBATT
IPA 0
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 13 of 33
Proposed SM architecture
VBATT
Mux BK1
Envelope1
Only one BB and one Inductor are
LA1 TX1 used.
LA2 TX2
Envelope2
Mux BK2
VBATT
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 14 of 33
2TX ET operation
VTX1_pk>VTX2_pk
VBATT
Mux BK1
Envelope1
Each set of LA and BK operate jointly
LA1 TX1 to generate envelope.
Envelope2
Mux BK2
VBATT
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 15 of 33
2TX APT operation
VTX1>VTX2
VBATT
Mux BK1
Envelope1
BB supplies the TX power, which
LA1 TX1 requires higher voltage.
Envelope2
Mux BK2
VBATT
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 16 of 33
1BB sharing challenge
BK1
TX1
DAC1 SWBB1 SWBK1
BB
BK1
TX1
DAC1 SWBB1 SWBK1
BB
<Restrictions>
TX1 transition cannot interrupt TX2
DAC2 SWBB2
SWBK2
communication.
BK2
TX2 Rush current of switches must be
avoided.
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 17 of 33
Capacitor swapping operation
BK1
VTX1 TX1
SWBB1 SWBK1
DAC1
BB
Main MIPI VBB VBK
Controller Interface
Time(s)
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 18 of 33
Capacitor swapping operation
BK1
VTX1 TX1
SWBB1 SWBK1
DAC1
BB
Main MIPI VBB VBK
Controller Interface
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 19 of 33
Capacitor swapping operation
BK1
VTX1 TX1
SWBB1 SWBK1
DAC1
BB
Main MIPI VBB VBK
Controller Interface
Time(s)
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 20 of 33
Outline
▪ Introduction
▪ Recent LTE Standards and Requirements
▪ Uplink Carrier Aggregation
▪ Power Class-2 HPUE for Band41
▪ Proposed 2TX SM Techniques
▪ Size-efficient Architecture with Capacitor Swapping
▪ High Power Output with Return to Battery Switching
▪ Experimental Results
▪ Conclusion
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 21 of 33
Conventional Return-to-Ground(R2G) switching
VBATT VBB VBATT VBB
BB BB VSW
VBB
LA LA
VTX
VSW VBATT
VSW CAC CAC
BB BB
VBB
LA LA
VSW VTX
VSW VBATT
VSW CAC CAC
VSW
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 23 of 33
Outline
▪ Introduction
▪ Recent LTE Standards and Requirements
▪ Uplink Carrier Aggregation
▪ Power Class-2 HPUE for Band41
▪ Proposed 2TX SM Techniques
▪ Size-efficient Architecture with Capacitor Swapping
▪ High Power Output with Return to Battery Switching
▪ Experimental Results
▪ Conclusion
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 24 of 33
1TX transition (APT-APT to ET-APT)
BK1
TX1
DAC1 SWBB1 SWBK1
BB
BK1
TX1
DAC1 SWBB1 SWBK1
BB
DAC2 SWBB2
SWBK2
BK2
TX2
BB
DAC2 SWBB2
SWBK2
BK2
TX2
BK1
TX1
DAC1 SWBB1 SWBK1
BB
85 max 84.6%
SM efficiency (%)
80
75
VBATT=4.0V, RLOAD = 4.7Ω
70
RB: Resource Block
65 1RB=180kHz ~
200RB=36MHz
60
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SM output power (W)
R2G_swtiching R2B_switching
90
VBATT=3.0V,
LTE1.4MHz (6RB),
Rload=4.7Ω 2.3%
SM efficiency (%)
85
80 1.6%
75
Boosted supply
70
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SM output power (W)
1.5
Boosted
1.0 supply by BB
200mW@ 20dBm
0.5
ET dynamic range
0.0
14 16 18 20 22 24 26 28
PAMiD output power (dBm)
No.
RF-PA Max. SM SM noise Carrier RF E-UTRA Die area Tech.
Supporting Operation PAE
Ref. of
Power ET BW effi. @30/95MHz freq. Pout ACLR / TX node
Protocol mode
TXClass (MHz) (%) (dBm/Hz) (GHz) (dBm) (%) (dBc) (mm2/ea) (nm)
This Class 2 LTE, WCDMA,
2 ET, APT 40 83 -133 / -142 2.593 29.4* 42.7 -38.2 3.0 90
work Class 3 GSM
LTE, WCDMA,
[2] 1 Class 3 ET, APT 40 83 -136 / -141 1.950 26.5^ 42.1 -41.2 4.0 130
GSM
[3] 1 Class 3 LTE, WCDMA ET, APT 10 82 -130 / -139 1.747 27.0 42.6 -39.0 5.0 130
[4] 1 Class 3 LTE ET 20 83 - 2.535 28.3 48.0 -41.4 1.5 180
[5] 1 Class 3 LTE ET 20 88.7" - 2.400 23.9 35.7 -32.0 3.5 65
* duplexer 3.0dB loss is added. ^ duplexer 2.5dB loss is added. " with envelope waveform shaping
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 31 of 33
Die micrograph
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 32 of 33
Conclusion
© 2018 IEEE 27-7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
International Solid-State Circuits Conference Power Class-2 High-Power User Equipment 33 of 33
94% Power-Recycle and Near-Zero Driving-
Dead-Zone N-type Low-Dropout Regulator
with 20mV Undershoot at Short-Period Load
Transient of Flash Memory in Smart Phone
Speaker: Wei-Chung Chen
Author: Wei-Chung Chen, Tzu-Chi Huang, Chao-Chang Chiu,
Chih-Wei Chang, Kuo-Chun Hsu
Affiliation: MediaTek, Taiwan
© 2018 IEEE 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient
International Solid-State Circuits Conference of Flash Memory in Smart Phone 1 of 20
Outline
Motivation
Open-loop status of N-type LDO
Short-period H-L-H load transient
Proposed N-type LDO
Virtual-ground-based dynamic-power-recycling
(VGDPR) Buffer
Anti-ringing feed-forward (ARFF) Compensation
Measurement Result
Performance Summary & Conclusion
© 2018 IEEE 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient
International Solid-State Circuits Conference of Flash Memory in Smart Phone 2 of 20
Outline
Motivation
Open-loop status of N-type LDO
Short-period H-L-H load transient
Proposed N-type LDO
Virtual-ground-based dynamic-power-recycling
(VGDPR) Buffer
Anti-ringing feed-forward (ARFF) Compensation
Measurement Result
Performance Summary & Conclusion
© 2018 IEEE 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient
International Solid-State Circuits Conference of Flash Memory in Smart Phone 3 of 20
Motivation
LDO with N-type PowerMOS
Widely used in Power Management IC (PMIC)
Two power domain
VSYS: BUCK
VBAT: Battery
© 2018 IEEE 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient
International Solid-State Circuits Conference of Flash Memory in Smart Phone 4 of 20
*For easier understanding,
let’s assume Vth=0 Motivation
Design Challenge of Load Transient when using N-type LDO
© 2018 IEEE 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient
International Solid-State Circuits Conference of Flash Memory in Smart Phone 6 of 20
Motivation
© 2018 IEEE 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient
International Solid-State Circuits Conference of Flash Memory in Smart Phone 7 of 20
Motivation
© 2018 IEEE 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient
International Solid-State Circuits Conference of Flash Memory in Smart Phone 8 of 20
Motivation
© 2018 IEEE 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient
International Solid-State Circuits Conference of Flash Memory in Smart Phone 9 of 20
Outline
Motivation
Open-loop status of N-type LDO
Short-period H-L-H load transient
Proposed N-type LDO
Virtual-ground-based dynamic-power-recycling
(VGDPR) Buffer
Anti-ringing feed-forward (ARFF) Compensation
Measurement Result
Performance Summary & Conclusion
© 2018 IEEE 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient
International Solid-State Circuits Conference of Flash Memory in Smart Phone 10 of 20
Proposed N-type LDO
• Fast & Efficient & Simple
© 2018 IEEE 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient
International Solid-State Circuits Conference of Flash Memory in Smart Phone 11 of 20
Proposed VGDPR Buffer
Conventional Proposed
Buffer Buffer
Low Output
Yes Yes
Impedance
Min. VGATE
0 VOUT
Voltage Level
Keep
No Yes
Close-loop Status
Complexity
High Low
for Dynamic IQ
Power Recycling No Yes
© 2018 IEEE 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient
International Solid-State Circuits Conference of Flash Memory in Smart Phone 12 of 20
ARFF Compensation
for Transient Improvement
Conventional
Proposed
Miller
ARFF
Compensation
Dominant
Yes Yes
Pole
Slew Rrate
No Yes
Improvement
Feed-forward
Yes Yes
Path
Smooth
No Yes
Recovery
© 2018 IEEE 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient
International Solid-State Circuits Conference of Flash Memory in Smart Phone 13 of 20
ARFF Compensation
for Transient Improvement
Conventional
Proposed
Miller
ARFF
Compensation
Dominant
Yes Yes
Pole
Slew Rrate
No Yes
Improvement
Feed-forward
Yes Yes
Path
Smooth
No Yes
Recovery
© 2018 IEEE 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient
International Solid-State Circuits Conference of Flash Memory in Smart Phone 14 of 20
Outline
Motivation
Open-loop status of N-type LDO
Short-period H-L-H load transient
Proposed N-type LDO
Virtual-ground-based dynamic-power-recycling
(VGDPR) Buffer
Anti-ringing feed-forward (ARFF) Compensation
Measurement Result
Performance Summary & Conclusion
© 2018 IEEE 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient
International Solid-State Circuits Conference of Flash Memory in Smart Phone 15 of 20
Process : UMC 0.15μm 5V-CMOS,
VBAT=3.8V , VSYS=1.2V
VOUT=1V COUT=1µF Measurement Result
(a) L-H Load transient at steady-state VOUT (b) L-H Load transient at overshoot VOUT
Extra 200μA is
recycled to VOUT
[5] M. Al-Shyoukh, et al., “A transient-enhanced low quiescent current low-dropout regulator with buffer impedance
attenuation,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1732–1742, Aug. 2007.
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Conclusion
Proposed VGDPR Buffer
Fast Transient: using VOUT as virtual ground to avoid open-loop status
High Efficiency: power recycle and dynamic IQ
Dynamic IQ: benefit compensation and slew rate
• ARFF Compensation Tactic
Feed-forward path
Smooth recovery
© 2018 IEEE 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient
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Thanks for your attention
© 2018 IEEE 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient
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An On-Chip Resonant-Gate-Drive
Switched-Capacitor Converter
for Near-Threshold Computing
1The
Ohio State University, Columbus, OH
2Qualcomm Inc., San Diego, CA
© 2018 IEEE
International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 1 of 36
Outline
• Introduction
– Motivation: Near-Threshold Computing
– Switched-Capacitor (SC) Converter: Challenge
• Measurement Results
• Conclusion
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International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 2 of 36
Near-Threshold (NT) Computing
Standard Near-Threshold
Energy
- Nominal Supply - NT supply
Efficient (≈0.4-0.6V)
(≈1.2V)
- Few cores - Many cores
• Measurement Results
• Conclusion
© 2018 IEEE
International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 5 of 36
SC Challenge: Efficiency vs. Current Density
Max Achievable
Heavy Loads
Max Achievable
Cfly
Proposed
RGD
Minimal
Maintain Current
impact
Density
on Area
Load Current (log)
© 2018 IEEE
International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 8 of 36
Outline
• Introduction
• Measurement Results
• Conclusion
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International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 9 of 36
Proposed RGD Scheme – Concept
Simultaneous
Gate Transition
GP
GN
( )
Reduced SW Losses
© 2018 IEEE
International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 13 of 36
Proposed RGD – Silicon Area
R L
( )
CGP CGN
( ) On-Chip Integration
Minimal Area Overhead
GP
GN
GP
GN
GP
GN
• Measurement Results
• Conclusion
© 2018 IEEE
International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 20 of 36
Single-Phase 2:1 SC-RGD
Introduced Conventional
RGD 2:1 Power Stage
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Single-Phase 2:1 SC-RGD
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International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 22 of 36
Single-Phase 2:1 SC-RGD
Dead Time
© 2018 IEEE
International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 23 of 36
Single-Phase 2:1 SC-RGD – Losses
( )
8%
RGD
( )
/
( ) ( )
© 2018 IEEE
International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 25 of 36
4-Phase Interleaved SC-RGD
CLK
CLK1
CLK2
CLK3
CLK4
• Measurement Results
• Conclusion
© 2018 IEEE
International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 27 of 36
Die Micrograph
100 pH inductor:
Active area: 0.32 mm2 5% of active area
On-chip load
© 2018 IEEE
International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 28 of 36
Transient Performance
Vin = 1V
Vout = 0.4V
© 2018 IEEE
International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 29 of 36
Efficiency
Vin = 1V
Vout = 0.4V
© 2018 IEEE
International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 30 of 36
Efficiency
Vin = 1V
Vout = 0.4V
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International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 31 of 36
Comparison to State of the Art
-1 0 1
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Comparison to State of the Art
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International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 33 of 36
Outline
• Introduction
• Measurement Results
• Conclusion
© 2018 IEEE
International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 34 of 36
Conclusion
• Proposed RGD scheme:
– Reduces losses
– Minimal Area Overhead
– Inductor sharing Multi-phase Support
© 2018 IEEE
International Solid-State Circuits Conference 27.9: An On-Chip Resonant-Gate-DriveSwitched-Capacitor Converter for Near-Threshold Computing 35 of 36
Thank You!
Questions?
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