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Controller
Unit Cost
($)
100
CPU
FPGA
10
DSP
MCU
1 Low-
power
ASIC
0.1
0.001 0.01 0.1 1 10
SMPS Power Level (kW)
DSP and FPGA
DSP FPGA
– Digital Signal Processor – Field Programmable Gate Array
– Special Processor optimized for – Flexible hardware architecture with
fast operation logic functions and DSP blocks
PROGRAMMABLE
LOGIC I/O BLOCK
Reg
Data
Reg
Reg
Data
Reg
Reg
In In
… C58
C1 X C2 XC0
C1 X C2 XC0 C3 X C4 X X
Dual-MAC Unit
2 operations + 58 operations + DSP48A1 Multipliers
in 1 clock cycle in 1 clock cycle
Data Out Data Out
NI LabVIEW FPGA
• High Level Programming
• True Parallel Execution
Dual-Core DSP versus Spartan-6 FPGA
– Pros
• Nanosecond control of timing, completely parallel execution
• Now contain dozens to hundreds of mini hard-core DSPs, emerging FPGAs have hard-core
floating point processors
• Orders of magnitude higher DSP performance per dollar and per watt compared to single core
DSPs
• Field reconfigurable at the silicon gate level (SGL)
– Cons
• Orders of magnitude more complex to program
• PCB layout is becoming increasingly complex and costly due to fine-pitch parts
• 70% of software development cost is I/O interface development (rather than algorithms)
Analog I/O
Graphical Co-Simulation
(Multisim, LabVIEW FPGA) Power Electronics Testing
(Bloomy Energy, PXI)
Test
Design
Cells
HIL
Prototype
Rapid Control Prototyping Testing
(Multicore CompactRIO, SIT)
Commercial Deployment
(General Purpose Inverter Controller)
Development Methodology
1. Co-Simulation, 2. Interface Board Design, 3. Commercial Deployment
1.
2. 3.
ni.com | NI CONFIDENTIAL
The Evolution of System Level Design
Traditional Methodology Proposed Methodology
Plant Software Plant Graphical
Closed Loop Closed Loop
Simulation Context
Model Simulation
Model Model Simulation Implementation
(Analog) (Analog) (Analog) Code w/ I/O
(Discrete-Time,
Circuit Design & Continuous to Circuit Design & Fixed Point)
PCB Layout Discrete Time PCB Layout
Deployment Context
FPGA SW Cost FPGA SW Cost
I/O
Algo-
I/O rithm
Algorithm
(70%)
(90%)
Full-Custom Chip-On-Board
ni.com | NI CONFIDENTIAL
Circuit Design with I/O Support
Demos
ni.com/ipnet
New data on LabVIEW graphical
system design approach
NOTE1: The overall embedded market study was a global Email/web study including over 1,700
responses from embedded engineers from Americas, Europe and Asia
NOTE2: The study of NI embedded customers was a global Email/web study including over 1,100
responses NI embedded customers from Americas, Europe and Asia
Achieving Performance with
FPGA-based Control
6 step PWM
- Rough motor operation
- Degrades motor life
- Simple to implement
- Highest Power Output
Sinusoidal PWM - Not power efficient
- Smooth Motor operation
- Relatively simple to design
Space Vector PWM
- Complex Algorithm
- Requires Processing
- Smooth Motor operation
-15% more efficient vs sinusoidal
Some
Frequency
Modulation
- Requires Processing
- Less harmonics
- Switching loss reduced
RPFM PWM-SVM
RPFM and Space Vector Modulation
RPFM PWM-SVM
Clarke Transform:
Convert phase currents from 3-axis to 2-axis
ADC
Spartan-6
FPGA: 2.5us ParkTransform:
Convert to rotating coordinate system
Park-1 Modulator
ISqref
PID d,q SVM Motor
- Driver
ISdref
PID α, β RPFM
-
Ɵ = theta = grid angle
θ
ISq d,q a
α, β
b
ISd α, β a, b, c
Park Clarke
ni.com | NI CONFIDENTIAL
Typical Stack
1. NI Single-Board RIO sbRIO-9606
2. NI GPIC RIO Mezzanine Card (bottom orientation connectors)
3. Custom interface or gate drive PCB (not provided by NI)
To Gate Driver
or IPM
GPIC Mating PCB Template (NI Ultiboard)
GPIC Mating PCB Template (NI Ultiboard)
GPIC Mating PCB Template (NI Ultiboard)
SmartPower Stack™ Inverter
ni.com | NI CONFIDENTIAL
LabVIEW FPGA Power Electronics IP
FPGA-to-FPGA Output
Motion
Communication, CORDIC Trig
Trajectory
Synchronization Functions Space Vector
Splining
PWM
JMAG RT State
Space H-Bridge Multichannel
Simulator Digital Logic
Logic PID
Fixed Point Signal
Generators Protection Loop
Math Interlocks Structures
Input
ni.com/ipnet
Next Steps
Visit
Download the Power
ni.com/powerdev Electronics Design Guide
for more info
Visit
ni.com/gpic