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Introduction
Thank you for choosing the Lattice Semiconductor MachXO3 Starter Kit!
This user’s guide describes how to start using the MachXO3 Starter Kit, an easy-to-use platform for evaluating and
designing with the MachXO3 ultra-low density FPGA. Along with the board and accessories, this kit includes a pre-
loaded demonstration design. You may also reprogram the on-board MachXO3 device to review your own custom
designs.
The MachXO3 Starter Kit currently features the MachXO3L-6900C (NVCM Based) or the MachXO3LF-6900C
(Flash Based) device in the 256-ball 0.8 mm pitch caBGA package. The kit also includes a Serial Flash Memory for
demonstrating external SPI boot-up. The external Flash Memory also supports a dual-boot mode in addition to
Golden boot/fail-safe boot options.
Note: Static electricity can severely shorten the lifespan of electronic components. See the Storage and Handling
section of this document for handling and storage tips.
Features
The MachXO3 Starter Kit includes:
• MachXO3L/LF Board – The board is a 3” x 3” form factor that features the following on-board components and
circuits:
— MachXO3 FPGA – LCMXO3L-6900C-5BG256C (NVCM Based) or LCMXO3LF-6900C-5BG256C (Flash
Based)
— USB mini-B connector for power and programming
— 4-Mb Serial Flash Memory for boot image and dual-boot support.
— Eight LEDs
— 4-position DIP switch
— Momentary push button switch
— 40-hole prototype area
— Four 2 x 20 expansion header landings for general I/O, JTAG, and external power
— 1 x 8 expansion header landing for JTAG
— 1 x 6 expansion header landing for SPI/I2C
— 3.3 V and 1.2 V supply rails
• Pre-loaded Demo – The kit includes a pre-loaded counter design that highlights use of the embedded MachXO3
oscillator and programmable I/Os configured for LED drive.
• USB Connector Cable – The board is powered from the USB mini-B socket when connected to a host PC. The
USB channel also provides a programming interface to the MachXO3 JTAG port.
• Lattice Development Kits and Boards Web Page – Visit www.latticesemi.com/breakoutboards for the latest
documentation (including this guide) and drivers for the kit.
The content of this user’s guide includes demo operation, programming instructions, top-level functional descrip-
tions of the Starter Kit, descriptions of the on-board connectors, and a complete set of schematics.
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MachXO3 Starter Kit User Guide
JTAG Header
Landing (J1)
LED array
(D9-D2)
SPI/I2C Header
Landing (J7)
USB Mini-B
Socket (J2)
4-Position DIP
Switch (SW2)
Power LED,
Blue (D1)
Push Button
Switch (SW1)
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MachXO3 Starter Kit User Guide
• Use anti-static precautions such as operating on an anti-static mat and wearing an anti-static wrist-band.
• Store the evaluation board in the packaging provided.
• Touch a metal USB housing to equalize voltage potential between you and the board.
Software Requirements
You should install the following software before you begin developing new designs for the Starter Kit:
MachXO3 Device
This board currently features the MachXO3L-6900C FPGA which offers embedded Non-Volatile Configuration
Memory (NVCM) technology or the MachXO3LF-6900C FPGA which offers embedded Non-Volatile Flash technol-
ogy for instant-on operation in a single chip. Numerous system functions are included, such as two PLLs and 256
kbits of embedded RAM plus hardened implementations of I2C and SPI. Flexible, high performance I/Os support
numerous single-ended and differential standards including LVDS. The 256-ball BGA package provides up to 206
user I/Os in a 14 mm x 14 mm form factor. A complete description of this device can be found in the MachXO3
Family Data Sheet.
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MachXO3 Starter Kit User Guide
Demonstration Design
Lattice provides a simple, pre-programmed demo to illustrate basic operation of the MachXO3 device. The design
integrates an up-counter with the on-chip oscillator. The pre-programmed design resides in the external Serial
Flash Memory (SPANSION S25FL204K or S25FL208K).
Note: To restore the factory default demo and program it with other Lattice-supplied examples see the Download
Demo Designs section of this document.
XO3L_SK_blink.v
OSCH
12.09 MHz Kitcar.v
1x8
LED
Heartbeat.v Array
X1
12.0 MHz
SW2
4-Position DIPSW
SW1
Async Reset
Momentary PB
WARNING: Do not connect the board to your PC before you follow the driver installation procedure of this section.
Communication between the board and a PC via the USB connection cable requires installation of the FTDI chip
USB hardware drivers. Loading these drivers enables the computer to recognize and program the board. Drivers
can be loaded as part of the installation of Lattice Diamond design software or Diamond Programmer, or as a
stand-alone package.
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MachXO3 Starter Kit User Guide
To load the FTDI Chip USB hardware drivers as part of the Lattice Diamond installation:
2. Select FTDI Windows USB Driver or All Drivers in the LSC Drivers Install/Uninstall dialog box.
3. Click Finish to install the USB driver.
4. After the driver installation is complete, connect the USB cable from a USB port on your PC to the board’s USB
mini-B socket (J2). After the connection is made, a blue Power LED (D1) will light indicating the board is pow-
ered on.
5. The demonstration design will automatically load and drive the LED array in a repeating pattern.
To load the FTDI chip USB hardware drivers via the stand-alone package on a Windows system:
1. Download the FTDI Chip USB Hardware Drivers package from the Lattice web site.
2. Extract the FTDI chip USB Hardware driver package to your PC hard drive.
3. Connect the USB cable from a USB port on your PC to the board’s USB mini-B socket (J2). After the connec-
tion is made, a blue Power LED (D1) will light indicating the board is powered on.
4. If you are prompted, “Windows may connect to Windows Update” select No, not this time from available
options and click Next to proceed with the installation. Choose the Install from specific location (Advanced)
option and click Next.
5. Search for the best driver in these locations and click the Browse button to browse to the Windows driver folder
created in the Download Windows USB Hardware Drivers section. Select the CDM 2.04.06 WHQL Certified
folder and click OK.
6. Click Next. A screen will display as Windows copies the required driver files. Windows will display a message
indicating that the installation was successful.
7. Click Finish to install the USB driver.
8. The demonstration design will automatically load and drive the LED array in a repeating pattern.
See the Troubleshooting section of this guide if the board does not function as expected.
1. In the Lattice web site, browse to Development Kits and Boards. Go to the MachXO3L Starter Kit or to the
MachXO3LF Starter Kit web page. In the Documentation section, select the Design File tab. Select
MachXO3L Starter Kit Demo Program or the MachXO3LF Starter Kit Demo Program and save the file.
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MachXO3 Starter Kit User Guide
1. Install, license and run Lattice Diamond software. See www.latticesemi.com/latticediamond for download and
licensing information.
2. Connect the USB cable to the host PC and the MachXO3 board.
3. From Diamond, open the Blink.ldf project file.
4. Click the Programmer icon.
5. Click Detect Cable. The Programmer will detect the cable (Cable: USB2, Port: FTUSB-0). If the cable is not
detected, see the Troubleshooting section.
6. Click Device Properties.
7. Change Access Mode to SPI Flash Programming.
8. Choose SPI Flash Background Erase, Program, Verify operation.
9. Select Blink_impl1.bit programming file.
10. Under SPI Flash Options, change Vendor to SPANSION and change Device to SPI-S25FL204K or
S25FL208K (as appropriate). Click OK.
11. Click the Program icon. When complete, PASS is displayed in the Status column.
12. Change Access mode to NVCM Programming Mode and NVCM Refresh, then click Program (or power-
cycle the Starter Kit board) to initiate a re-boot from the SPI flash.
7
MachXO3 Starter Kit User Guide
Overview
The Starter Kit is a complete development platform for the MachXO3 FPGA. The board includes a prototyping
area, a USB program/power port, an LED array, switches, and header landings with electrical connections to most
of the FPGA’s programmable I/O, power, and configuration pins. The board is powered by the PC’s USB port or
optionally with external power. You may create or modify the program files and reprogram the board using Lattice
Diamond software.
Bank 1
GPIO
2 x 20 Header
Bank 3, 4 and 5 Landing (J4)
2 x 20 Header GPIO
MachXO3L/LF-6900C device
Landing (J8)
8 LED
Array
4
DIP_SW
GPIO
2 x 20 Header 1 x 6 Header
Landing (J6) Landing (J7,
Bank 2 Optional SPI,
I2C Intrfaces)
Bank 0, 2
8
MachXO3 Starter Kit User Guide
Table 2 describes the components on the board and the interfaces it supports.
Subsystems
This section describes the principle sub systems for the Starter Kit in alphabetical order.
Clock Sources
Clock sources for the LED demonstration designs originate from the MachXO3 on-chip oscillator or the 12 MHz
crystal X1. You may use an expansion header landing to drive a FPGA input with an external clock source.
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MachXO3 Starter Kit User Guide
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MachXO3 Starter Kit User Guide
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MachXO3 Starter Kit User Guide
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MachXO3 Starter Kit User Guide
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MachXO3 Starter Kit User Guide
Top Side J6 J8 1 2 1 2
VCCIO2 VCCIO2 VCCIO5 VCCIO3
T12 T14 H6 N3
R11 R13 M2 M1
T11 M11 L2 L1
P11 N10 L3 L5
GND GND GND GND
T10 P10 K4 J1
R9 R10 K1 J2
T9 N9 J3 H3
P9 M8 H2 H1
GND GND GND GND
T8 L8 G2 G1
P8 M6 F2 F1
R7 R8 E2 E1
P7 T7 D2 D1
GND GND GND C2
L7 R6 C1 G3
N6 T5 B1 D3
R4 P4 E3 F3
T3 T4 F5 VCCIO4
39 40 39 40
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MachXO3 Starter Kit User Guide
MachXO3L
J1 J1 LED Net Ball
8 D9 LED0 H11
D8 LED1 J13
TCK D9 D7 LED2 J11
GND
D6 LED3 L12
TMS
D5 LED4 K11
nc
D2 D4 LED5 L13
nc
J7 D3 LED6 N15
TDI
D2 LED7 P16
TDO
VCCIO0
Top Side
LCMXO2-7000HE SW2
1 4TG144C
MachXO3L
J7
Net Ball
6
DIP_SW1 DIP_SW1 N2
MCLK DIP_SW2 P1
SISPI DIP_SW3 M3
SPISO DIP_SW4 DIP_SW4 N1
SN
SCL
SDA
1
MachXO3 FPGA
The LCMXO3L/LF-6900C-5BG256C is a 256-ball caBGA package FPGA device which provides up to 206 usable
I/Os in a 14 mm x 14 mm package. 150 I/Os are accessible from the board headers, switches and LEDs.
15
MachXO3 Starter Kit User Guide
LEDs
A blue LED (D1) is used to indicate USB 5V power. Eight red LEDs are driven by I/O pins of the MachXO3 device.
Power Supply
3.3 V and 1.2 V power supply rails are converted from the USB 5 V interface when the board is connected to a host
PC.
Test Points
In order to check the various voltage levels used, test points are provided:
• TP1: +3.3 V
• TP2: +1.2 V
• TP3: GND
JTAG Programming: For JTAG programming, a preprogrammed USB PHY peripheral controller is provided on the
Starter Kit to serve as the programming interface to the MachXO3 FPGA.
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MachXO3 Starter Kit User Guide
Board Modifications
This section describes modifications to the board to change or add functionality.
Mechanical Specifications
Dimensions: 3 in. [L] x 3 in. [W] x 1/2 in. [H]
Environmental Requirements
The evaluation board must be stored between –40° C and 100° C. The recommended operating temperature is
between 0° C and 90° C.
Glossary
FPGA: Field Programmable Gate Array
17
MachXO3 Starter Kit User Guide
Troubleshooting
Use the tips in this section to diagnose problems with the Starter Kit.
If power is applied but the board does not flash according to the preprogrammed counter demonstration then it is
likely the board has been reprogrammed with a new design. Follow the directions in the Demonstration Design sec-
tion to restore the factory default.
If Lattice Diamond Programmer or ispVM System does not recognize the USB cable after installing the Lattice USB
port drivers and rebooting, the incorrect USB driver may have been installed. This usually occurs if you attach the
board to your PC prior to installing the Lattice-supplied USB driver.
2. Search for USB driver or Troubleshooting, then select the Troubleshooting the USB Driver topic.
3. Follow the directions to install the Lattice USB driver.
For ispVM:
1. Start ispVM System and choose Options > Cable and I/O Port Setup.
The Cable and I/O Port Setup Dialog appears.
An alternate failure mode can occur when the user design assigns an output signal to the FPGA package pin C8
which is connected the oscillator (X1) output signal "12 MHz". This can occur unintentionally when the Placer ran-
domly assigns unconstrained outputs. In this case, the contention squelches the FTDI device (U1) clock input, ren-
dering it unable to communicate. To eliminate the contention, remove the resistor R23. This will restore the FTDI
device operation and allow the erasure of the offending FPGA image. Resistor R23 should be reinstalled if an
external clock source is desired.
If the Starter Kit has been reprogrammed, the original demo design can be restored. To restore the board to the
factory default, see the Download Demo Designs section for details on downloading and reprogramming the
device.
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MachXO3 Starter Kit User Guide
Ordering Information
China RoHS Environment-Friendly
Description Ordering Part Number Use Period (EFUP)
Revision History
Date Version Change Summary
March 2016 1.2 Updated Demonstration Design section. Indicated external Serial Flash
Memory (SPAN-SION S25FL204K or S25FL208K).
Updated Run the Demonstration Design section. Corrected the link to
the FTDI Chip USB Hardware Drivers in the procedure for loading the
FTDI chip USB hardware drivers via the stand-alone package on a Win-
dows system.
Updated Programming a Demo Design with the Lattice Diamond Pro-
grammer section. Modified Device in step 10 of the procedure for pro-
gramming MachXO3 device.
Updated Expansion Header Landings section. Revised Figure 7, J1
Header Landing and LED Array Callout to correct DIPSW ball callouts.
Updated Download Demo Designs section. Corrected links in the proce-
dure for downloading demo designs.
Updated Appendix B. Bill of Materials section. Modified item 40 Span-
sion MFG Pin in Table 15, MachXO3 Starter Kit Bill of Materials.
May 2015 1.1 Changed document title to MachXO3 Starter Kit User Guide
Changed instances of MachXO3L to MachXO3.
Indicated MachXO3L and/or MachXO3LF devices and board versions.
Indicated MachXO3 NVCM and/or Flash based devices.
Updated Technical Support Assistance section.
November 2014 1.0 Initial release.
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
19
5 4 3 2 1
D D
SPI
I/O'S
I/O'S
BANK-2 BANK-4
HEADER
Appendix A. Schematics
I2C
I/O'S
C C
HEADER
I/O'S
LCMXO3L/LF-6900C-5BG256C
HEADER
BANK-0
BANK-3
JTAG_I/F
USB USB to
CONNECTOR JTAG / RS232 RS232_I/F
20
BANK-1 BANK-5
Power from USB 5V
B B
I/O'S
I/O'S
LEDS (1-8)
HEADER
A A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Title
MACHXO3 Starter Kit - BLOCK DIAGRAM
+3.3V
L1 VCCIO0
2 1
600ohm 500mA
1
C1 C2
4.7uF
+3.3V 0.1uF
2
D R3 R1 R2 D
L2
2 1
600ohm 500mA 4.7K 4.7K 4.7K
1
C3 C4 VCC1_8FT +3.3V J1
4.7uF 1
0.1uF 1 2 TDO
2
2 3 TDI
3 4
Figure 9. USB Interface to JTAG
4 5
5 6 TMS
6 7
VCC1_8FT +3.3V U1 7 8 TCK
FT2232HL 8
4
9
12
37
64
20
31
42
56
Header 1x8
DNI
VPLL
VPHY
VCCIO
VCCIO
VCCIO
VCCIO
VCORE
VCORE
VCORE
16 0 R4
ADBUS0 TCK Sheet[4]
50 17 0 R5
VREGIN ADBUS1 TDI Sheet[4]
18 0 R6
ADBUS2 TDO Sheet[4]
49 19 0 R7
VREGOUT ADBUS3 TMS Sheet[4]
21
C ADBUS4 C
22
7 ADBUS5 23
Sheet[3] DM DM ADBUS6
Sheet[3] DP 8 24
DP ADBUS7 R8
C5 C6 26 2.2K
R9 2.2K 14 ACBUS0 27
10uF 0.1uF RESET# ACBUS1 28
+3.3V R10 12K ACBUS2 29
6 ACBUS3 30
+3.3V REF ACBUS4 32
R11 R12 R13 ACBUS5 33
ACBUS6 34 FOR FUTURE RS232 FUNCTION
ACBUS7
21
FT_EECS 63
FT_EECLK 62 EECS 38 0 DNI R14
EECLK BDBUS0 RS232_Rx_TTL Sheet[4]
U2 10K 10K 10K FT_EEDATA 61 39 0 DNI R15
EEDATA BDBUS1 RS232_Tx_TTL Sheet[4]
8 1 40 0 DNI R16 RTSn Sheet[4]
7 VCC CS 2 BDBUS2 41 0 DNI R17
NU CLK BDBUS3 CTSn Sheet[4]
6 3 2 43 0 DNI R18 DTRn Sheet[4]
C7 5 ORG DI 4 OSCI BDBUS4 44 0 DNI R20
VSS DO BDBUS5 DSRn Sheet[4]
12K R19 45 0 DNI R21
X1 BDBUS6 DCDn Sheet[4]
0.1uF 93LC56C-I/SN 46 0 DNI R22
BDBUS7 RI Sheet[4]
1 3 3
1 3 OSCO 48
2 4 BCBUS0 52
B B
C8 G1 G2 C9 BCBUS1 53 FOR FUTURE I2C FUNCTION
13 BCBUS2 54
18pF 12MHZ 18pF TEST BCBUS3 55 0 DNI R27 FTDI_SCL Sheet[6]
BCBUS4 57 0 DNI R62
BCBUS5 58 0 DNI R82
FTDI High-Speed USB BCBUS6 FTDI_SDA Sheet[6]
59
BCBUS7
USB_I2C_EN Sheet[6]
FT2232H 60
PWREN#
+3.3V 36
0 R23 SUSPEND#
Sheet[4] 12MHZ
AGND
GND
GND
GND
GND
GND
GND
GND
GND
10
11
15
25
35
47
51
A A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Title
USB to JTAG I/F
VBUS_5V
C15
1
R24 1 R31 1 R25 1 R37 1
L3 0.1uF NOTE : Boot from external SPI Flash (U6)
D D
600ohm 500mA
requires VCCIO2 set to 3.3V. Use caution
+1.2V +1.2V +1.2V +1.2V when setting VCCIO2 to any other voltage.
2
R86 1 R33 1 R28 1 R39 1
1
1
1
1
GND C16 0.1uF
SKT_MINIUSB_B_RA
1
1K TAB
22
D1 C19 C20 C21
GND DNI DNI DNI
Blue
10uF 22uF 0.1uF
1 NCP1117
2
TP9 TP10 TP11
1
1
1
B B
TP3
TP1 TP2
1
+3.3V +1.2V
1
1
+3.3V
GND
22uF
Email: techsupport@Latticesemi.com
100
1
Phone (503) 268-8001 -or- (800) LATTICE
Title
POWER REGULATORS
VCCIO0
NOTE : MAKE PWR TRACES
CAPABLE OF 1A
1
PT20D/PT23D/PT27D || PROGRAMN IO_A5 36 35 IO_B5
TDO C6 A11 RS232_Rx_TTL IO_A4 38 37 IO_B4
Sheet[2] TDO PT12C/PT13C/PT14C || TDO PT21A*/PT24A*/PT28A* RS232_Rx_TTL Sheet[2]
TDI A6 C11 RS232_Tx_TTL IO_A3 40 39
Sheet[2] TDI PT12D/PT13D/PT14D || TDI PT21B*/PT24B*/PT28B* RS232_Tx_TTL Sheet[2]
IO_B7 B7 F10 RTSn
C PT13A*/PT14A*/PT15A* PT21C/PT24C/PT32A* RTSn Sheet[2] C
IO_C7 C7 D11 DTRn
PT13B*/PT14B*/PT15B* PT21D/PT24D/PT32B* DTRn Sheet[2]
Header 2x20
IO_E6 E6 B11 CTSn
PT13C/PT14C/PT16A* PT22A*/PT25A*/PT33A* CTSn Sheet[2]
IO_D7 D7 A12 DSRn
PT13D/PT14D/PT16B* PT22B*/PT25B*/PT33B* DSRn Sheet[2]
IO_F7 F7 B13 DCDn
PT16A*/PT15A*/PT17A* PT22C/PT26A*/PT34A* DCDn Sheet[2]
IO_E8 E8 A14 RI
PT16B*/PT15B*/PT17B* PT22D/PT26B*/PT34B* RI Sheet[2]
TCK A7 C12 IO_C12
Sheet[2] TCK PT16C/PT15C/PT17C || TCK PT23A*/PT27A*/PT35A*
TMS B8 B12 IO_B12
Sheet[2] TMS PT16D/PT15D/PT17D || TMS PT23B*/PT27B*/PT35B*
12MHZ C8 B14 VCCIO0
Sheet[2] 12MHZ PT17A*/PT18A*/PT18A* || PCLKT0_1 PT24A*/PT28A*/PT36A*
A8 A15
23
PT17B*/PT18B*/PT18B* || PCLKC0_1 PT24B*/PT28B*/PT36B*
IO_D8 D8 A13 INITN
IO_E9 E9 PT17C/PT19A*/PT21A* PT24C/PT28C/PT36C || INITN C13 DONE R45
PT17D/PT19B*/PT21B* PT24D/PT28D/PT36D || DONE
LCMXO3L-6900C-5BG256C
A A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Title
BANK0 I/0
U5B
NOTE : MAKE PWR TRACES
BANK1 CAPABLE OF 1A
Figure 12. Power LEDs
24
M14 IO_M14
PR13A/PR18A/PR23A M15 IO_M15
PR13B/PR18B/PR23B
N16 IO_N16
PR14A/PR19A/PR24A N14 IO_N14
PR14B/PR19B/PR24B
A A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Title
BANK1 I/O
U5C
NOTE : MAKE PWR TRACES
BANK2 CAPABLE OF 1A
VCCIO2 J6 VCCIO2 IO_P4 R46 DNI 100
Figure 13. Bank 2 I/O
25
IO_T11 R59 DNI 100
VCCIO2 VCCIO2 IO_P11
+3.3V
NOTE : PLACE SPI FLASH IN THE BOTTOM SIDE
NOTE : PLACE TEST POINTS NEAR PIN 1 OF J7 AND THE SAME LINE
C41
Sheet[2] USB_I2C_EN 1 TP15 R63
100nF
Sheet[2] FTDI_SDA 1 TP14 10V
R64 R65 R66
1 TP13 1K U6
8
Sheet[2] FTDI_SCL
Sheet[4] SDA 1
Sheet[4] SCL 2 J7 SISPI 5 2 SPISO 10K 10K 10K
VCC
SN 3 SDI SDO
SPISO 4 DNI MCLK 6
SISPI 5 SCK
MCLK 6 NOTE : PLACE J7 NEAR J1 3
WP SPI FLASH
CSSPIN 0 R67 1 7
CON6 CS HOLD
GND
A A
4
U5D U5F
BANK3 BANK5
N2 DIP_SW1 IO_B1 B1 G5
IO_L1 L1 PL13C/PL18C/PL23C P1 DIP_SW2 IO_C2 C2 PL1C/PL2C/PL2C PL4C/PL7C/PL7C G4
D IO_L3 L3 PL11A/PL16A/PL19A PL13D/PL18D/PL23D PL1D/PL2D/PL2D PL4D/PL7D/PL7D D
PL11B/PL16B/PL19B M3 DIP_SW3 IO_D3 D3 F3 IO_F3
IO_K4 K4 PL13A/PL19A/PL24A N1 DIP_SW4 IO_D1 D1 PL1A/PL3A/PL3A || L_GPLLT_FB PL4A/PL7A/PL8A F1 IO_F1
Figure 14. Bank 3, 4, 5 I/O
26
BANK4 VCCIO3 J8 VCCIO5
IO_G1 G1 J2 IO_J2 VCCIO3 PLACE THE RESISTORS IN THE TOP
IO_H2 H2 PL6A/PL9A/PL10A PL9A/PL13A/PL15A K1 IO_K1
PL6B/PL9B/PL10B PL9B/PL13B/PL15B 2 1
H4 H5 IO_N3 4 3 IO_H6
J6 PL6C/PL9C/PL10C PL9C/PL13C/PL15C J4 IO_M1 6 5 IO_M2
PL6D/PL9D/PL10D PL9D/PL13D/PL15D IO_L1 8 7 IO_L2 R68 R69 R70 R71
IO_H3 H3 J5 IO_L5 10 9 IO_L3
IO_H1 H1 PL7A/PL10A/PL11A PL10C/PL14C/PL16C K6 12 11
PL7B/PL10B/PL11B PL10D/PL14D/PL16D IO_J1 14 13 IO_K4
K3 IO_J2 16 15 IO_K1 4.7K 4.7K 4.7K 4.7K SW2
B B
PL10A/PL14A/PL17A K2 IO_H3 18 17 IO_J3 DIP_SW1 1 8
PL10B/PL14B/PL17B IO_H1 20 19 IO_H2 DIP_SW2 2 1 8 7
IO_J1 J1 22 21 DIP_SW3 3 2 7 6
IO_J3 J3 PL7C/PL10C/PL12A || PCLKT4_0 IO_G1 24 23 IO_G2 DIP_SW4 4 3 6 5
PL7D/PL10D/PL12B || PCLKC4_0 IO_F1 26 25 IO_F2 4 5
VCCIO4 IO_E1 28 27 IO_E2
SW-DIP4
IO_D1 30 29 IO_D2
IO_C2 32 31
H7 IO_G3 34 33 IO_C1
VCCIO4/VCCIO4/VCCIO4 J7 IO_D3 36 35 IO_B1
VCCIO4/VCCIO4/VCCIO4 C48 C49 C50 VCCIO4 IO_F3 38 37 IO_E3
40 39 IO_F5
1K-2K/4K/7K || 2nd_Fn. 0.1uF 0.1uF 0.1uF
A A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Title
BANK3,4,5 I/O
VCC_CORE
D +3.3V LEDs D
U5G
B2 A1
B15 GND/GND/GND VCC/VCC/VCC A16
C3 GND/GND/GND VCC/VCC/VCC G7
C14 GND/GND/GND VCC/VCC/VCC G10 R72 R73 R74 R75 R76 R77 R78 R79
D4 GND/GND/GND VCC/VCC/VCC K7
GND/GND/GND VCC/VCC/VCC 1K 1K 1K 1K 1K 1K 1K 1K
D13 K10
E5 GND/GND/GND VCC/VCC/VCC T1
E12 GND/GND/GND VCC/VCC/VCC T16
F6 GND/GND/GND VCC/VCC/VCC
F11 GND/GND/GND
1
1
1
1
1
1
1
1
H8 GND/GND/GND
H9 GND/GND/GND A2 D2 D3 D4 D5 D6 D7 D8 D9
J8 GND/GND/GND NC/NC/NC
GND/GND/GND Red Red Red Red Red Red Red Red
J9
GND/GND/GND
Figure 15. Power Decoupling and LEDs
L6
L11 GND/GND/GND
2
2
2
2
2
2
2
2
M5 GND/GND/GND
M12 GND/GND/GND
N4 GND/GND/GND LAYOUT LEDs IN A SINGLE ROW
N13 GND/GND/GND
C GND/GND/GND C
P3 Sheet[5] LED7
P14 GND/GND/GND
GND/GND/GND Sheet[5] LED6
R2 Sheet[5] LED5
R15 GND/GND/GND
GND/GND/GND Sheet[5] LED4
Sheet[5] LED3
Sheet[5] LED2
1K-2K/4K/7K
Sheet[5] LED1
Sheet[5] LED0
LCMXO3L-6900C-5BG256C
27
Note : LEDs are controlled by XO3L I/O Bank 1. When
VCCIO1 is set to a voltage less than 3.3V, observe all I/O
overdrive requirements. Refer to Lattice TN1280
"MachXO3 sysIO Usage Guide" for more information.
B B
C51 C52 C53 C54 C55 C56 C57 C58 C59 C60
10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.1uF 0.1uF 0.01uF
A A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Title
POWER DECOUPLING AND LED'S
28
MachXO3 Starter Kit User Guide
29