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Answer: a
Explanation: Its the different modes of accessing the i/o
devices.
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Answer: c
Explanation: BUS is a collection of address,control and data
lines used to connect the various devices of the computer.
Answer: b
Explanation: This type of accessing is called as I/O mapped
devices.
Answer: c
Explanation: Since the I/O mapped devices have a
seperate address space the address lines are limited by
amount of the space allocated.
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Answer: d
Explanation: It is necessary for the processor to send a
signal intimating the request as either read or write.
Answer: b
Explanattion: The processor operating is much faster than
that of the I/O devices , so by using the status flags the
processor need not wait till the I/O operation is done. It can
continue with its work until the status flag is set.
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Answer: a
Explanation: In this method the processor constantly
checks the status flags , and when it finds that the flag is
set it performs the appropriate operation.
Answer: c
Explanation: This is a method of accessing the I/O devices
which gives the complete power to the devices, enabling
them to intimate the processor when they’re ready for
transfer.
Answer: d
Explanation: In DMA the I/O devices are directly allowed to
interact with the memory with out the intervention of the
processor and the transfres take place in the form of blocks
increasing the speed of operaion.
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Answer: a
Explanation: None.
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sanfoundry.com
Interrupts - Computer
Organization Questions and
Answers
by Manish
5-6 minutes
Answer: b
Explanation: The Interrupt-request line is a control line
along which the device is allowed to send the interrupt
signal.
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c) Processor stack
d) Memory
View Answer
Answer: c
Explanation: The Processor after servicing the interrupts as
to load the address of the previous process and this
address is stored in the stack.
Answer: a
Explanation: The Processor upon recieving the interrupt
should let the device know that its request is received.
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Answer: d
Explanation: None.
Answer: b
Explanation: The delay in servicing of an interrupt happens
due to the time taken for contect switch to take place.
Answer: c
Explanation: This forms an imporatant part of the Real time
system since if a process arrives with greater priority then it
raises an interrupt and the other process is stopped and the
interrupt will be serviced.
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Answer: a
Explanation: None
Answer: a
Explanation: None
Answer: b
Explanation: This resistor is used to pull up the voltage of
the interrupt service line.
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c) Maskable interrupt
d) High priority interrupt
View Answer
Answer: c
Explanation: The maskable interrupts are usually low
priority interrupts which can be ignored if an higher priority
process is being executed.
Answer: c
Explanation: The 8085 microprocessor are designed to
complete the execution of the current instruction and then
to service the interrupts.
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View Answer
Answer: b
Explanation: A software interrupt by some program which
needs some cPU service, at that time the two modes can
be interchanged.
Answer: c
Explanation: The trap is a non-maskable interrupt as it
deals with the on going process in the processor. THe trap
is initiated by the process being executed due to lack of
data required for its completion.Hence trap is unmaskable.
Answer: d
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Explanation: None.
Answer: d
Explanation: None.
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sanfoundry.com
Answer: a
Explanation: In this method the processor checks the IRQ
bits of all the devices, which ever is enabled first that device
is serviced.
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c) Interrupt nesting
d) Simultaneous requesting
View Answer
Answer: b
Explanation: None.
Answer: c
Explanation: By sending the starting address of the routine
the device ids the routine required and thereby identifying
itself.
Answer: d
Explanation: None.
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Answer: b
Explanation: None.
Answer: c
Explanation: When the processor activates the
acknowledge line the devices send their interrupts to the
processor.
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step a
Identify the form of communication best describes the I/O
mode amongst the following:
a) Programmed mode of data transfer
b) DMA
c) Interrupt mode
d) Polling
View Answer
Answer: d
Explanation: In polling the processor checks each of the
device if they wish to perform data transfer and if they do it
performs the particular operation.
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Answer: a
Explanation: None.
Answer: a
Explanation: None.
Answer: b
Explanation: In Daisy chain mechanism, all the devices are
connected using a single request line and they’re serviced
based on the interrupting device’s priority.
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View Answer
Answer: b
Explanation: In daisy chaining since there is only one
request line and only one acknowledge line, the
acknowledge signal passes from device to device until the
one with the interrupt is found.
Answer: a
Explanation: None.
Answer: d
Explanation: None.
14. The anded output of the bits of the interrupt register and
the mask register are set as input of:
a) Priority decoder
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b) Priority encoder
c) Process id encoder
d) Multiplexer
View Answer
Answer: b
Explanation: In a parallel priority system, the priority of the
device is obtained by anding the contents of the interrupt
register and the mask register.
Answer: b
Explanation: None.
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sanfoundry.com
Exceptions - Computer
Organization Questions and
Answers
by Manish
4-5 minutes
Answer: b
Explanation: Since the interrupt was raised during the
exevution of the instruction, the instruction cannot be
executed and the exception is servied immediately.
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b) Interrupt
c) System calls
d) All of the mentioned
View Answer
Answer: d
Explanation: None.
Answer: a
Explanation: Debugger is a program used to detect and
correct errors in the program.
Answer: d
Explanation: The debugger provides us with the two
facilities to improve the checking of errors.
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Answer: a
Explanation: In trace mode the program is checked line by
line and if errors are detected then exceptions are raised
right away.
Answer: d
Explanation: The Breakpoint mode of operation allows the
program to be alted at only specific locations.
Answer: b
Explanation: The user programs are in the user mode and
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Answer: c
Explanation: These instructions are those which can are
crucial for the systems performance and hence cannot be
adultered by user programs, so is run only in supervisor
mode.
Answer: d
Explanation: None.
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of a new process
d) The system switches mode and runs the debugger
View Answer
Answer: a
Explanation: None.
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sanfoundry.com
Answer: d
Explanation: DMA is an approcah of performing data
transfers in bulk between memory and the external device
without the intervention of the processor.
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c) Data controller
d) Overlooker
View Answer
Answer: b
Explanation: The Controller performs the functions that
would normally be carried out by the processor.
Answer: c
Explanation: The DMA controller acts like a processor for
DMA transfers and overlooks the entire process.
Answer: b
Explanation: The controller raises an interrupt signal to
notify the processor that the transfer was complete.
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a) 4
b) 2
c) 3
d) 1
View Answer
Answer: c
Explanation: The Controller uses the registers to store the
starting address,word count and the status of the operation.
Answer: a
Explanation: None.
Answer: b
Explanation: The controller is directly connected to the
system BUS to provide faster transfer of data.
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Answer: a
Explanation: The DMA controller can perform operations on
two different disks if the appropriate details are known.
Answer: c
Explanation: The controller takes over the processor’s
access cycles and performs memory operations.
Answer: d
Explanation: The controller is given full control of the
memory access cycles and can transfer blocks at a faster
rate.
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Answer: a
Explanation: The controller stores the data to transfered in
the buffer and then transfers it.
Answer: b
Explanation: The BUS arbitrator is used overcome the
contention over the BUS possession.
Answer: c
Explanation: None.
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Answer: d
Explanation: The process requesting the transfer is paused
and the operation is performed , meanwhile another
process is run on the processor.
Answer: c
Explanation: The transfer can only be initiated by instruction
of a program being executed.
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sanfoundry.com
Answer: b
Explanation: The BUS arbitrator is used to allow a device to
access the BUS based on certain parameters.
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c) BUS arbitrator
d) Controller
View Answer
Answer: a
Explanation: The device which is currently accessing the
BUS is called as the BUS master.
Answer: a
Explanation: In this approach the processor takes into
account the various parameters and assigns the BUS to
that device.
Answer: c
Explanation: None.
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a) Priority
b) Parallel
c) Single
d) Daisy chain
View Answer
Answer: d
Explanation: None.
Answer: b
Explanation: The Grant signal is passed from one device till
the other until the device that has requested is found.
Answer: d
Explanation: The BUS master is the one that decides which
will get the BUS.
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Answer: a
Explanation: The BUS busy activated indicates that the
BUS is already allocated to a device and is being used.
Answer: b
Explanation: None.
Answer: b
Explanation: After the device completes the operation it
releases the BUS and the processor takes over it.
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Answer: c
Explanation: None.
Answer: d
Explanation: The device uses a 4bit ID number and based
on this the BUS is allocated.
Answer: a
Explanation: None.
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Answer: c
Explanation: The OR output of all the 4 lines is obtained
and the device with the larger value is assigned the BUS.
15. If two devices A and B contesting for the BUS have ID’s
5 and 6 respectively, which device gets the BUS based on
the Distributed arbitration
a) Device A
b) Device B
c) Insufficient information
d) None of the mentioned
View Answer
Answer: b
Explanation: The device Id’s of both the devices are passed
on the lines and since the value of B is greater after the Or
operation it gets the BUS.
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sanfoundry.com
Answer: a
Explanation: The BUS is used to allow the passage of
commands and data between cpu and devices.
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Answer: c
Explanation: The BUS are classified into different types for
convenience of use and depending on the device.
Answer: d
Explanation: The device which starts the data transfer is
called as initiator.
Answer: a
Explanation: The device which recieves the commands
from the initiator for data transfer.
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Answer: b
Explanation: The devices recieve their timing signals from
the clock line of the BUS.
Answer: c
Explanation: The time taken for the signal to reach the BUS
from the device or the circuit accounts for this delay.
Answer: d
Explanation: The time for which the data is held is larger
than the time taken for propogation delay and setup time.
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Answer: a
Explanation: None.
Answer: d
Explanation: None.
Answer: b
Explanation: The slave once it recieves the commands and
address from the master strobes the ready line indicating to
the master that the commands are recieved.
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Answer: a
Explanation: The signal activated by the master in the
asynchronous mode of transmission is used to intimate the
slave the required data is on the BUS.
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b) False
View Answer
Answer: a
Explanation: The devices with variable speeds are
connected using asynchronous BUS, as the devices share
a master-slave relationship.
Answer: b
Explanation: This signal is activated by the master to tell the
slave that the required commands are on the BUS.
Answer: a
Explanation: The signal is used to scan and connect to
input or output devices.
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Answer: a
Explanation: The line is used to monitor the devices usage
for a process.
Answer: b
Explanation: The command is used to initiate a read from
memory operation.
Answer: c
Explanation: None.
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Answer: d
Explanation: The asynchronous transmission is termed as
Hand-Shake transfer because the master intimates the
slave after each step of the transfer.
Answer: a
Explanation: This mode of transmission is suitable for
multiple device situation as it supports variable speed
transfer.
Answer: b
Explanation: None.
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sanfoundry.com
Answer: a
Explanation: The interface circuits act as an hardware
interface between the device and the software side.
2. The side of the interface circuits, that has the data path
and the control signals to transfer data between interface
and device is _____
a) BUS side
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b) Port side
c) Hardwell side
d) Software side
View Answer
Answer: b
Explanation: This side connects the device to the
motherboard.
Answer: c
Explanation: Once the address is put on the BUS the
interface circuit decodes the address and uses the buffer
space to transfer data.
Answer: a
Explanation: By doing this the interface circuits provides a
better interconnection between devices.
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a) Timing skew
b) Memory access delay
c) Latency
d) None of the mentioned
View Answer
Answer: a
Explanation: None.
Answer: a
Explanation: The interface circuits generates the required
clock signal for the synchronous mode of transfer.
Answer: c
Explanation: The circuit holds the flags which are required
for data transfers.
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a) KIPs
b) Pc
c) Mainframe
d) Intelligent terminals
View Answer
Answer: d
Explanation: None.
Answer: a
Explanation: In batch processing systems the processes
are grouped into batches and they’re executed in batches.
Answer: c
Explanation: When the processor is busy with the process
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Answer: a
Explanation: The bridge circuit is basically used to extend
the processor BUS to connect devices.
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Answer: c
Explanation: The PCI BUS is used as an extension of the
processor BUS and devices connected to it, is like
connected to the Processor itself.
Answer: b
Explanation: The ISA is a architectural standard developed
by IBM for its PC’s.
Answer: a
Explanation: The ANSI is one of the standard architecture
used by companies in designing the systems.
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c) HDMI
d) SCSI
View Answer
Answer: d
Explanation: The SCSI BUS is used to connect the video
devices to processor by providing a parallel BUS.
Answer: b
Explanation: The SCSI BUS is used to connect disks and
video controllers.
Answer: a
Explanation: The ISO is yet another architectural standard,
used to design systems.
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b) SUN-SPARC
c) PC-AT
d) None of the mentioned
View Answer
Answer: c
Explanation: None.
Answer: a
Explanation: None.
Answer: a
Explanation: The IDE interface is used to connect the
harddisk to the processor in most of the Pentium
processors.
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sanfoundry.com
Answer: c
Explanation: The signal generated upon the pressing of a
button is encoded by the encoder circuit into the
corresponding ASCII value.
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b) Debouncing circuit
c) Multiplexer
d) XOR circuit
View Answer
Answer: b
Explanation: When the button is pressed,the contact
surfaces bounce and hence it might lead to generation of
multiple signals.In order to overcome this we use
Debouncing circuits.
Answer: c
Explanation: The parallel port transfers around 8 to 16 bits
of data simultaneously over the lines, hence increasing
transfer rates.
Answer: b
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Answer: a
Explanation: The parallel mode of data transfer is costly as
it involves data being sent over parallel lines.
Answer: d
Explanation: None.
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Answer: b
Explanation: The circuit is implemented using the edge
triggered D flip flop, that is triggered on the rising edge of
the valid signal.
Answer: b
Explanation: The idle signal is used to check if the device is
idle and ready to receive data.
Answer: a
Explanation: This register is used to control the flow of data
from the DATAOUT register.
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Answer: a
Explanation: None.
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Answer: d
Explanation: In isochronous mode of transmission, each bit
of the data is sent per each cycle.
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c) Shift registers
d) None of the mentioned
View Answer
Answer: c
Explanation: The Shift registers are used to output the data
in a desired format based on the need.
Answer: a
Explanation: The serial port is used to connect keyboard
and other devices which input or output one bit at a time.
Answer: a
Explanation: None.
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Answer: b
Explanation: The ports are made more flexible by enabling
the input or output of different clock signals for different
devices.
Answer: c
Explanation: The UART is a standard developed for
designing serial ports.
Answer: d
Explanation: None.
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Answer: a
Explanation: This basically means that the data transfer is
done in asynchronous mode.
Answer: c
Explanation: This is a standard which acts as a protocol for
message communication involving serial ports.
Answer: a
Explanation: None.
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Answer: c
Explanation: The PCI BUS has a closer resemblance to
IBM architecture.
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View Answer
Answer: a
Explanation: The NuBUS is an extension of the processor
BUS in Macintosh PC’s.
Answer: b
Explanation: The PCI BUS was the first to introduce plug
and play interface for I/O devices.
Answer: a
Explanation: The PCI BUS is used as an extension for the
processor BUS.
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View Answer
Answer: d
Explantion: The PCI BUS is mainly built to provide a wide
range of connectivity for devices.
6. ______ address space gives the PCI its plug and play
capability.
a) Configuration
b) I/O
c) Memory
d) All of the mentioned
View Answer
Answer: a
Explanation: The coniguration address space is used to
store the details of the connected device.
Answer: c
Explanation: The PCI bridge is circuit that acts as a bridge
between the BUS and the memory.
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a) True
b) False
View Answer
Answer: b
Explanation: The address is stored by the slave in a buffer
and hence it is not required by the master to hold it.
Answer: a
Explanation: The Master is also called as initiator in PCI
terminology as it is the one that initiates a data transfer.
Answer: b
Explanation: None.
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Answer: a
Explanation: None.
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Answer: b
Explanation: Each of the devices connected to the BUS will
be allocated an address during the initialisation phase.
Answer: c
Explanation: The interrupt request lines are used by the
devices connected to raise the interrupts.
Answer: a
Explanation: The FRAME signal is used to indicate the time
required by the device.
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Answer: d
Explanation: The signal is used to enable a 4 command
lines.
Answer: c
Explanation: The initiator transmits this signal to tell the
target that it is ready.
Answer: b
Explanation: None.
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Answer: c
Explanation: This is signal is activated by the device after it
as recognised the address and commands put on the BUS.
Answer: d
Explanation: This signal is used to initialisation of device
select.
Answer: a
Explanation: The PCI BUS allows only 21 devices to be
connected as only the higher order 21 bits of the 32 bit
address space is used to specify the device.
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Answer: b
Explanation: The SCSI BUS can overlap various data
transfer requests by the devices.
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d) Target Controller
View Answer
Answer: d
Explanation: The initiator involves in arbitration process and
after winning the BUS it’ll handover the control to the target
controller.
Answer: a
Explanation: The processor or the controller is unaware of
the data being transfered.
Answer: b
Explanation: None.
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View Answer
Answer: a
Explanation: This signal is generally initiated when the BUS
is currently occupied in an operation.
Answer: b
Explanation: This signal is usually asserted during the
selection or reselection process.
Answer: d
Explanation: The ATN signal is short for attention, which is
used to initimate the target that the initiator sent a message
to it.
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Answer: c
Explanation: None.
Answer: b
Explanation: None.
Answer: a
Explanation: The SCSI uses distributed arbitration to select
the device to give the BUS control.
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Answer: a
Explanation: The SCSI BUS is one of the expansion BUSes
used in a system.
Answer: d
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Answer: b
Explanation: The SCSI BUS which is narrow is capable of
transfering 8 bits of data at a time.
Answer: c
Explanation: These type of signals are a common feature of
the SCSI BUS.
Answer: a
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Answer: d
Explanation: To increase the transmission rate in SCSI in
SE mode of transfer the wire length is restricted to 1.6m.
Answer: c
Explanation: None.
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Answer: a
Explanation: This is used to co-ordinate and monitor the
data transfer over the BUS.
Answer: b
Explanation: None.
Answer: c
Explanation: The data is stored on the disk in the form of a
collection of blocks called as sectors.
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Answer: d
Explanation: The USB has two rates of operation the low-
speed and the full-speed one.
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d) ANSI
View Answer
Answer: c
Explanation: The high-speed mode of operation was
introduced with USB 2.0,which enabled the USB to operatte
at 480 Mb/s.
Answer: c
Explanation: The isochronous process means each bit of
data is seperated by a time interval.
Answer: d
Explanation: The USB has a tree structure with the root hub
at the centre.
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b) Subordinate roots
c) Left sub trees
d) Right sub trees
View Answer
Answer: a
Explanation: The I/o devices form the leaves of the
structure.
Answer: b
Explanation: The USB does a serial mode of data transfer.
Answer: b
Explanation: It allows only the host to communicate with the
devices and not between themselves.
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View Answer
Answer: b
Explanation: None.
Answer: c
Explanation: The USB’s root is connected to the processor
directly using the BUS.
Answer: d
Explanation: To make it easier for recognition the devices
are given 7 bit addresses.
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View Answer
Answer: b
Explanation: The USB memory space is not under any
address sapces and cannot be accessed.
Answer: b
Explanation: By standard the usual address of a new device
is zero.
Answer: a
Explanation: None.
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Answer: c
Explanation: This means that the pipe is bi-directional in
sending messages or information.
Answer: d
Explanation: This means that the usb gets both data and
control signlas required for the transfer operation.
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Answer: a
Explanation: The PID is the field that is used to identify the
device (the device id).
Answer: a
Explanation: The fields are transmitted twice, once with the
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Answer: d
Explanation: The last 5 bits of the packet is used for error
checking, that is cyclic redundancy check.
Answer: d
Explanation: The CRC bits are calculated based on the
values of the address and endp.
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Answer: c
Explanation: None.
Answer: d
Explanation: The above are all the common features of the
USB.
Answer: a
Explanation: To support the isochronous mode of operation
the usb transmission is divided into frames.
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Answer: b
Explanation: The SOF(State Of Frame) is used to inidicate
the beginning of a new frame.
Answer: c
Explanation: None.
Answer: a
Explanation: None.
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