2344
4, AUGUST 2007
A Reduced-Switch-Count Five-Level Inverter With
Common-Mode Voltage Elimination for an
Open-End Winding Induction Motor Drive
Gopal Mondal, K. Gopakumar, Senior Member, IEEE, P. N. Tekwani, and Emil Levi, Senior Member, IEEE
Abstract—The paper presents a five-level inverter scheme with
reduced power circuit complexity for an induction motor drive.
The scheme is realized by cascading conventional two-level and
three-level neutral point clamped inverters in conjunction with an
open-end winding three-phase induction motor drive. An inverter
control scheme with common-mode voltage (CMV) elimination,
along with a simple dc link voltage control, is developed by using
only switching states with zero CMV for the entire modulation
range. Theoretical considerations are experimentally verified for
a variety of operating conditions.
Index Terms—Common-mode voltage (CMV) elimination, in-
duction motor drives, multilevel inverter, open-end winding
structure.
I. I NTRODUCTION
M ULTILEVEL inverters are nowadays the preferred
choice for high-voltage and high-power applications in
industry [1]–[11]. Typically, as the voltage level increases,
the power circuit complexity increases as well. Pulsewidth-
modulated inverters generate an alternating common-mode
voltage (CMV) at the motor terminals, which results in leakage
current. This unwanted current causes bearing erosion and
motor failure. It is therefore desirable to eliminate or at least
reduce the CMV. Various strategies have been developed for re-
duction of the CMV in three-phase ac drives, and one approach,
which is well suited to drives that are supplied from a multilevel
inverter, consists of the design of modified pulsewidth mod-
ulation (PWM) strategies that select only inverter states with
reduced CMV. Such a PWM strategy for CMV reduction in the
three-level neutral-point-clamped (NPC) inverter supplied drive
is discussed in [12], whereas a CMV reduction method for the
cascaded H-bridge inverters is elaborated in [13].
If a three-phase machine has a so-called open-end winding
(instead of the star-connected) structure of the stator winding,
new possibilities with regard to CMV reduction/elimination
Manuscript received November 1, 2006; revised January 23, 2007.
G. Mondal and K. Gopakumar are with the Centre for Electronics Design
and Technology, Indian Institute of Science, Bangalore 560012, India.
P. N. Tekwani is with the Centre for Electronics Design and Technology,
Indian Institute of Science, Bangalore 560012, India, and also with the Institute
of Technology, Nirma University of Science and Technology, Ahmedabad
382481, India.
E. Levi is with the School of Engineering, Liverpool John Moores University,
L3 3AF Liverpool, U.K.
Digital Object Identifier 10.1109/TIE.2007.899927
0278-0046/$25.00 © 2007 IEEE
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO.
open up. Such a machine’s structure has been considered as
a serious contender for high-power applications (traction and
similar) since the early 1990s [2]. In more recent times, it is
looked at as a possible solution for electric vehicles/hybrid
electric vehicles [14], distributed energy generation systems
[15], and electric ship propulsion [16], [17]. The basic idea is
to supply the machine from both ends using inverters with a
certain (small) number of levels [2], [3], which results in mul-
tilevel voltage across stator phase windings. Depending on the
power level of the drive, two inverters that are connected at the
two ends of the stator winding can be of the same power/voltage
rating and can operate at the same switching frequency, or they
can be of very different power/voltage ratings in which case
they operate at very different switching frequencies (the con-
cept of a “bulk” inverter operated at switching frequency equal
to the drive’s output frequency, and “conditioning” inverter, of
low power/voltage but operated at high switching frequency;
the intended application is for ship propulsion [16], [17]).
When inverters at both ends of the stator winding operate
in PWM mode, at the same switching frequency, it becomes
possible to devise strategies for complete CMV elimination
by selecting only those switching states that give zero CMV
[18]–[22]. The simplest open-end winding supply configuration
consists of connecting to each side of the winding a two-
level inverter [2], [3], [20]. The CMV elimination strategy for
such a structure has been developed in [19], [20]. It is also
possible to connect a two-level inverter at one side and two
cascaded two-level inverters (resulting in three-level structure)
at the other side [18]. Operation with zero CMV is again
possible by selecting appropriate switching states in the drive
operation [18]. Another three-level inverter configuration with
CMV elimination has been described in [21]. This three-level
inverter structure has a higher number of redundant switching
states for each voltage vector location as compared to the
conventional three-level NPC inverter. The CMV is once more
eliminated by using only switching states with zero CMV in the
generation of the reference voltage space vector.
A five-level inverter structure with CMV elimination is con-
sidered in [22] for an open-end winding induction motor drive.
The dual five-level structure is realized by connecting two
conventional two-level inverters and one conventional three-
level inverter, in series, at each side of the three-phase stator
winding. To eliminate the CMV, only switching states with
zero CMV are used for PWM control. It is observed that there
are more switching states present in the voltage space vector
MONDAL et al.: REDUCED-SWITCH-COUNT FIVE-LEVEL INVERTER WITH COMMON-MODE VOLTAGE ELIMINATION
Fig. 1. Power circuit of the nine-level inverter configuration formed by a dual
five-level inverter-fed open-end winding induction motor drive [22].
locations than are required to eliminate the CMV [22]. The
topology of [22] presents the starting point for the development
of the configuration described in this paper. From a thorough
study of the switching state redundancies available from the
power circuit presented in [22], it is observed that the power
circuit can be considerably simplified. In particular, two two-
level inverters are eliminated in the configuration analyzed here,
so that the topology is simplified and consists of a total of two
two-level and two three-level inverters. Although the numbers
of switching redundancies for the voltage vector locations are
lower in such a five-level inverter circuit, the CMV elimination
is still possible with the available switching states for the entire
range of operating speeds, as shown in the further development.
Developed power circuit and the PWM algorithm with com-
plete CMV elimination are experimentally verified on a 2.5-kW
open-end winding induction motor drive.
II. F IVE -L EVEL I NVERTER S CHEME W ITH R EDUCED
P OWER C IRCUIT C OMPLEXITY
The drive configuration of [22] is illustrated in Fig. 1. The
scheme uses a dual five-level inverter topology, where one
three-level and two two-level inverters are employed at each
side of the open-end winding induction motor drive. This results
in a voltage space vector structure that is equivalent to the
nine-level inverter topology [22]. With the proper selection of
the switching state combinations, motor phase voltages that
are equivalent to a five-level inverter with CMV elimination
have been realized, and the zero CMV has been experimentally
demonstrated for a number of operating conditions.
The configuration of Fig. 1 is now simplified to the one of
Fig. 2 by removing two two-level inverters. Hence, the drive
configuration of Fig. 2 consists of two three-level inverters
(inverter A and inverter A’) and two conventional two-level
inverters that are common to both three-level inverters. Taken
together, they again work as a dual five-level inverter that feeds
the open-end winding induction motor from both ends. The
power circuit of Fig. 1 uses a total of 48 switches, whereas the
circuit of Fig. 2, which is analyzed in the present paper, has a
total of 36 switches. Hence, a substantial reduction in the switch
count is achieved, as compared to [22], which leads to a simpler
2345
Fig. 2. Simplified dual five-level inverter-fed open-end winding induction
motor drive with CMV elimination developed in this paper.
TABLE I
POSSIBLE STATES OF THE SWITCHES FOR INVERTER SYSTEM A
OR I NVERTER S YSTEM A’
drive configuration. The switches are labeled in Fig. 2 as Sxy ,
where x = 1, . . . , 4 and y = 1, 2, . . . , 6. The maximum voltage
blocking capability that is required for the switches is Vdc /8 for
each switch of the two two-level inverters and Vdc /4 for each
switch of the NPC three-level inverters. For example, when the
switch S11 is “on,” the voltage across S14 is Vdc /8, and when
S14 is “on,” the voltage across S11 is Vdc /8. Similarly, when
S11 , S44 , S21 , and S24 are “on,” the combined voltage across
S31 and S34 is Vdc /2, so that the voltage across each switch is
Vdc /4 (assuming equal voltage sharing by two switches).
The power scheme of Fig. 2 gives a significant reduction
in the circuit complexity, as compared to Fig. 1, and it also
leads to a reduction of the number of redundant switching
states. However, the available switching states are still sufficient
for the CMV elimination, as shown shortly. As the inverter A
and inverter A’ of Fig. 2 share the two conventional two-level
inverters, some restrictions in the combined switching states
have to be added. This reduces the number of redundancies
in the switching states for the voltage space vector locations.
In the inverter structure of Fig. 2, there are 241 switching
states that are distributed over 61 voltage space vector locations.
Table I shows the states of the switches for obtaining different
voltage levels at the inverter poles (legs), where the pole (leg)
voltages are measured with respect to the dc-link midpoint
point “0” (Fig. 2). There are different complimentary pairs
of the switches. The complimentary pairs for phase A are
S11 –S14 , S21 –S34 , S24 –S31 , and S41 –S44 . For phase B, the
2346 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007
TABLE II
POSSIBLE COMBINATIONS OF VOLTAGE LEVELS FROM THE
INVERTER SYSTEM A AND INVERTER SYSTEM A’
complimentary switches are S13 –S16 , S23 –S36 , S26 –S33 , and
S43 –S46 , and those for phase C are S15 –S12 , S25 –S32 ,
S22 –S35 , and S45 –S42 . Each pole voltage (from both ends
of the drive system) can attain five different voltage levels
(Table I). To generate a voltage level “2” at pole A of inverter
system A (three-level inverter A and the two conventional two-
level inverters in series), the switches S11 , S21 , and S31 should
be on, and S41 can be in any state depending on pole A’
voltage level of inverter system A (three-level inverter A’ and
the two conventional two-level inverters in series). Let pole A of
inverter A be at voltage level “2” (Table I). To generate voltage
level “1” at pole A’ of inverter A’, switches S14 , S2
1 , and S3
1
should be “on” (Table I). Now, to attain these states for two
inverter systems, both switches S11 and S14 need to be “on.”
However, S11 and S14 are complimentary switches, and hence,
they cannot simultaneously be in “on” state. This implies that
inverter pole A and pole A’ cannot be at voltage level “2” and
voltage level “1,” respectively, at the same time. It can be shown
using similar reasoning that opposite poles of the same phase
of the motor cannot be at voltage level “−1” and voltage level
“−2” at the same time.
Table II shows the possible voltage levels that are obtainable
simultaneously from the inverter system A and inverter system
A’. The state of the switches for three different voltage levels
in inverter legs A and A’ is shown in Fig. 3. It is obtained on
the basis of Tables I and II. The same approach can be used to
find the switch transitions for the other two phases to obtain the
different voltage levels.
III. CMV E LIMINATION S TRATEGY
The voltage space vector structures of inverter system A
and inverter system A’, taken individually, produce a five-
level voltage space vector structure each. Since the individual
inverter systems at each side will produce a total of 125 (= 53 )
switching states (Table III—only 30◦ angular sector is shown),
which are distributed over 61 voltage space vector locations,
the combination of these switching states (five-level structure)
from two inverter systems will produce a nine-level voltage
space vector structure, this being the same as for the structure in
[22, Fig. 1].
CMV, which is generated by the inverters at the two ends
of the open-end winding induction motor, can be expressed as
follows. The CMV for inverter system A is defined as
VCMVA = (VAO + VBO + VCO )/3 (1)
and, similarly, for inverter system A’
VCMVA
= (VA
O
+ VB
O
+ VC
O
)/3. (2)
The equivalent CMV for the combined inverter system (CMV
generated at the inverter phases) is
VCMV = VCMVA − VCMVA
. (3)
It is observed from (3) that the resultant CMV VCMV can
be made zero either by individually making both VCMVA and
VCMVA
zero or by making them equal. It can be seen that from
all the available switching states of one inverter system (inverter
system A or inverter system A’), for 19 switching states, the
CMVs VCMVA and VCMVA
are zero, which results in a three-
level voltage space vector structure, as shown in Fig. 4. The
combinations of these 19 switching states (with zero CMV)
from the two inverter systems will produce a resultant five-level
voltage space vector structure (61 locations and 241 switching
combinations). However, all 241 switching state combinations
are not needed for PWM control with CMV elimination. In
the present study, only 103 switching state combinations are
used for the PWM control. These are shown in Fig. 5 and are
listed in Table IV. Switching states of Fig. 5 are selected in
such a way that the resultant pole voltage will have quarter
wave symmetry and will not contain even harmonics. Also,
the same switching states can be used for a simple dc-link
capacitor voltage balancing, as explained in Section V. The
five-level structure with CMV elimination is obtained from
the original nine-level structure by taking only voltage vec-
tors with zero CMV. Hence, there will be 15% reduction √ in
the fundamental voltage component, as the radius ( 3/2Vdc )
of the new hexagonal voltage space vector structure will be
smaller than the actual hexagon (Vdc ). Thus, to obtain the same
maximum fundamental phase voltage as with a conventional
five-level inverter,
√ a 15% boost can be given to the dc-link
voltage (2/ 3Vdc ) [22].
IV. E XPERIMENTAL R ESULTS
The developed five-level inverter-fed open-end winding in-
duction motor drive with CMV elimination scheme and reduced
switch count is experimentally tested on a 2.5-kW induction
motor drive with volts-per-hertz (V/f) control. The V/f control
scheme and the PWM signal generation are implemented on a
Digital Signal Processor (DSP) TMX320F240PQ, and Spartan
xc2s100 Field-Programmable Gate Array (FPGA) is used for
the switching state generation for different sectors. The inverter
switching frequency is kept at 2.5 kHz for the entire speed
range of operation. The scheme is examined throughout the
operating range by varying the modulation index from linear
range to 12-step operation. The algorithm for the generation of
level signals for the five-level inverter uses only the sampled
amplitude of the reference voltages, so that the use of lookup
table for sector identification is avoided, and the speed of
execution is increased [23]. A detailed description of the PWM
implementation scheme with sampled reference phase voltage
amplitudes for the entire modulation range is available in [23].
MONDAL et al.: REDUCED-SWITCH-COUNT FIVE-LEVEL INVERTER WITH COMMON-MODE VOLTAGE ELIMINATION 2347

Fig. 3. State of the switches for legs A and A’ (phase A) of Fig. 2, which leads to the different voltage levels. (a) Leg A at level “2;” leg A’ at level “−2.”
(b) Leg A at level “0;” leg A’ at level “−1.” (c) Leg A at level “1;” leg A’ at level “−2.”

TABLE III
SWITCHING STATES FOR THE VECTOR LOCATIONS OF 30◦ ANGULAR
SECTOR FOR INVERTER SYSTEM A OR INVERTER SYSTEM A’

Fig. 5. Switching states for individual voltage vector locations for the overall
inverter system with zero CMV.

Fig. 4. Locations of the voltage space vectors for the individual inverter
systems A or A’ with zero CMV.
The PWM signals and the level signals for three phases are
generated using the DSP controller.
The switching states (Table IV) are stored in the FPGA.
Fig. 5 shows the inverter switching states, which are used for the
PWM control, with zero CMV at each location. For the present
PWM control, from the available redundant switching states
(Table IV), two combinations at a certain location are used
for PWM control (Fig. 5). The switching states for the voltage
vectors are chosen in such a way that the switching losses of
the inverter systems are reduced due to the minimum number
of transitions. Also, the selected switching state combinations
can be effectively used for the dc-link capacitor voltage control,
as explained in the following section. Experimental results for
the PWM control in the innermost sectors are shown in Fig. 6.
Fig. 6(a) shows the pole voltage and phase voltage of the
inverter. The top and bottom traces are the pole voltages, and
the middle trace is the phase voltage. The motor phase voltage
(top trace) and the motor phase current (bottom trace) are
presented in Fig. 6(c). The fast Fourier transforms (FFTs) of
the pole voltage and phase voltage for the PWM control in the
inner hexagon are shown in Fig. 6(b) and (d), respectively. It
can be observed that there are no triplen harmonics in either the
pole voltage or the phase voltage. Experimental results for the
three-level operation are given in Fig. 7. Fig. 7(a) shows once
more the pole voltage (top and bottom traces) and the phase
2348 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007
TABLE IV
SWITCHING STATE COMBINATIONS WITH ZERO CMV, USED AT ALL VOLTAGE SPACE VECTOR LOCATIONS, FOR THE FIVE-LEVEL INVERTER-FED DRIVE
Fig. 6. PWM operation in the innermost (two-level) region. (a) y-axis:
1 div = 50 V; x-axis: 1 div = 20 ms. (c) y-axis: 1 div = 50 V and 1 div =
5 A; x-axis: 1 div = 20 ms. (b), (d) Normalized amplitude versus harmonic
order.
voltage (middle trace) of the inverter, whereas Fig. 7(c) shows
the motor phase voltage (top trace) and the motor phase current
(bottom trace). The FFTs of the leg voltage and phase voltage
are shown in Fig. 7(b) and (d), respectively. The absence of
triplen harmonics in the pole voltage and in the phase voltage
for the three-level operation is evident from the FFT spectra
results. Identical measurements have also been performed for
the 4-level, 5-level, and, finally, 12-step operations of this drive
system. Experimental results for these operating modes are
shown in Figs. 8–10. In all these figures, the same set of results
is depicted as already described in conjunction with Figs. 6
and 7. It is evident from the spectrum analysis shown in
Figs. 8–10 that the CMV elimination is provided in all
the possible operating modes of the drive system. Hence,
the experimental results confirm that the proposed inverter
structure of reduced power circuit complexity is capable of
producing a five-level voltage structure with zero CMV under
all operating conditions.
V. O PEN -L OOP C ONTROL OF DC-L INK C APACITOR
V OLTAGE B ALANCING
The explanations provided so far are related to the strategy
for the CMV elimination by selecting only the switching states
that have zero CMV. However, the switching states (Fig. 5)
are selected in such a way that the outer two capacitor (C4
and C1 ) and inner two capacitor (C2 and C3 ) voltages are
kept balanced. For example, during PWM control, switching
MONDAL et al.: REDUCED-SWITCH-COUNT FIVE-LEVEL INVERTER WITH COMMON-MODE VOLTAGE ELIMINATION
Fig. 7. PWM operation in the three-level region. (a) y-axis: 1 div = 50 V;
x-axis: 1 div = 20 ms. (c) y-axis: 1 div = 50 V and 1 div = 5 A; x-axis:
1 div = 20 ms. (b), (d) Normalized amplitude versus harmonic order.
Fig. 8. Four-level operation. (a) y-axis: 1 div = 100 V; x-axis: 1 div =
10 ms. (c) y-axis: 1 div = 100 V and 1 div = 5 A; x-axis: 1 div = 10 ms.
(b), (d) Normalized amplitude versus harmonic order.
states (0 − 11, 10 − 1) and (−101, 01 − 1) are used for the
voltage space vector B8 . Fig. 11(a) and (b) shows the currents
through the capacitors for the switching states (0 − 11, 10 − 1)
and (−101, 01 − 1), respectively. From Fig. 11(a), the current
through capacitors C4 and C1 is iA + iB + iC , and the currents
through C3 and C2 are iB and iA , respectively. Next, Fig. 11(b)
shows that the current through C4 and C1 is again iA + iB +
iC , and currents through C3 and C2 are now interchanged to iA
and iB , respectively. These two switching states are selected
in consecutive sampling interval for the voltage vector B8 .
Now, this means that after two consecutive sampling intervals,
there will be identical voltages across C4 and C1 and across
C3 and C2 since the same current will pass through these
pairs of capacitors after two sampling intervals. Fig. 11(c)
shows the current through the capacitors for the switching state
2349
Fig. 9. Five-level operation. (a) y-axis: 1 div = 100 V; x-axis: 1 div =
5 ms. (c) y-axis: 1 div = 160 V and 1 div = 5 A; x-axis: 1 div = 10 ms.
(b), (d) Normalized amplitude versus harmonic order.
Fig. 10. Operation in 12-step mode. (a) y-axis: 1 div = 100 V; x-axis:
1 div = 5 ms. (c) y-axis: 1 div = 200 V and 1 div = 5 A; x-axis: 1 div = 5 ms.
(b), (d) Normalized amplitude versus harmonic order.
(0 − 11, 01 − 1) for the voltage vector B9 . For the switching
state (0 − 11, 01 − 1), the current through C4 and C1 is iA +
iB , and there is no phase current through C3 and C2 , which
results in identical voltages across C4 and C1 and identical
voltages across C3 and C2 . It is therefore possible to simplify
the power circuit by reducing the number of dc sources from
four in the power circuit of Fig. 2 to two, as shown in Fig. 12. In
Fig. 12, a dc source of Vdc /4 is connected across the inner two
capacitors, and a dc source of Vdc /2 is connected across all the
four capacitors. Therefore, the total voltage across C1 and C4
and the total voltage across C2 and C3 are fixed to Vdc /4. It thus
follows that the voltage balance of all the four capacitors will be
enabled by keeping the inner two capacitor voltages and outer
two capacitor voltages equal after a maximum of two sampling
2350
Fig. 11. (a), (b) Phase connections and the currents through the capacitors for
the switching states of the voltage vector B’8. (c) Phase connection and the
capacitor currents for the switching states of the voltage vector B’9.
Fig. 12. Proposed power circuit with dc-link balancing and common-mode
voltage elimination.
intervals. Fig. 13 shows the phase voltage, the phase current,
and the voltages across the capacitors for the motor accelerating
from zero speed to the five-level mode of operation. The traces
confirm that the present PWM control is capable of balancing
the voltage across all the four capacitors. However, if there
is a momentary short circuit that results in a mismatch in
the capacitor voltages, this strategy cannot bring the capacitor
voltages to the balanced condition. To take the corrective action
for such conditions, a closed loop control would be required.
Capacitor voltages would have to be sensed, and the correct
inverter switching state to balance the capacitor voltages would
have to be correspondingly switched. Development of such a
closed-loop control scheme is, however, beyond the scope of
this paper.
VI. C ONCLUSION
A five-level inverter scheme for the open-end winding induc-
tion motor drive is proposed in the paper, with a reduced power
circuit complexity when compared to the existing scheme. The
five-level structure is realized by cascading two conventional
two-level and three-level inverters. The inverter systems at
two machine ends produce a five-level voltage space vector
structure, and the combined system from both ends produces
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007
Fig. 13. (a) Phase voltage and current for the motor accelerating from zero
speed to the five-level mode of operation. (b) Voltages across the capacitors for
this acceleration transient.
a nine-level voltage space vector structure for the drive system.
For the present study, the switching state combinations (from
both ends) with zero CMV are chosen for the PWM control,
which results in the five-level inverter-fed drive. Such five-level
inverter-fed induction motor drive scheme generates zero CMV;
hence, all the problems associated with the presence of CMV
variation (such as bearing currents, early motor failure, etc.) are
also eliminated from the drive system. Since CMV is elimi-
nated, the combined inverter system can be fed from a single
dc link. The present scheme requires a significantly smaller
number of switches when compared to the five-level inverter
for the open-end winding induction motor (obtained by cascad-
ing two-level and three-level inverters at each winding side),
previously reported, while enabling the same quality of per-
formance. There are fewer switches, and the switching loss in
the converter is therefore reduced. As two two-level inverters
have been eliminated, when compared to the previous work,
the cost and complexity of the power circuit will be lower. The
power circuit is modular in nature and relies on the utilization
of only conventional inverter structures, so that a simple power
bus structure is possible. The present scheme gives a reduced
number of switching state redundancies, as compared to the
previous scheme of [22]. However, the available redundancies
are sufficient and can be effectively utilized for CMV elimina-
tion; moreover, a simple dc-link capacitor voltage balancing is
also possible, as demonstrated in the paper. This further reduces
the power circuit complexity due to a reduction in the number of
required dc-link power supplies. The proposed scheme is exper-
imentally verified on a 2.5-kW induction motor drive for differ-
ent modulation indexes up to and including the 12-step mode.
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2351
Gopal Mondal received the B.E. degree from the
College of Engineering and Management, Kolaghat,
West Bengal, India, and the M.E. degree in control
systems from Jadavpur University, Calcutta, West
Bengal. He is currently working toward the Ph.D.
degree in power electronics at the Centre for Elec-
tronics Design and Technology, Indian Institute of
Science, Bangalore, India.
K. Gopakumar (M’94–SM’96) received the B.E.,
M.Sc. (Eng.), and Ph.D. degrees from the Indian
Institute of Science, Bangalore, India, in 1980, 1984,
and 1994, respectively.
He was with the Indian Space Research Organiza-
tion from 1984 to 1987. He is currently an Associate
Professor at the Centre for Electronics Design and
Technology, Indian Institute of Science. His fields of
interest are power converters, pulsewidth modulation
techniques, and ac drives.
Mr. Gopakumar is an Associate Editor of the IEEE
TRANSACTIONS ON INDUSTRIAL ELECTRONICS.
P. N. Tekwani received the B.E. degree (Uni.
First, Gold Medallist) in power electronics from
the Saurashta University (LEC), Morbi, India, in
1995 and the M.E. degree in electrical engineering
(Industrial Electronics, First Rank) from the M. S.
University of Baroda, Vadodara, India, in 2000. He
is currently working toward the Ph.D. degree at
the Centre for Electronics Design and Technology,
Indian Institute of Science, Bangalore, India.
From 1995 to 1996, he was with the Amtech
Electronics Pvt. Ltd., Gandhinagar, India. From 1996
to 2001, he was with the Electrical Research and Development Association,
Vadodara. Since 2001, he has been a member of the faculty in the Institute of
Technology, Nirma University of Science and Technology, Ahmedabad, India.
Emil Levi (S’89–M’92–SM’99) was born in
Zrenjanin, Serbia, in 1958. He received the Dipl. Ing.
degree from the University of Novi Sad, Novi Sad,
Serbia, in 1982 and the M.Sc. and Ph.D. degrees
from the University of Belgrade, Belgrade, Serbia,
in 1986 and 1990, respectively.
From 1982 to 1992, he was with the Department of
Electrical Engineering, University of Novi Sad. He
joined Liverpool John Moores University, Liverpool,
U.K., in May 1992. Since September 2000, he has
been a Professor of electric machines and drives
at the same university. He has extensively published in major journals and
conference proceedings.
Dr. Levi is an Associate Editor of the IEEE TRANSACTIONS ON
INDUSTRIAL ELECTRONICS and is a member of the Editorial Board of the
IEE Proceedings—Electric Power Applications.