Multiple Closed Loop System Control with Digital
PID Controller Using FPGA
Şirin AKKAYA
Control and Automation Engineering Department
Istanbul Technical University
Istanbul, Turkey
sakkaya@itu.edu.tr
Abstract— PID (Proportional – Integral - Derivative)
controllers are the most widely used closed loop controllers due
to their simplicity, robustness, effectiveness and applicability for
much kind of systems. With the rapid development of technology,
implementation of PID controller has gone several steps from
using analog components in hardware to using some software-
based program to execute PID instructions digitally in some
processor-based systems. And also, these developments have
brought an alternative solution to implement PID instructions in
Programmable Logic Devices (PLD). Field Programmable Logic
Array (FPGA) is the most advanced members of PLDs. This
paper presents the digital PID algorithm on FPGA. The
controller algorithm is developed using VHDL and implemented
using Altera DE0 Nano Board. As the controlled system, five axis
robot arm is selected, which have five dc motor and four
potentiometer to determine the positions of motors. The results
show that digital PID controller and also multi-feedback control
systems can be implemented successively using FPGA devices.
Keywords—fpga, digital pid, pwm, vhdl, robot arm
I. INTRODUCTION
The new and effective theories and design methodologies
are being continually developed in the automatic control field,
however, Proportional – Integral – Derivative (PID) controllers
are still the most widely adopted controllers in industry. Owing
to the advantage of simple structure, good stability, reliable
operation, robustness and effectiveness, the PID controllers are
properly used in different areas such as aerospace, process
control, manufacturing, robotic, automation, transportation
systems and real time multi tasking applications.
The implementation of PID control has same evolutionary
stages from the early mechanical and pneumatic designs to
software based microcontroller systems. But these systems
encounter some difficulties such as overloading or computing
speed limits to implement the requirements of modern control
systems. Recently, Field Programmable Gate Arrays (FPGA)
has become alternative solution for the realization of digital
control systems, particularly PID [1]. And some works about
how to implement PID controller using FPGA has begun to be
published. In [2], the basic discrete PID equation and algorithm
is given, and in addition to PID algorithm in [3], some
peripheral interfaces (analog to digital converter and digital to
Analog converter) are introduced, in [4], to verify the design
This project is supported by Yildiz Technical University Scientific
Research Projects Coordination Unit under rule 2012-04-04-YL02.
978-1-4799-6773-5/14/$31.00 ©2014 IEEE
Onur Akbatı and Haluk Görgün
Control and Automation Engineering Department
Yildiz Technical University
Istanbul, Turkey
oakbati@yildiz.edu.tr, gorgun@yildiz.edu.tr
performance a sine micro stepping driver system model of
stepper motor is introduced. Different types of digital PID
algorithm based on parallel, serial and mixed architecture is
implemented and simulated in [5]. The structure proposed in
[6] is based on a distributed arithmetic algorithm where, a
Look-Up-Table mechanism inside the FPGA is utilized and in
[7] System on a Programmable Chip (SOPC)-based PID
controller Intellectual Property (IP) core is implemented on
FPGA using hardware description language.
For a low voltage synchronous buck converter, FPGA
based PID controller is designed and implemented in [8]. And
also, FPGA has been used in motion control systems which are
employed all sort of robotic applications, such as in [9] and
[10], a technique has been adopted for the generation of the
control input for controlling the DC motor driver circuit and
decoding the optical encoder data for using it for speed
feedback in the PID control loop. In [11], an FPGA controller
is designed and programmed to control the speed of the
permanent magnet DC motor of a portable dough mixing
machine, using digital PID algorithm with PWM signals. In
[12], a simple approach for designing a fractional order FPGA
based PI controller for controlling the speed of a DC motor is
presented and in [13], for multi-axis systems a high
performance PID IP core controller is described. In [14] the
design and implementation of a fuzzy-control based speed
control IC for permanent magnet synchronous motor is
presented, with Simulink/Modelsim co-simulation and FPGA
realization. And also robotic control applications are one of the
most recent targeted fields covered by FPGA. For a three
degree-of-freedom (DOF) wafer-handling robot, three current
vector controllers, three position/speed controllers and one
trajectory planning are implemented in a single FPGA chip
[15]. For a modular reconfigurable robot controller is proposed
which based on the Advanced RISC Machine (ARM)
processor and FPGA [16].
In this paper, the design and implementation of a FPGA-
based digital PID controller for a five axis robot arm is
presented. The organization of this paper is as follows: In
section II, digital PID controller algorithm, five axis robot arm
and FPGA development board are described, in section III, the
implementation of analog input interface, digital PWM block
and digital PID block implemented in FPGA and the results are
discussed. In section IV, the conclusion of the work is given.
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 II.STRUCTURE OF CLOSED LOOP CONTROL SYSTEM u[k ] = K p e[k ] + ui [k − 1] + K i e[ k ] + K d (e[k ] − e[ k − 1]) (5)
The overall block diagram of the system is shown in Fig. 1. where K i is the integral gain, K d is the derivative gain, e[k]
is the current error signal, e[k-1] is the previous error signal
r[ k ] e[k ] u[k ] y (t ) and u[k] is the control signal, u[k-1]is the previous integral
control signal. The discrete PID algorithm given (5) is known
b[k ] as the absolute form or position form of PID algorithm [17].

B. The Controlled System

To show the applicability of the algorithm in multi-
feedback control systems, a basic five axis robot arm selected
Fig. 1. The block diagram of the system as a controlled system is shown in Fig. 2.

Where r[k] is the discrete reference signal, e[k] is the

discrete error signal, b[k] is the discrete feedback signal, u[k]
is the controller output and y(t) is the output of the controlled
system. In FPGA, there are three block; digital PID controller
block, analog input interface and digital PWM block.
A. Digital PID Controller
The PID algorithm consists of three basic modes as
Proportional mode, Integral mode and Derivative mode. The
general form of PID controller given in (1);
Fig. 2. Five axes robot arm
1 t de(t )
u (t ) = K p (e(t ) +
Ti ∫0 e(t )dt + Td dt ) (1)
The robot arm has a five axes pick-and-place manipulator
which consists of mechanical parts forming a rotating base,
three links and a gripper with dc motors and rotary
where K p is a proportional gain, Ti is integral time constant potentiometers and motor driver units. Each of these axes is
and Td is derivative time constant. For a small sample time Ts , driven by a small DC electric motor. These five axes consist of
(1) can be turned into a difference equation with approximating a shoulder, elbow and wrist having 180, 270 and 90 degree
the derivative mode by backward difference approximation and rotational limits respectively for vertical movement, and the
the integral mode by backward integration rule. axes at base has 270 degree rotational limit for horizontal
movement. The potentiometer is an electro mechanic device
k
used for measuring the angular position of the motor in terms
Ts Td
u[ k ] = K p ( e[ k ] +
Ti ∑ e[n] + T
n =0 s
(e[ k ] − e[ k − 1])) (2) of voltage levels. The motor driver unit is an electronic circuit
which links the controller and the robotic arm; adjust the
voltage level to control motor direction and speed according to
Parallel PID algorithm is also shown in (3) as sum of three controller’s output. The basic driver unit generally consists of
basic blocks, where u p [k ] is proportional part, u i [k ] is H-bridge as an integrated circuit in a chip or can be built from
discrete components. L298 chip is well known H-bridge which
integral part and u d [k ] is derivative part of algorithm. allows driving DC motor in both directions and adjusts the
speed with PWM inputs. A driver unit can drive two motors
u[k ] = u p [k ] + u i [k ] + u d [k ] (3) simultaneously, so three units are used to control five DC
motors.
The robotic arm is designed for training purpose, but there
u p [k ] = K p e[k ]
is not enough information about the parameters of the dc motor
K p Ts k
K p Ts k −1
K p Ts and the material. So to obtain the mathematical model of the
u i [k ] =
Ti ∑ e[k ] = Ti ∑ e[k ] + Ti
e[k ] robotic arm, each of the joint is considered as a separated
n=0 n =0 system and the linear model of each axis (motor and
K p Ts (4) mechanical load) are created by using model based system
u i [k ] = u i [k − 1] + e[k ] identification technique. The basic idea of this technique
Ti
depends on applying a sinusoidal signal to a linear system as an
K p TD input; and measuring the sinusoidal output with the same
u d [k ] = (e[k ] − e[k − 1])
Ts frequency but different amplitude and phase. The model of the
each joint is thought as motor and mechanical load and the
By using (4), (3) can be written as below; schematic diagram is shown in Fig. 3 and the estimated transfer
function is shown in (6) for each joint of the robotic arm [18].

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θ m (t)
Fig. 3. The diagram of the motor and the mechanical load [20]
θ m ( s) 1 /( Ra J m ) A (6)
= =
E a (s) s[s + (1 J m )( Dm + ( K t K b Ra ))] s(s + B )
where θ m is the position of motor, Ea is the armature voltage,
Ra is the armature resistance, K t and K b the motor constants,
J m is the equivalent inertia of the motor and the load and Dm
is the equivalent constant of friction of the motor and the load.
To obtain the linear model of each joint of robotic arm the
testing system is created as in Fig. 4.
Fig. 4. The testing system for system identification
As seen in Fig. 4, the input signal (AC 30Vpp) which is given
the motor is shown in Channel 1 and the output signal which is
taken from potentiometer is shown in Channel 2 of
oscilloscope. The graphics for axes of robots is given in Fig 5
and Fig 6.
Fig. 5. The graphics for axis 1 and axis 2 (Channel 1: 5.00 V/Div, 50.0
ms/Div - Channel 2: 100.0 mV/Div Time/Div - 50.0 ms/Div)
Fig. 6. The graphics for axis 3 and axis 4 (Channel 1: 5.00 V/Div, 50.0
ms/Div - Channel 2: 50.0 mV/Div Time/Div - 50.0 ms/Div)
To compare these signal values the mathematical model of
each joint is obtained for base, shoulder, elbow, and wrist
respectively and the results are shown in Fig. 7.
θ 4 (s) 0.492
=
E4 (s) s(s + 30.9)
θ3 (s) 0.8232
=
E3 (s) s (s+ 28.10)
θ 2 (s) 0.7374
E2 (s)
=
s(s+ 24.55)
θ1 (s) 0.58
=
E1 (s) s (s+ 19.44)
Fig. 7. The mathematical model for each joint of robotic arm
C. FPGA Development Board
FPGA, a PLD is a semicustom component, which includes
configurable logic blocks, input-output blocks and
interconnects. It has some important characteristics; highly
integrated, fast computer speed, could be parallel programmed
and online programmed. The proposed PID controller
algorithm is implemented with VHDL using the Altera Corp.
DE0Nano (Cyclone® IV EP4CE22F17C6N FPGA) device.
The components of this board are shown in Fig. 8. This board
introduces a compact-sized FPGA development platform suited
for to a wide range of portable design projects, such as robots
and mobile projects. It features Cyclone FPGA with 22,230
logic elements, 32MB of SDRAM, 2 kB EEPROM and 64 MB
serial configuration memory device. For connecting to real-
world sensors, it includes a National Semiconductor 8-channel,
12 bit ADC device, 13-bit, 3 axis accelerometer device, two
pushbuttons, 8 use LEDs, a set of four dipswitch, three
expansion headers [19].
Fig. 8. DE0 Nano FPGA Education and development board
The components which is used in the study; Cyclone IV
EP4CE22F17C6N FPGA, USB type-mini AB port to connect
the board to computer to power the board and download the
VHDL program to FPGA, 50 MHz clock oscillator which can
use as a source clock, ADC and 26-pin header to take the
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motors position values as a voltage level and transmit these to
FPGA as s digital value, push button for reset the system and
LEDs to see the same values about the program values.
III.IMPLEMENTATION
In FPGA, three basic blocks are executed, which are
Analog Input Interface Block, Digital PWM Block and, Digital
PID Block. In this section, these blocks is introduced. The
FPGA design is generally synchronous, that means that the
design is clock based and each rising edge allows all the D-flip
flops to simultaneously take a new state. But, most of the
designs need one more clock which works in a different
frequency. To solve this problem, there are some techniques
about clock domain crossing (CDC). In this design, a binary
counter is created (33 bits) triggered by 50 MHz main
oscillator clock and suitable divided bits are chosen for ADC,
digital PID and digital PWM blocks.
A. Analog Input Interface
The ADC performs the function of converting a
continuous-valued analog signal into a discrete-valued digital
signal. FPGAs are well suited for serial analog to digital
converters owing to serial interface consuming less
communication lines while the FPGA is fast enough to
accommodate to high speed serial data. The DE0Nano board
contains ADC120S02 analog to digital converter provides up to
8 channels of analog input and converts them into a 12-bit
digital signal [20]. ADC receives analog signals via the eight
analog inputs from IN0 to IN7. When performing a
conversation, the ADC reads the signal on one of these eight
input channels and converts it to a digital output. These eight
pins are part of 2x13 GPIO header. The ADC also has four
wires connected to the FPGA and these wires are used to
control the ADC and allow communication between ADC and
the FPGA. ADC120S02 is a high speed, low power 12 bit
converter. In this study the first four channels of ADC is used
actively. The ADC is connected both the FPGA and the 2x13
GPIO header as shown in Fig 9.
Fig. 9. Signals to and from the ADC
The timing diagram of ADC is shown in Fig. 10;
Fig. 10. The Timing diagram of ADC[20]
B. Digital PWM Block
Pulse width modulation is a simple method of using
rectangular digital waveform to control an analog variable by
changing ON and OFF ratio or the output pulse in discrete time
domain. It is used in a variety of applications ranging from
communications to automatic control. In this application, pulse
width modulation (PWM) block implemented within FPGA
and adjusts on and off period of each terminal of the full H-
bridges to control five DC motors at the robot axes.
The total PWM period T can be stated as in (7) and where
Ton= ON time and Toff = OFF time.
T = Ton + Toff (7)
The output voltage is calculated as in (8), where Vout is the
average output voltage, Vin is the input voltage and D is the
duty cycle.
⎛ Ton ⎞
Vout = ⎜ ⎟Vin , Vout = DVin , (8)
⎜T +T ⎟
⎝ on off ⎠
The simplest digital PWM architecture, counter-based
PWM, and can be easily implemented only by an n-bit counter
and n-bit comparator shown in Fig. 11. The counter counts
each positive transit of reference clock and when the value of
counter is less than the digital settling code K, the output
(A<B) of the comparator remains high level state until the
content of the counter is large then K [21]. Therefore, this
output will generate a pulse width corresponding to duty cycle
and a frequency.
Fig. 11. Basic structure of counter based digital PWM[23]
The modulating signal is 12 bit digital value. The source
(reference) clock signal of FPGA is 50 MHz and the period is
20ns. To represent 212 = 4096 level of modulation signal,
20 × 4096 = 81920 ns period is necessary. This allows a
maximum PWM frequency of about 12.2 KHz. This frequency
is experimented on motors and found to be sufficient. All axes
are driven with 12V DC motors, the PWM signal of all motors
change between 100% - 0% and to apply this PWM value H-
bridges supplied with 12V are used.
C. Digital PID Block
In FPGA, the digital PID control algorithm is implemented
and synthesized using Altera Quartus II, the RTL
implementation of controller is described using VHDL
language. Finally, the generated implementation file is
downloaded to the FPGA development board for testing. The
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four closed loop digital PID algorithm is executed so K d is set to zero. The parameters for each axes is given in
simultaneously in FPGA for control base, shoulder, elbow and Table I.
wrist motors.
In the loop, the first step is that the previous error signal TABLE I. PID PARAMETERS
e[k-1] and the total previous integral signal ui[k-1] is updated.
Axis 1 Axis 2 Axis 3 Axis 4
Then the present error e[k] is obtained to subtract reference
point from the output of the system. The reference and the Kp 40 50 60 130
output of the system are both 12 bits wide and the sign of the Ki 4 5 6 13
result is checked to see if the error is positive or negative. If
the error sign is positive or zero the sign bit is set to ‘0’, Below, the application results for a pick and place
otherwise is set to ‘1’. Then e[k], e[k-1] are multiplied by the experiment are given for each axis of robot. The reference
PID parameters. The sign bits of the multiplicands are found position is calculated by using Matlab and the real time motor
with XOR to get the sign bit of the products. With the multiple position is obtained by using Quanser Q2 data accusation
12 bit two signals, the result is found as 24 bits. After two board.
additions, the output of PID controller is found 26 bits. As a
result, 26 bits value is reduced to 12 bits duty cycle value. All 2.2
reference pos i ti on
of the values in PID control algorithm are binary. In the 2
real ti me motor pos i ti on for axi s 1

algorithm there are no decimal points. The sampling time of

position (volt)
the algorithm is 20ms. The block diagram of the digital PID 1.8

controller in FPGA is shown as below;

1.6

1.4

0 10 20 30 40 50 60 70
time (seconds)

Kp Kd Ki
Fig. 13. Reference and real time motor position for axis1

Kd

1.9 reference position

real time motor position for axis 2
1.8

1.7
position(Volt)

1.6

1.5

1.4

1.3

0 10 20 30 40 50 60 70
time (second)

Fig. 12. Digital PID implementation in FPGA

Fig. 14. Reference and real time motor position for axis 2
There are various methods to determine PID parameters
and in this paper, the proportional ( K p ), integral ( K i ) and
1.7 reference position
derivative ( K d ) gains are obtained from Matlab Sisotool with real time motor position for axis 3

the help of linear system model which obtained in Section II, 1.6

based on step response[22]. The basic criteria to find these

position(Volt)

1.5
parameters, the overshoot for all robot axes are assumed to be
zero. However, theoretical studies show proportional control 1.4
satisfy, but in the real system owing to unmodelled nonlinear
1.3
disturbance and dead-zones requires integral control. In this
method at first K i and K d parameters are set to zero and the 1.2

proportional gain is increased until the step response reaches 1.1

the overshoot boundary. After that, K p and K i have been set 0 10 20 30 40
time(seconds)
50 60 70

to get desired fast control system with minimal steady state

error and the result show that there is no need derivative term Fig. 15. Reference and real time motor position for axis 3

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2.05 reference position
real time motor position for axis 4
2 digital PID controller in Field Programmable Gate Array
position (Volt)
1.95
1.9
1.85
1.8
0 10 20 30 40 50 60
time (second)
Fig. 16. Reference and real time motor position for axis 4
Fig 13, 14, 15 and 16 show the trajectory of each robot axes
against the reference trajectory, respectively. Four axis
controllers are executed simultaneously, with help of the
parallel nature of FPGA as they are seen in the results. The
axes keep tracking the reference trajectories without overshoot
except axis 4; small overshoots and steady-state errors are
caused by undesired noise and mechanical problems.
IV.CONCLUSIONS
In this paper, FPGA-based digital parallel PID controller is
designed and implemented for multi axes control systems.
Altera DE0 Nano board is used to control five axes robotic arm
as a multi axes system. The digital PID block, digital PWM
block and Analog Input Interface block are successfully
designed on an FPGA to control the position of four motor
which is places in joint of robot. VHDL language is used for
coding. The results demonstrate that FPGA can be shown as a
flexible solution for multi axes systems. The digital PID
controller is implemented on FPGA in some study seen in
literature, but this paper shows that how to control a real
model-unknown system with digital PID using FPGA.
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