VENDING MACHINE

Rahul Rithe
Roll No.: 04EC1029
Department of Electronics and Electrical Communication Engineering
Indian Institute of Technology, Kharagpur – 721302, India
Email: rrithe@iitkgp.ac.in

OBJECTIVE:

To design a Vending Machine which accepts money inputs in any sequence and delivers
the product when required amount is been deposited and gives back the change. It is also
possible to withdraw the deposited money in between, if consumer wishes by pressing a
button.

SPECIFICATIONS:

1. Price of the product : Rs. 3/-

2. Possible money inputs : Rs. 2/-, Re. 1/- (in any sequence)
3. Product to be delivered when Rs. 3/- or more (Rs. 4/-) are deposited.
4. In case Rs. 4/- are deposited Re. 1/- has to be returned.
5. Status of the “CANCEL” button to be checked at every stage and deposited
money is to be returned if it is pushed.

STATES DESCRIPTION:

1. Altogether 6 states are needed to represent the machine using ‘Moore Model’.
2. State R0 represents no money deposited, so the both outputs are zero.
3. State R1 represents Re. 1/- has been deposited.
4. State R2 represents Rs. 2/- have been deposited.
5. State R3 represents Rs. 3/- have been deposited, so the product is to be delivered,
i.e. P output becomes 1 and C output is 0.
6. State R4 represents Rs. 4/- have been deposited, so the product is to be delivered,
i.e. P output becomes 1 and C output also becomes 1 in order to return Re. 1/-
7. The state CANCEL represents that the consumer wants to stop the process and get
back his deposited money, so both P & C outputs are 0, and R becomes 1 to
instantiate the return process.
ALGORITHM:
The machine is described by the use of “ASM CHART ” as follows:

START

R0
P=C=0,R=0

I =0 I =1
I =?

J =1
J =?

C =1 C= 0
CANCEL =? CANCEL=0
CANCEL =?
R1
R2
P=C=0,R=0
P=C=0,R=0
I =1 I =0
I =? I =1 I =0
I =?

J =1 J =0
J =?
J=0 J =1
J =?

0 C =1
C =1 0 CANCEL =?
CANCEL =?

CANCEL R3 R4
P=C=0,R=1 P=1,C=0,R=0 P=C=1,R=0
MACHINE DESIGN USING VERILOG:
The hardware implementation of above ASM can be modeled using ‘VERILOG’. The
corresponding Verilog code is shown below:

module MOORE_VEND_MACH(i,j,b,clk,p,c,r);
//i/o declarations
input i,j,b,clk;
output p,c,r;
reg p,c,r;
parameter R0=0,R1=1,R2=2,R3=3,R4=4,RET=5;
reg [2:0] ps,ns;
always @(posedge clk)
case(ps)

R0: begin
ps<=i?(j?R2:R1):R0;
end

R1:begin
if(b)
begin
ps<=RET;
end
else
begin
ps<=i?(j?R3:R2):R1;
end
end

R3:begin
if(b)
begin
ps<=RET;
end
else
begin
ps<=R0;
end
end

R2:begin
if(b)
begin
 ps<=RET;
end
else
begin
ps<=i?(j?R4:R3):R2;
end
end

R4:begin
if(b)
begin
ps<=RET;
end
else
begin
ps<=R0;
end
end
RET:begin
ps<=R0;
end

default
begin
ps<=R0;
end
endcase

always @(ps)
case(ps)

R0: begin
p=0;
c=0;
end

R1:begin
if(b)
begin
 p=0;
c=0;
r=0;
end
else
begin
p=0;
c=0;
r=0;
end
end

R3:begin
if(b)
begin
p=0;
c=0;
r=0;
end
else
begin
p=1;
c=0;
r=0;
end
end

R2:begin
if(b)
begin
p=0;
c=0;
r=0;
end
else
begin
p=0;
c=0;
r=0;
end
end

R4:begin
if(b)
begin
 p=0;
c=0;
r=0;
end
else
begin
p=1;
c=1;
r=0;
end
end

RET:begin
p=0;
c=0;
r=1;
end

default
begin
p=0;
c=0;
r=0;
end
endcase
endmodule

CODE SIMULATION:

The above code is simulated and the outputs are checked by using the following
STIMULUS module.
//// testbench
module stimulus;
reg i,j,b,clk;
wire p,c,r;

//instantiating vendingmachine
MOORE_VEND_MACH VM(i,j,b,clk,p,c,r);

// monitoring
initial
begin
$monitor($time,"i=%b,j=%b,b=%b,.......p=%b,c=%b,r=%b",i,j,b,p,c,r);
end
// stimulus inputs
initial
begin
clk=1'b0;

i=0;j=0;
#5 i=1;j=1;b=0;
#5 i=1;j=0;b=1;
#5 i=1;j=1;b=0;
#5 i=1;j=0;b=0;
#5 i=1;j=0;b=0;
#5 i=1;j=1;b=1;
#5 i=1;j=0;b=0;
#5 i=1;j=0;b=0;
end

always
#1 clk = ~clk;
initial
#60 $finish;

endmodule
RESULTS OBTAINED:
The above code when compiled and run in VERILOG compiler gives following outputs
for the inputs given in the STIMULUS module of the code:

0i=0,j=0,b=x,.......p=x,c=x,r=x
1i=0,j=0,b=x,.......p=0,c=0,r=0
5i=1,j=1,b=0,.......p=0,c=0,r=0
9i=1,j=1,b=0,.......p=1,c=1,r=0
10i=1,j=0,b=1,.......p=1,c=1,r=0
11i=1,j=0,b=1,.......p=0,c=0,r=0
15i=1,j=1,b=0,.......p=0,c=0,r=1
19i=1,j=1,b=0,.......p=0,c=0,r=0
20i=1,j=0,b=0,.......p=0,c=0,r=0
21i=1,j=0,b=0,.......p=1,c=1,r=0
23i=1,j=0,b=0,.......p=0,c=0,r=0
29i=1,j=0,b=0,.......p=1,c=0,r=0
30i=1,j=1,b=1,.......p=1,c=0,r=0
31i=1,j=1,b=1,.......p=0,c=0,r=0
35i=1,j=0,b=0,.......p=0,c=0,r=1
39i=1,j=0,b=0,.......p=0,c=0,r=0
43i=1,j=0,b=0,.......p=1,c=0,r=0
45i=1,j=0,b=0,.......p=0,c=0,r=0
51i=1,j=0,b=0,.......p=1,c=0,r=0
53i=1,j=0,b=0,.......p=0,c=0,r=0
59i=1,j=0,b=0,.......p=1,c=0,r=0
Exiting VeriLogger Pro at simulation time 60000
0 Errors, 0 Warnings
Compile time = 0.01500, Load time = 0.04700, Execution time = 0.03100
Normal exit
INPUT/OUTPUT WAVEFORMS:
SIMULATION & FPGA IMPLEMENTATION USING XILINX :

ModelSim is used for simulation of the code and Xilinx is used for the implementation of
the code in FPGA.
Here are some screenshots at various stages of the implementation procedure:

Implementation Report:
Synthesized Circuits:
(i) RTL Schematic –
One of the blocks in RTL schematic:
(ii) Technology Schematic –
One of the blocks in Technology Schematic:
Karnaugh Map for the above block:
Test bench waveforms for the simulation:
Layout & I/O port assignment:
Programming the FPGA: