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UART Interface User Guide AML8726-MX Version 0.

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Application Notes

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AML 8726-MX

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UART Interface User Guide
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AMLOGIC, Inc.
3930 Freedom Circle
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Santa Clara, CA 95054


U.S.A.
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www.amlogic.com
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AMLOGIC reserves the right to change any information described herein at any time without notice.
AMLOGIC assumes no responsibility or liability from use of such information.

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UART Interface User Guide AML8726-MX Version 0.2

Table of Content
1. GENERAL DESCRIPTION ............................................................................................................................................. 4
2. OVERVIEW ....................................................................................................................................................................... 4
3. FEATURES ........................................................................................................................................................................ 4
4. UART SIGNAL AND PIN MAPPING ............................................................................................................................ 5
4.1. SIGNAL ......................................................................................................................................................................... 5
4.2. PIN MAPPING ................................................................................................................................................................ 5

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5. INTERRUPT ...................................................................................................................................................................... 6
6. POWER MANAGEMENT ............................................................................................................................................... 7

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7. RESET ................................................................................................................................................................................ 7

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8. BAUD RATE ...................................................................................................................................................................... 8
8.1. INPUT CLOCK................................................................................................................................................................ 8

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8.2. BAUD RATE GENERATION ............................................................................................................................................ 8

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9. REGISTER DESCRIPTIONS .......................................................................................................................................... 9
9.1. UART_A...................................................................................................................................................................... 9
9.2. UART_B .................................................................................................................................................................... 14

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9.3. UART_C .................................................................................................................................................................... 19
9.4. UART_AO ................................................................................................................................................................. 24
10. ADDRESS MAPPING ................................................................................................................................................. 29
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11. ANDROID™/LINUX KERNEL ................................................................................................................................. 30
11.1. OPERATION MACRO DEFINITION ............................................................................................................................ 30
11.2. REGISTER MACRO DEFINITION ............................................................................................................................... 30
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5/22/2012 2/30 AMLOGIC Proprietary


UART Interface User Guide AML8726-MX Version 0.2

Revision History
Revision Revised Date By Changes
Number
0.1 Feb. 15, 2012 Kevin Zhu Initial release draft
0.2 May. 22,2012 Kevin Zhu UART0~2 renamed to UART_A, UART_B and UART_C

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5/22/2012 3/30 AMLOGIC Proprietary


UART Interface User Guide AML8726-MX Version 0.2

1. General Description
Amlogic AML8726-MX is a highly integrated multimedia application processor SoC for Multimedia Internet Device
(MID), tablet and Set Top Box (STB). It integrates a powerful CPU, a 2D/3D graphics subsystem and a
state-of-the-art video decoding engine together with all major peripherals.

This document is a user guide of universal asynchronous receiver/transmitter (UART) serial ports integrated in
AML8726-MX.

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The guide provides:
 An overview of UART interface

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 The feature of UART
 The UART interface pin selection

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 The baud rate generation
 The register definition that control and operate UART interface
 AML8726-MX UART in Android/Linux Amlogic porting

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2. Overview
Each AML8726-MX has four fully functional UARTs which use the same programming model. They are named as

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UART_A, UART_B, UART_C and UART_AO. The one with ‘AO’ in the naming are located at the Always-On (AO)
power domain, which cannot be powered off unless AML8726-MX is disconnected from power supply.

The four UARTs are controlled separately. Each UART has a build-in standalone register set for controlling and
to
data exchange.

The UARTs in AML8726-MX can only operate in FIFO mode. UART_A has a 128-byte RX/TX FIFO and
UART_B/UART_C/UART_AO has a 64-byte FIFO. If non-FIFO mode is required, the registers of UART should be
fine tuned and a polling mechanism should be used to fulfill.
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Each UART has programmable interrupt generation circuit which will reduce the loading of processor and to
improve communication performance.
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A baud-rate generator is also contained in each UART to provide flexible division of input clock by 1 to (2 -1) or 1
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to (2 -1) according to the setting in the internal register.
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3. Features
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The UARTs share the following features:


 Each UART independent control register set
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 Independently controlled transmit and receive interrupts with FIFO threshold


 Programmable serial interface:
 5-, 6-, 7- or 8-bit characters
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 Even, odd or no parity detection


 1 stop bit generation
 Programmable baud rate
 64-byte transmit and receive FIFO (UART_B/UART_C/UART_AO)
 128-byte transmit and receive FIFO (UART_A)
 Automatic frame error detection
 Programmable RX, TX, RTS, CTS signal polarity

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UART Interface User Guide AML8726-MX Version 0.2

4. UART Signal and Pin Mapping


4.1. Signal
Each AML8726-MX UART function module has 4 external signals which can be connected to a series of GPIO pins
via pin multiplex mapping circuit. The pins transmit digital CMOS-level signals only.

The signals are described in the table below:

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Table 1. UART Signal Descriptions
Name Type Description

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RX Input Serial data input to the receive shift register and Receive FIFO.
TX Output Serial data output to external data set.
CTS Input Clear to Send.

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When asserted, it indicates that the receiver is ready to exchange data.
RTS Output Request to Send.

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When asserted, it notifies the receiver that the sender is ready to exchange data.

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4.2. Pin Mapping
In AML8726-MX, only UART RX and TX signal are available. If CTS and RTS signal are required, please contact
with Amlogic Sales.

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AML8726-MX has 11 GPIO banks. UART_A, UART_B and UART_C are located in Bank X and UART_AO is in the
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dedicated Bank AO. RX and TX signals of the UART function blocks can be multiplexed to the corresponding bank
in pair.

The relationship between pins and registers of each UART signal and GPIO bank is shown in the table below:
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Table 2. UART Signal Pin out Mapping

UART Module UART Signal Bank X Bank AO


UART_RX_A GPIOX_14
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UART_TX_A GPIOX_13
UART_A
UART_CTS_A GPIOX_15
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UART_RTS_A GPIOX_16
UART_RX_B GPIOX_18
UART_TX_B GPIOX_17
UART_B
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UART_CTS_B GPIOX_19
UART_RTS_B GPIOX_20
UART_RX_C GPIOX_22
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UART_TX_C GPIOX_21
UART_C
UART_CTS_C GPIOX_23
UART_RTS_C GPIOX_24
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UART_RX_AO GPIOAO_1
UART_TX_AO GPIOAO_0
UART_AO
UART_CTS_AO GPIOAO_2
UART_RTS_AO GPIOAO_3
About GPIO function settings, please refer to AML8726-MX GPIO User Guide for detailed description.

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UART Interface User Guide AML8726-MX Version 0.2

5. Interrupt
The UART interrupts are controlled in two levels: CPU and Function.

In CPU level, the UART interrupts can be controlled and programmed by using the registers below:

Table 3. Interrupt Control Register UART CPU Level


UART Module Offset Bit R/W
0x2690 bit 26 R UART_A interrupt flag. When interrupt happens, it will be

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set to 1.
0x2691 bit 26 R/W Write 1 to this register bit to clean UART_A interrupt flag.

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UART_A 0x2692 bit 26 R/W Interrupt mask. Set to 1 to mask UART_A interrupt (disable
UART_A interrupt).
0x2693 bit 26 R/W Fast interrupt enable. Set to 1 to enable UART_A interrupt

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multiplexing to CPU FAST interrupt
0x2698 bit 11 R UART_B interrupt flag. When interrupt happens, it will be

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set to 1.
0x2699 bit 11 R/W Write 1 to this register bit to clean UART_B interrupt flag.

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UART_B 0x269A bit 11 R/W Interrupt mask. Set to 1 to mask UART_B interrupt (disable
UART_A interrupt).
0x269B bit 11 R/W Fast interrupt enable. Set to 1 to enable UART_B interrupt

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multiplexing to CPU FAST interrupt
0x2698 bit 29 R UART_C interrupt flag. When interrupt happens, it will be
set to 1.
0x2699 bit 29 R/W Write 1 to this register bit to clean UART_C interrupt flag.
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UART_C 0x269A bit 29 R/W Interrupt mask. Set to 1 to mask UART_C interrupt (disable
UART_AO interrupt).
0x269B bit 29 R/W Fast interrupt enable. Set to 1 to enable UART_C interrupt
multiplexing to CPU FAST interrupt
0x2698 bit 26 R UART_AO interrupt flag. When interrupt happens, it will be
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set to 1.
0x2699 bit 26 R/W Write 1 to this register bit to clean UART_AO interrupt flag.
UART_AO 0x269A bit 26 R/W Interrupt mask. Set to 1 to mask UART_AO interrupt
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(disable UART_AO interrupt).


0x269B bit 26 R/W Fast interrupt enable. Set to 1 to enable UART_AO interrupt
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multiplexing to CPU FAST interrupt

In Function Level, the block registers need to be set to enable UART interrupt.
 UART_A: UART_A_CONTROL[27] and [28] must be set to 1.
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 UART_B: UART_B_CONTROL[27] and [28] must be set to 1.


 UART_C: UART_C_CONTROL[27] and [28] must be set to 1.
 UART_AO: AO_UART_CONTROL[27] and [28] must be set to 1.
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For more details and other register setup, please refer to the Register Descriptions section.
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UART Interface User Guide AML8726-MX Version 0.2

6. Power Management
The UARTs in AML8726-MX can be shut down to save power consumption by using the register bits described
below:
Need verify
 UART_A: in EE domain;
 UART_B: in EE domain;
 UART_C: in EE domain;
 UART_AO: in AO domain;

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Setting these bits to 0 will disable the UARTs function blocks and 1 will enable them. After system power-on or
reset, UART modules are enabled on default.

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7. Reset

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For the UART module in the AO power domain, it is possible to reset it by programming the register bit 0x0010[17]
which is also in AO domain. Setting this bit to 1 will reset the I2C AO function blocks.

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Note: The receivers and transmitters of UARTs are disabled after system power-on or reset. Therefore software
must program the registers to enable them, e.g., bit 12 and 13 in the corresponding control register should be set

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to 1.
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UART Interface User Guide AML8726-MX Version 0.2

8. Baud Rate
A build-in baud rate generator is implemented in AML8726-MX for each UART interface. The generator contains
an input clock, a divider circuits and control registers.

8.1. Input Clock


The input clock of the generator, named as UART_Clock, is configurable. The exact value of UART_Clock is based

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on AML8726-MX system software implementation.

In Amlogic Android/Linux porting for AML8726-MX, the value of UART_Clock can be obtained by using the

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following process in software.

1. Include clkdev.h at [linux_kernel_root]/arch/arm/include/asm/.

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2. Include clock.h at [linux_kernel_root]/arch/arm/mach-meson/include/mach/.
3. Define a variable type struct clk.

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4. Define an unsigned int type variable uart_clock_rate.
5. Use API clk_get_sys(“clk81”, NULL) to get clock structure.

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6. Use API clk_get_rate() to get the value of UART_Clock.

The sample code is illustrated as below:

#include <linux/clk.h>
#include <asm/clkdev.h>
#include <mach/clock.h> E
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unsigned int uart_clock_rate;
struct clk *uart_clock

uart_clock = clk_get_sys(“clk81”, NULL);


uart_clock_rate = clk_get_rate(uart_clock);
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8.2. Baud Rate Generation


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After obtaining the uart_clock_rate, software can use the equation as shown below to generate correct baud rate.


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UART_A: or or
 UART_B: or or

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UART_C: or or
 UART_AO: or or
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UART Interface User Guide AML8726-MX Version 0.2

9. Register Descriptions
These are 6 registers are defined and implemented in AML8726-MX for each UART. They are all 32-bit.

9.1. UART_A
Write Buffer Register (UART_A_WFIFO)

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UART_A_WFIFO is the data entry of UART_A transmit FIFO. Writing to the register puts a byte data into the top of
transmit FIFO. The data at the front of the FIFO transmits automatically until transmit FIFO empty.

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Table 4. UART_A_WFIFO register definition
Name UART_A_WFIFO Offset 0x2130 Width 32-bit

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Bit R/W Name Default Description
31:8 R - 0 Reserved

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7:0 W FIFO_WDATA - Write UART Transmit FIFO. The Write FIFO holds 64 bytes

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Read Buffer Register (UART_A_RFIFO)
UART_A_RFIFO is the data entry of UART Read FIFO. It latches the value of data byte at the front of UART Read
FIFO.

Name UART_A_RFIFO
Bit R/W Name
Offset 0x2131
Default Description
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Table 5. UART_A_RFIFO register definition
Width 32-bit
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31:8 R - 0 Reserved
7:0 R FIFO_RDATA 0x00 Read a byte from UART FIFO.
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UART Interface User Guide AML8726-MX Version 0.2

UART_A Mode Register (UART_A_CONTROL)


UART_A_CONTROL is a control register.

Table 6. UART_A_CONTROL register definition


Name UART_A_CONTROL Offset 0x2132 Width 32-bit
Bit R/W Name Default Description
31 R/W RTS_INV 0 Invert RTS signal. 0: RTS active LOW. 1: RTS active HIGH
30 R/W ERR_MASK_EN 0 Error Mask enable. 0: disable error mask. 1: enable error mask.
29 R/W CTS_INV 0 Invert CTS signal. 0: CTS active LOW 1: CTS active HIGH.

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28 R/W UART_TX_INT_EN 0 Transmit byte interrupt enable. When enabled, an interrupt will be
generated whenever a byte is read from Transmit FIFO.
0: disable transmit byte interrupt

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1: enable transmit byte interrupt
27 R/W UART_RX_INT_EN 0 Receive byte interrupt enable. When enabled, an interrupt will be

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generated whenever a byte is written to Read FIFO.
0: disable receive byte interrupt
1: enable receive byte interrupt

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26 R/W UART_TX_INV 0 Invert TX signal. 0: TX active HIGH. 1: TX active LOW
25 R/W UART_RX_INV 0 Invert RX signal. 0: RX active HIGH. 1: RX active LOW

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24 R/W UART_CLR_ERR 0 Clear error. Writing 1 to this register bit clears error.
Note: This bit does not clear to 0 automatically. Please set the bit
to 0 after clearing error manually.

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23 R/W UART_RX_RST 0 Reset receive state machine. Writing 1 to this register bit resets
receive state machine.
22 R/W UART_TX_RST 0 Reset transmit state machine. Write 1 to this register bit reset
transmit state machine.
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21:20 R/W UART_DATA_LEN 00 Character length of data.
00: 8-bit
01: 7-bit
10: 6-bit
11: 5-bit
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19 R/W PARITY_EN 1 Parity enable bit. 0: disable parity bit. 1: enable parity bit
18 R/W PARITY_TYPE 0 Parity type bit. 0: even parity. 1: odd parity
17:16 R/W STOP_BIT_LEN 0 Stop bit length.
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00: 1 stop bit


01: 2 stop bit
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10-11: reserved.
15 R/W TWO_WIRE_EN 0 Two-wire mode enables. 0: four-wire mode. 1: Two-wire mode
14 - - 0 Reserved
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13 R/W UART_RX_EN 0 Receive enable. 0: disable receive function. 1: enable receive


function
12 R/W UART_TX_EN 0 Transmit enable. 0: disable transmit function. 1: enable
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transmit function
11:0 R/W BAUD_RATE 0x120 Baud rate setup. Please refer to Baud Rate Generation Section
for detail.
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UART Interface User Guide AML8726-MX Version 0.2

UART_A Status Register (UART_A_STATUS)


UART_A_STATUS is a read-only register to indicate the status of UART interface.

Table 7. UART_A_STATUS register definition


Name UART_A_STATUS Offset 0x2133 Width 32-bit
Bit R/W Name Default Description
31:27 - - 0x00 Reserved
26 R UART_RECV_BUSY 0 Receive state machine busy indicator. Being set to 1
indicates receive state machine is busy

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25 R UART_XMIT_BUSY 0 Transmit state machine busy indicator. Being set to 1
indicates transmit state machine is busy
24 R RECV_FIFO_OVERFLOW 0 Receive FIFO overflow indicator. Being set to 1 indicates

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receive FIFO overflows
23 R CTS_LEVEL 0 CTS signal level.

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22 R TX_FIFO_EMPTY 0 Transmit FIFO Empty indicator. Being set to 1 indicates
Transmit FIFO is empty

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21 R TX_FIFO_FULL 0 Transmit FIFO Full indicator. Being set to1 indicates
Transmit FIFO is full.
20 R RX_FIFO_EMPTY 0 Receive FIFO Empty indicator. Being set to 1 indicates

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Receive FIFO is empty
19 R RX_FIFO_FULL 0 Receive FIFO Full indicator. Being set to 1 indicates
Receive FIFO is full.

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18 R TX_FIFO_WERR 0 Transmit FIFO writing error indicator. The bit is set to 1 if
writing data to Transmit FIFO when Transmit FIFO is full.
Note: Please use register UART_A_CONTROL bit 24 to
clear this bit. Refer to UART_A_CONTROL register
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definition.
17 R FRAME_ERR 0 Frame Error indicator. The bit is set to 1 if frame error
detected.
Note: Please use register UART_A_CONTROL bit 24 to
clear this bit. Refer to UART_A_CONTROL register
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definition.
16 R PARITY_ERR 0 Parity Error indicator. The bit is set to 1 if parity error
detected.
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Note: Please use register UART_CONTROL bit 24 to clear


this bit. Refer to UART_A_CONTROL register definition.
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15 - - 0 Reserved
14:8 R TX_FIFO_DCNT 0 Transmit FIFO data count. The value is the number of
bytes in the Transmit FIFO.
7 R - 0 Reserved
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6:0 R RX_FIFO_DCNT 0 Receive FIFO data count. The value is the number of
bytes in the Receive FIFO.
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UART Interface User Guide AML8726-MX Version 0.2

UART_A Interrupt Control Register (UART_A_MISC)


UART_A_MISC is the register to control UART related interrupt.

Table 8. UART_A_MISC register definition


Name UART_A_MISC Offset 0x2134 Width 32-bit
Bit R/W Name Default Description
31 - - 0 Reserved
30 R/W USE old Rx Baud 0 he Rx baud rate generator was re-designed to compute a
baud rate correctly. If you want to use the old (stupid) logic,

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you can set this bit to 1.
29 R/W ASYNC_FIFO_PURGE 0 Set to 1 after all UART bytes have been received in order to
purge the data into the async FIFO

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28 R/W ASYNC_FIFO_EN 0 Automatically send to async FIFO module enable
1: enable automatic sending

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0:disable automatic sending
27 R/W CTS_FIL_TB_SEL 0 CTS input filter time base selection.
A digital signal filter can be used to filter the UART CTS signal

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input.
The filter has two parameters, the time base and the number

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of time base.
0: The time base is 111nS.
1: The time base is 1uS.

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26-24 R/W CTS_FIL_SEL 0 CTS input filter times
000: No filter.

111: Maximum filter time. The time is 7x 111= 777nS
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(CTS_FIL_TB_SEL = 0) or 7x 1=7uS (CTS_FIL_TB_SEL = 1)
23-20 R/W BAUD_RATE_EXT 0 Extend the baud rate divider to 16-bits together with
UART_A_STATUS[11:0]
Baud_Rate = {Reg4[23:20],Reg2[11:0]}
19 R/W RX_FIL_TB_SEL 0 RX input filter time base selection.
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A digital signal filter can be used to filter the UART RX signal


input.
The filter has two parameters, the time base and the times of
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time base.
0: The time base is 111nS.
1: The time base is 1uS.
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18:16 R/W RX_FIL_SEL 0 RX input filter times


000: No filter.

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111: Maximum filter time. The time is 7x 111= 777nS


(RX_FIL_TB_SEL = 0) or 7x 1=7uS (RX_FIL_TB_SEL = 1)
15:8 R/W XMIT_IRQ_CNT 32 Transmit FIFO threshold.
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UART generates an interrupt when the number of bytes in


Transmit FIFO is below the value of these bits.
7:0 R/W RECV_IRQ_CNT 15 Receive FIFO threshold.
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UART generates an interrupt when the number bytes in


Receive FIFO is large than the value of these bits.

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UART Interface User Guide AML8726-MX Version 0.2

UART_A_REG5
Table 9. UART_A_REG5 register definition
Name UART_A_REG5 Offset 0x2135 Width 32-bit
Bit R/W Name Default Description
31-24 R/W - 0 unused
23 R/W USE New Baud rate. 0 Over the years, the baud rate has been extended by
concatenating bits from different registers. To take
advantage of the full 23-bit baud rate generate (extended to
23 bits to accommodate very low baud rates), you must set

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this bit. If this bit is set, then the baud rate is configured
using bits [22:0] below
22:0 R/W NEW_BAUD_RATE: 0 If bit[23] = 1 above, then the baud rate for the UART is

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computed using these bits. This was added in MX to
accommodate lower baud rates.

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UART Interface User Guide AML8726-MX Version 0.2

9.2. UART_B
Write Buffer Register (UART_B_WFIFO)
UART_B_WFIFO is the data entry of UART_B transmit FIFO. Writing to the register puts a byte data into the top of
transmit FIFO. The data at the front of the FIFO transmits automatically until transmit FIFO empty.

Table 10. UART_B_WFIFO register definition


Name UART_B_WFIFO Offset 0x2137 Width 32-bit
Bit R/W Name Default Description

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31:8 R - 0 Reserved
7:0 W FIFO_WDATA - Write UART Transmit FIFO.

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Read Buffer Register (UART_B_RFIFO)
UART_B_RFIFO is the data entry of UART Read FIFO. It latches the value of data byte at the front of UART Read

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FIFO.

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Table 9. UART_B_RFIFO register definition
Name UART_B_RFIFO Offset 0x2138 Width 32-bit

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Bit R/W Name Default Description
31:8 R - 0 Reserved
7:0 R FIFO_RDATA 0x00 Read a byte from UART FIFO.

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UART Interface User Guide AML8726-MX Version 0.2

UART_B Mode Register (UART_B_CONTROL)


UART_B_CONTROL is a control register.

Table 10. UART_B_CONTROL register definition


Name UART_B_CONTROL Offset 0x2139 Width 32-bit
Bit R/W Name Default Description
31 R/W RTS_INV 0 Invert RTS signal. 0: RTS active LOW. 1: RTS active HIGH
30 R/W ERR_MASK_EN 0 Error Mask enable. 0: disable error mask. 1: enable error mask.
29 R/W CTS_INV 0 Invert CTS signal. 0: CTS active LOW 1: CTS active HIGH.

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28 R/W UART_TX_INT_EN 0 Transmit byte interrupt enable. When enabled, an interrupt will be
generated whenever a byte is read from Transmit FIFO.
0: disable transmit byte interrupt

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1: enable transmit byte interrupt
27 R/W UART_RX_INT_EN 0 Receive byte interrupt enable. When enabled, an interrupt will be

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generated whenever a byte is written to Read FIFO.
0: disable receive byte interrupt
1: enable receive byte interrupt

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26 R/W UART_TX_INV 0 Invert TX signal. 0: TX active HIGH. 1: TX active LOW
25 R/W UART_RX_INV 0 Invert RX signal. 0: RX active HIGH. 1: RX active LOW

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24 R/W UART_CLR_ERR 0 Clear error. Writing 1 to this register bit clears error.
Note: This bit does not clear to 0 automatically. Please set the bit
to 0 after clearing error manually.

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23 R/W UART_RX_RST 0 Reset receive state machine. Writing 1 to this register bit resets
receive state machine.
22 R/W UART_TX_RST 0 Reset transmit state machine. Write 1 to this register bit reset
transmit state machine.
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21:20 R/W UART_DATA_LEN 00 Character length of data.
00: 8-bit
01: 7-bit
10: 6-bit
11: 5-bit
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19 R/W PARITY_EN 1 Parity enable bit. 0: disable parity bit. 1: enable parity bit
18 R/W PARITY_TYPE 0 Parity type bit. 0: even parity. 1: odd parity
17:16 R/W STOP_BIT_LEN 0 Stop bit length.
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00: 1 stop bit


01: 2 stop bit
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10-11: reserved.
15 R/W TWO_WIRE_EN 0 Two-wire mode enables. 0: four-wire mode. 1: Two-wire mode
14 - - 0 Reserved
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13 R/W UART_RX_EN 0 Receive enable. 0: disable receive function. 1: enable receive


function
12 R/W UART_TX_EN 0 Transmit enable. 0: disable transmit function. 1: enable
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transmit function
11:0 R/W BAUD_RATE 0x120 Baud rate setup. Please refer to Baud Rate Generation Section
for detail.
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UART Interface User Guide AML8726-MX Version 0.2

UART_B Status Register (UART_STATUS)


UART_B_STATUS is a read-only register to indicate the status of UART interface.

Table 13. UART_B_STATUS register definition


Name UART_B_STATUS Offset 0x213A Width 32-bit
Bit R/W Name Default Description
31:27 - - 0x00 Reserved
26 R UART_RECV_BUSY 0 Receive state machine busy indicator. Being set to 1
indicates receive state machine is busy

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25 R UART_XMIT_BUSY 0 Transmit state machine busy indicator. Being set to 1
indicates transmit state machine is busy
24 R RECV_FIFO_OVERFLOW 0 Receive FIFO overflow indicator. Being set to 1 indicates

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receive FIFO overflows
23 R CTS_LEVEL 0 CTS signal level.

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22 R TX_FIFO_EMPTY 0 Transmit FIFO Empty indicator. Being set to 1 indicates
Transmit FIFO is empty

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21 R TX_FIFO_FULL 0 Transmit FIFO Full indicator. Being set to1 indicates
Transmit FIFO is full.
20 R RX_FIFO_EMPTY 0 Receive FIFO Empty indicator. Being set to 1 indicates

m
Receive FIFO is empty
19 R RX_FIFO_FULL 0 Receive FIFO Full indicator. Being set to 1 indicates
Receive FIFO is full.

E
18 R TX_FIFO_WERR 0 Transmit FIFO writing error indicator. The bit is set to 1 if
writing data to Transmit FIFO when Transmit FIFO is full.
Note: Please use register UART_B_CONTROL bit 24 to
clear this bit. Refer to UART_B_CONTROL register
to
definition.
17 R FRAME_ERR 0 Frame Error indicator. The bit is set to 1if frame error
detected.
Note: Please use register UART_B_CONTROL bit 24 to
clear this bit. Refer to UART_B_CONTROL register
te

definition.
16 R PARITY_ERR 0 Parity Error indicator. The bit is set to 1 if parity error
detected.
u

Note: Please use register UART_CONTROL bit 24 to clear


this bit. Refer to UART_B_CONTROL register definition.
ib

15 - - 0 Reserved
14:8 R TX_FIFO_DCNT 0 Transmit FIFO data count. The value is the number of
bytes in the Transmit FIFO.
7 R - 0 Reserved
tr

6:0 R RX_FIFO_DCNT 0 Receive FIFO data count. The value is the number of
bytes in the Receive FIFO.
is
D

5/22/2012 16/30 AMLOGIC Proprietary


UART Interface User Guide AML8726-MX Version 0.2

UART_B Interrupt Control Register (UART_B_MISC)


UART_B_MISC is the register to control UART related interrupt.

Table 11. UART_B_MISC register definition


Name UART_B_MISC Offset 0x213B Width 32-bit
Bit R/W Name Default Description
31 - - 0 Reserved
30 R/W USE old Rx Baud 0 he Rx baud rate generator was re-designed to compute a
baud rate correctly. If you want to use the old (stupid) logic,

r!
you can set this bit to 1.
29 R/W ASYNC_FIFO_PURGE 0 Set to 1 after all UART bytes have been received in order to
purge the data into the async FIFO

o
28 R/W ASYNC_FIFO_EN 0 Automatically send to async FIFO module enable
1: enable automatic sending

o
0:disable automatic sending
27 R/W CTS_FIL_TB_SEL 0 CTS input filter time base selection.
A digital signal filter can be used to filter the UART CTS signal

d
input.
The filter has two parameters, the time base and the number

m
of time base.
0: The time base is 111nS.
1: The time base is 1uS.

E
26-24 R/W CTS_FIL_SEL 0 CTS input filter times
000: No filter.

111: Maximum filter time. The time is 7x 111= 777nS
to
(CTS_FIL_TB_SEL = 0) or 7x 1=7uS (CTS_FIL_TB_SEL = 1)
23-20 R/W BAUD_RATE_EXT 0 Extend the baud rate divider to 16-bits together with
UART_B_STATUS[11:0]
Baud_Rate = [BAUD_RATE_EXT: BAUD_RATE]
19 R/W RX_FIL_TB_SEL 0 RX input filter time base selection.
te

A digital signal filter can be used to filter the UART RX signal


input.
The filter has two parameters, the time base and the times of
u

time base.
0: The time base is 111nS.
1: The time base is 1uS.
ib

18:16 R/W RX_FIL_SEL 0 RX input filter times


000: No filter.

tr

111: Maximum filter time. The time is 7x 111= 777nS


(RX_FIL_TB_SEL = 0) or 7x 1=7uS (RX_FIL_TB_SEL = 1)
15:8 R/W XMIT_IRQ_CNT 32 Transmit FIFO threshold.
is

UART generates an interrupt when the number of bytes in


Transmit FIFO is below the value of these bits.
7:0 R/W RECV_IRQ_CNT 15 Receive FIFO threshold.
D

UART generates an interrupt when the number bytes in


Receive FIFO is large than the value of these bits.

5/22/2012 17/30 AMLOGIC Proprietary


UART Interface User Guide AML8726-MX Version 0.2

UART_B_REG5
Table 15. UART_B_REG5 register definition
Name UART_B_REG5 Offset 0x213c Width 32-bit
Bit R/W Name Default Description
31-24 R/W - 0 unused
23 R/W USE New Baud rate. 0 Over the years, the baud rate has been extended by
concatenating bits from different registers. To take
advantage of the full 23-bit baud rate generate (extended to
23 bits to accommodate very low baud rates), you must set

r!
this bit. If this bit is set, then the baud rate is configured
using bits [22:0] below
22:0 R/W NEW_BAUD_RATE: 0 If bit[23] = 1 above, then the baud rate for the UART is

o
computed using these bits. This was added in MX to
accommodate lower baud rates.

o
d
m
E
to
te
u
ib
tr
is
D

5/22/2012 18/30 AMLOGIC Proprietary


UART Interface User Guide AML8726-MX Version 0.2

9.3. UART_C
Write Buffer Register (UART_C_WFIFO)
UART_C_WFIFO is the data entry of UART transmit FIFO. Writing to the register puts a byte data into the top of
transmit FIFO. The data at the front of the FIFO transmits automatically until transmit FIFO empty.

Table 12. UART_C_WFIFO register definition


Name UART_C_WFIFO Offset 0x21C0 Width 32-bit
Bit R/W Name Default Description

r!
31:8 R - 0 Reserved
7:0 W FIFO_WDATA - Write UART Transmit FIFO.

o
Read Buffer Register (UART_C_RFIFO)
UART_C_RFIFO is the data entry of UART Read FIFO. It latches the value of data byte at the front of UART Read

o
FIFO.

d
Table 13. UART_C_RFIFO register definition
Name UART_C_RFIFO Offset 0x21C1 Width 32-bit

m
Bit R/W Name Default Description
31:8 R - 0 Reserved
7:0 R FIFO_RDATA 0x00 Read a byte from UART FIFO.

E
to
te
u
ib
tr
is
D

5/22/2012 19/30 AMLOGIC Proprietary


UART Interface User Guide AML8726-MX Version 0.2

UART_C Mode Register (UART_C_CONTROL)


UART_C_CONTROL is a control register.

Table 14. UART_C_CONTROL register definition


Name UART_C_CONTROL Offset 0x21C2 Width 32-bit
Bit R/W Name Default Description
31 R/W RTS_INV 0 Invert RTS signal. 0: RTS active LOW. 1: RTS active HIGH
30 R/W ERR_MASK_EN 0 Error Mask enable. 0: disable error mask. 1: enable error mask.
29 R/W CTS_INV 0 Invert CTS signal. 0: CTS active LOW 1: CTS active HIGH.

r!
28 R/W UART_TX_INT_EN 0 Transmit byte interrupt enable. When enabled, an interrupt will be
generated whenever a byte is read from Transmit FIFO.
0: disable transmit byte interrupt

o
1: enable transmit byte interrupt
27 R/W UART_RX_INT_EN 0 Receive byte interrupt enable. When enabled, an interrupt will be

o
generated whenever a byte is written to Read FIFO.
0: disable receive byte interrupt
1: enable receive byte interrupt

d
26 R/W UART_TX_INV 0 Invert TX signal. 0: TX active HIGH. 1: TX active LOW
25 R/W UART_RX_INV 0 Invert RX signal. 0: RX active HIGH. 1: RX active LOW

m
24 R/W UART_CLR_ERR 0 Clear error. Writing 1 to this register bit clears error.
Note: This bit does not clear to 0 automatically. Please set the bit
to 0 after clearing error manually.

E
23 R/W UART_RX_RST 0 Reset receive state machine. Writing 1 to this register bit resets
receive state machine.
22 R/W UART_TX_RST 0 Reset transmit state machine. Write 1 to this register bit reset
transmit state machine.
to
21:20 R/W UART_DATA_LEN 00 Character length of data.
00: 8-bit
01: 7-bit
10: 6-bit
11: 5-bit
te

19 R/W PARITY_EN 1 Parity enable bit. 0: disable parity bit. 1: enable parity bit
18 R/W PARITY_TYPE 0 Parity type bit. 0: even parity. 1: odd parity
17:16 R/W STOP_BIT_LEN 0 Stop bit length.
u

00: 1 stop bit


01: 2 stop bit
ib

10-11: reserved.
15 R/W TWO_WIRE_EN 0 Two-wire mode enables. 0: four-wire mode. 1: Two-wire mode
14 - - 0 Reserved
tr

13 R/W UART_RX_EN 0 Receive enable. 0: disable receive function. 1: enable receive


function
12 R/W UART_TX_EN 0 Transmit enable. 0: disable transmit function. 1: enable
is

transmit function
11:0 R/W BAUD_RATE 0x120 Baud rate setup. Please refer to Baud Rate Generation Section
for detail.
D

5/22/2012 20/30 AMLOGIC Proprietary


UART Interface User Guide AML8726-MX Version 0.2

UART_C Status Register (UART_STATUS)


UART_C_STATUS is a read-only register to indicate the status of UART interface.

Table 15. UART_C_STATUS register definition


Name UART_C_STATUS Offset 0x21C3 Width 32-bit
Bit R/W Name Default Description
31:27 - - 0x00 Reserved
26 R UART_RECV_BUSY 0 Receive state machine busy indicator. Being set to 1
indicates receive state machine is busy

r!
25 R UART_XMIT_BUSY 0 Transmit state machine busy indicator. Being set to 1
indicates transmit state machine is busy
24 R RECV_FIFO_OVERFLOW 0 Receive FIFO overflow indicator. Being set to 1 indicates

o
receive FIFO overflows
23 R CTS_LEVEL 0 CTS signal level.

o
22 R TX_FIFO_EMPTY 0 Transmit FIFO Empty indicator. Being set to 1 indicates
Transmit FIFO is empty

d
21 R TX_FIFO_FULL 0 Transmit FIFO Full indicator. Being set to1 indicates
Transmit FIFO is full.
20 R RX_FIFO_EMPTY 0 Receive FIFO Empty indicator. Being set to 1 indicates

m
Receive FIFO is empty
19 R RX_FIFO_FULL 0 Receive FIFO Full indicator. Being set to 1 indicates
Receive FIFO is full.

E
18 R TX_FIFO_WERR 0 Transmit FIFO writing error indicator. The bit is set to 1 if
writing data to Transmit FIFO when Transmit FIFO is full.
Note: Please use register UART_C_CONTROL bit 24 to
clear this bit. Refer to UART_C_CONTROL register
to
definition.
17 R FRAME_ERR 0 Frame Error indicator. The bit is set to 1if frame error
detected.
Note: Please use register UART_C_CONTROL bit 24 to
clear this bit. Refer to UART_C_CONTROL register
te

definition.
16 R PARITY_ERR 0 Parity Error indicator. The bit is set to 1 if parity error
detected.
u

Note: Please use register UART_CONTROL bit 24 to clear


this bit. Refer to UART_C_CONTROL register definition.
ib

15 - - 0 Reserved
14:8 R TX_FIFO_DCNT 0 Transmit FIFO data count. The value is the number of
bytes in the Transmit FIFO.
7 R - 0 Reserved
tr

6:0 R RX_FIFO_DCNT 0 Receive FIFO data count. The value is the number of
bytes in the Receive FIFO.
is
D

5/22/2012 21/30 AMLOGIC Proprietary


UART Interface User Guide AML8726-MX Version 0.2

UART_C Interrupt Control Register (UART_C_MISC)


UART_C_MISC is the register to control UART related interrupt.

Table 20. UART_C_MISC register definition


Name UART_C_MISC Offset 0x21C4 Width 32-bit
Bit R/W Name Default Description
31 - - 0 Reserved
30 R/W USE old Rx Baud 0 he Rx baud rate generator was re-designed to compute a
baud rate correctly. If you want to use the old (stupid) logic,

r!
you can set this bit to 1.
29 R/W ASYNC_FIFO_PURGE 0 Set to 1 after all UART bytes have been received in order to
purge the data into the async FIFO

o
28 R/W ASYNC_FIFO_EN 0 Automatically send to async FIFO module enable
1: enable automatic sending

o
0:disable automatic sending
27 R/W CTS_FIL_TB_SEL 0 CTS input filter time base selection.
A digital signal filter can be used to filter the UART CTS signal

d
input.
The filter has two parameters, the time base and the number

m
of time base.
0: The time base is 111nS.
1: The time base is 1uS.

E
26-24 R/W CTS_FIL_SEL 0 CTS input filter times
000: No filter.

111: Maximum filter time. The time is 7x 111= 777nS
to
(CTS_FIL_TB_SEL = 0) or 7x 1=7uS (CTS_FIL_TB_SEL = 1)
23-20 R/W BAUD_RATE_EXT 0 Extend the baud rate divider to 16-bits together with
UART_C_STATUS[11:0]
Baud_Rate = [BAUD_RATE_EXT: BAUD_RATE]
19 R/W RX_FIL_TB_SEL 0 RX input filter time base selection.
te

A digital signal filter can be used to filter the UART RX signal


input.
The filter has two parameters, the time base and the times of
u

time base.
0: The time base is 111nS.
1: The time base is 1uS.
ib

18:16 R/W RX_FIL_SEL 0 RX input filter times


000: No filter.

tr

111: Maximum filter time. The time is 7x 111= 777nS


(RX_FIL_TB_SEL = 0) or 7x 1=7uS (RX_FIL_TB_SEL = 1)
15:8 R/W XMIT_IRQ_CNT 32 Transmit FIFO threshold.
is

UART generates an interrupt when the number of bytes in


Transmit FIFO is below the value of these bits.
7:0 R/W RECV_IRQ_CNT 15 Receive FIFO threshold.
D

UART generates an interrupt when the number bytes in


Receive FIFO is large than the value of these bits.

5/22/2012 22/30 AMLOGIC Proprietary


UART Interface User Guide AML8726-MX Version 0.2

UART_C_REG5
Table 21. UART_C_REG5 register definition
Name UART_C_REG5 Offset 0x21c5 Width 32-bit
Bit R/W Name Default Description
31-24 R/W - 0 unused
23 R/W USE New Baud rate. 0 Over the years, the baud rate has been extended by
concatenating bits from different registers. To take
advantage of the full 23-bit baud rate generate (extended to
23 bits to accommodate very low baud rates), you must set

r!
this bit. If this bit is set, then the baud rate is configured
using bits [22:0] below
22:0 R/W NEW_BAUD_RATE: 0 If bit[23] = 1 above, then the baud rate for the UART is

o
computed using these bits. This was added in MX to
accommodate lower baud rates.

o
d
m
E
to
te
u
ib
tr
is
D

5/22/2012 23/30 AMLOGIC Proprietary


UART Interface User Guide AML8726-MX Version 0.2

9.4. UART_AO
The following registers are for UART_AO module and located in the AO power domain.

Write Buffer Register (AO_UART_WFIFO)


AO_UART_WFIFO is the data entry of UART transmit FIFO. Writing to the register puts a byte data into the top of
transmit FIFO. The data at the front of the FIFO transmits automatically until transmit FIFO empty.

Table 16. AO_UART_WFIFO register definition


Name AO_UART_WFIFO Offset 0x0130 Width 32-bit

r!
Bit R/W Name Default Description
31:8 - - 0 Reserved

o
7:0 W FIFO_WDATA - Write UART Transmit FIFO.

o
Read Buffer Register (AO_UART_RFIFO)
AO_UART_RFIFO is the data entry of UART Read FIFO. It latches the value of data byte at the front of UART

d
Read FIFO.

Table 29. AO_UART_RFIFO register definition

m
Name AO_UART_RFIFO Offset 0x0131 Width 32-bit
Bit R/W Name Default Description
31:8 - - 0 Reserved
7:0 R FIFO_RDATA 0x00
E
Read a byte from UART FIFO.
to
te
u
ib
tr
is
D

5/22/2012 24/30 AMLOGIC Proprietary


UART Interface User Guide AML8726-MX Version 0.2

UART_AO Mode Register (AO_UART_CONTROL)


AO_UART_CONTROL is a control register.

Table 17. AO_UART_CONTROL register definition


Name AO_UART_CONTROL Offset 0x0132 Width 32-bit
Bit R/W Name Default Description
31 R/W RTS_INV 0 Invert RTS signal. 0: RTS active LOW. 1: RTS active HIGH
30 R/W ERR_MASK_EN 0 Error Mask enable. 0: disable error mask. 1: enable error mask.
29 R/W CTS_INV 0 Invert CTS signal. 0: CTS active LOW 1: CTS active HIGH.

r!
28 R/W UART_TX_INT_EN 0 Transmit byte interrupt enable. When enabled, an interrupt will be
generated whenever a byte is read from Transmit FIFO.
0: disable transmit byte interrupt

o
1: enable transmit byte interrupt
27 R/W UART_RX_INT_EN 0 Receive byte interrupt enable. When enabled, an interrupt will be

o
generated whenever a byte is written to Read FIFO.
0: disable receive byte interrupt
1: enable receive byte interrupt

d
26 R/W UART_TX_INV 0 Invert TX signal. 0: TX active HIGH. 1: TX active LOW
25 R/W UART_RX_INV 0 Invert RX signal. 0: RX active HIGH. 1: RX active LOW

m
24 R/W UART_CLR_ERR 0 Clear error. Writing 1 to this register bit clears error.
Note: This bit does not clear to 0 automatically. Please set the bit
to 0 after clearing error manually.

E
23 R/W UART_RX_RST 0 Reset receive state machine. Writing 1 to this register bit resets
receive state machine.
22 R/W UART_TX_RST 0 Reset transmit state machine. Write 1 to this register bit reset
transmit state machine.
to
21:20 R/W UART_DATA_LEN 00 Character length of data.
00: 8-bit
01: 7-bit
10: 6-bit
11: 5-bit
te

19 R/W PARITY_EN 1 Parity enable bit. 0: disable parity bit. 1: enable parity bit
18 R/W PARITY_TYPE 0 Parity type bit. 0: even parity. 1: odd parity
17:16 R/W STOP_BIT_LEN 0 Stop bit length.
u

00: 1 stop bit


01: 2 stop bit
ib

10-11: reserved.
15 R/W TWO_WIRE_EN 0 Two-wire mode enables. 0: four-wire mode. 1: Two-wire mode
14 R/W - 0 Reserved
tr

13 R/W UART_RX_EN 0 Receive enable. 0: disable receive function. 1: enable receive


function
12 R/W UART_TX_EN 0 Transmit enable. 0: disable transmit function. 1: enable
is

transmit function
11:0 R/W BAUD_RATE 0x120 Baud rate setup. Please refer to Baud Rate Generation Section
for detail.
D

5/22/2012 25/30 AMLOGIC Proprietary


UART Interface User Guide AML8726-MX Version 0.2

UART_AO Status Register (AO_UART_STATUS)


AO_UART_STATUS is a read-only register to indicate the status of UART interface.

Table 31. AO_UART_STATUS register definition


Name AO_UART_STATUS Offset 0x0133 Width 32-bit
Bit R/W Name Default Description
31:27 - - 0x00 Reserved
26 R UART_RECV_BUSY 0 Receive state machine busy indicator. Being set to 1
indicates receive state machine is busy

r!
25 R UART_XMIT_BUSY 0 Transmit state machine busy indicator. Being set to 1
indicates transmit state machine is busy
24 R RECV_FIFO_OVERFLOW 0 Receive FIFO overflow indicator. Being set to 1 indicates

o
receive FIFO overflows
23 R CTS_LEVEL 0 CTS signal level.

o
22 R TX_FIFO_EMPTY 0 Transmit FIFO Empty indicator. Being set to 1 indicates
Transmit FIFO is empty

d
21 R TX_FIFO_FULL 0 Transmit FIFO Full indicator. Being set to1 indicates
Transmit FIFO is full.
20 R RX_FIFO_EMPTY 0 Receive FIFO Empty indicator. Being set to 1 indicates

m
Receive FIFO is empty
19 R RX_FIFO_FULL 0 Receive FIFO Full indicator. Being set to 1 indicates
Receive FIFO is full.

E
18 R TX_FIFO_WERR 0 Transmit FIFO writing error indicator. The bit is set to 1 if
writing data to Transmit FIFO when Transmit FIFO is full.
Note: Please use register AO_UART_CONTROL bit 24 to
clear this bit. Refer to AO_UART_CONTROL register
to
definition.
17 R FRAME_ERR 0 Frame Error indicator. The bit is set to 1if frame error
detected.
Note: Please use register AO_UART_CONTROL bit 24 to
clear this bit. Refer to AO_UART_CONTROL register
te

definition.
16 R PARITY_ERR 0 Parity Error indicator. The bit is set to 1 if parity error
detected.
u

Note: Please use register UART_CONTROL bit 24 to clear


this bit. Refer to AO_UART_CONTROL register definition.
ib

15 - - 0 Reserved
14:8 R TX_FIFO_DCNT 0 Transmit FIFO data count. The value is the number of
bytes in the Transmit FIFO.
7 R - 0 Reserved
tr

6:0 R RX_FIFO_DCNT 0 Receive FIFO data count. The value is the number of
bytes in the Receive FIFO.
is
D

5/22/2012 26/30 AMLOGIC Proprietary


UART Interface User Guide AML8726-MX Version 0.2

UART_AO Interrupt Control Register (AO_UART_MISC)


AO_UART_MISC is the register to control UART related interrupt.

Table 18. AO_UART_MISC register definition


Name AO_UART_MISC Offset 0x0134 Width 32-bit
Bit R/W Name Default Description
31 - - 0 Reserved
30 R/W USE old Rx Baud 0 he Rx baud rate generator was re-designed to compute a
baud rate correctly. If you want to use the old (stupid) logic,

r!
you can set this bit to 1.
29 R/W ASYNC_FIFO_PURGE 0 Set to 1 after all UART bytes have been received in order to
purge the data into the async FIFO

o
28 R/W ASYNC_FIFO_EN 0 Automatically send to async FIFO module enable
1: enable automatic sending

o
0:disable automatic sending
27 R/W CTS_FIL_TB_SEL 0 CTS input filter time base selection.
A digital signal filter can be used to filter the UART CTS signal

d
input.
The filter has two parameters, the time base and the number

m
of time base.
0: The time base is 111nS.
1: The time base is 1uS.

E
26-24 R/W CTS_FIL_SEL 0 CTS input filter times
000: No filter.

111: Maximum filter time. The time is 7x 111= 777nS
to
(CTS_FIL_TB_SEL = 0) or 7x 1=7uS (CTS_FIL_TB_SEL = 1)
23-20 R/W BAUD_RATE_EXT 0 Extend the baud rate divider to 16-bits together with
AO_UART_STATUS[11:0]
Baud_Rate = [BAUD_RATE_EXT: BAUD_RATE]
19 R/W RX_FIL_TB_SEL 0 RX input filter time base selection.
te

A digital signal filter can be used to filter the UART RX signal


input.
The filter has two parameters, the time base and the times of
u

time base.
0: The time base is 111nS.
1: The time base is 1uS.
ib

18:16 R/W RX_FIL_SEL 0 RX input filter times


000: No filter.

tr

111: Maximum filter time. The time is 7x 111= 777nS


(RX_FIL_TB_SEL = 0) or 7x 1=7uS (RX_FIL_TB_SEL = 1)
15:8 R/W XMIT_IRQ_CNT 32 Transmit FIFO threshold.
is

UART generates an interrupt when the number of bytes in


Transmit FIFO is below the value of these bits.
7:0 R/W RECV_IRQ_CNT 15 Receive FIFO threshold.
D

UART generates an interrupt when the number bytes in


Receive FIFO is large than the value of these bits.

5/22/2012 27/30 AMLOGIC Proprietary


UART Interface User Guide AML8726-MX Version 0.2

UART_AO_REG5(AO_UART_REG5)
Table 33. AO_UART_REG5 register definition
Name AO_UART_REG5 Offset 0x0135 Width 32-bit
Bit R/W Name Default Description
31-24 R/W - 0 unused
23 R/W USE New Baud rate. 0 Over the years, the baud rate has been extended by
concatenating bits from different registers. To take
advantage of the full 23-bit baud rate generate (extended to
23 bits to accommodate very low baud rates), you must set

r!
this bit. If this bit is set, then the baud rate is configured
using bits [22:0] below
22:0 R/W NEW_BAUD_RATE: 0 If bit[23] = 1 above, then the baud rate for the UART is

o
computed using these bits. This was added in MX to
accommodate lower baud rates.

o
d
m
E
to
te
u
ib
tr
is
D

5/22/2012 28/30 AMLOGIC Proprietary


UART Interface User Guide AML8726-MX Version 0.2

10. Address Mapping


The register addresses in previous sections are provided as address offset. Address mapping is needed to convert
register address offset to the physical register address.

The basic formula of address mapping is:

REG_ADDR = BASE_ADDR + (REG_OFFSET << 2)

r!
where:
REG_ADDR: physical register address that software can access the register
BASE_ADDR: the base address of the address bus

o
REG_OFFSET: the register address offset

o
The value of base address (BASE_ADDR) may be different in different software implementation. In Amlogic ported
Linux kernel and the boot loader uBoot, the base addresses for those registers which are not in the AO domain

d
are:

Linux Kernel: 0xF1100000

m
uBoot: 0xC1100000

For the registers in the AO domain, the base addresses are:

Linux Kernel:
uBoot:
0xF3100000
0xC8100000 E
to
Software needs to choose BASE_ADDR according to the implementation environment.
te
u
ib
tr
is
D

5/22/2012 29/30 AMLOGIC Proprietary


UART Interface User Guide AML8726-MX Version 0.2

11. Android™/Linux Kernel


Google Android™ and Linux kernel are ported on AML8726-MX by Amlogic. A Software Development Kit (SDK) is
provided with AML8726-MX. An Amlogic porting version Linux kernel includes in SDK with UART interface
definition and some tools.

11.1. Operation Macro Definition

r!
Some Macros are defined for UART programming.

Table 19 Andriod/Linux Register Operation Macro Defintion

o
Operation Marco
Writing a 32bit register WRITE_CBUS_REG(reg, val)

o
Read a 32bit register READ_CBUS_REG(reg)
Write a serial bit of register WRITE_CBUS_REG_BITS(reg, val, start, len)

d
Read a serial bit of register READ_CBUS_REG_BITS(reg, start, len)
reg: Register address index

m
val: Value of register
start: Start bit address of register
len: The length of bits

11.2. Register Macro Definition


E
Table 20. Android/Linux UART Register Macro Definition
to
UART Module Register Macro
UART_A_WFIFO UART_A_WFIFO
UART_A_RFIFO UART_A_RFIFO
UART_A_CONTROL UART_A_CONTROL
UART_A
UART_A_STATUS
te

UART_A_STATUS
UART_A_MISC UART_A_MISC
UART_A_REG5 UART_A_REG5
UART_B_WFIFO UART_B_WFIFO
u

UART_B_RFIFO UART_B_RFIFO
UART_B_CONTROL UART_B_CONTROL
ib

UART_B UART_B_STATUS UART_B_STATUS


UART_B_MISC UART_B_MISC
UART_B_WFIFO UART_B_WFIFO
tr

UART_B_REG5 UART_B_REG5
UART_C_RFIFO UART_C_RFIFO
UART_C_CONTROL UART_C_CONTROL
is

UART_C_STATUS UART_C_STATUS
UART_C
UART_C_MISC UART_C_MISC
UART_C_WFIFO UART_C_WFIFO
D

UART_C_REG5 UART_C_REG5
AO_UART_RFIFO AO_UART_RFIFO
AO_UART_CONTROL AO_UART_CONTROL
AO_UART_STATUS AO_UART_STATUS
UART_AO
AO_UART_MISC AO_UART_MISC
AO_UART_WFIFO AO_UART_WFIFO
AO_UART_REG5 AO_UART_ REG5

5/22/2012 30/30 AMLOGIC Proprietary