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si
-
PS
so
x=o X = l
s1 s2
x=o
1
X=l
0
when 4 =>
i f X-'O' t h e n
Z<='l' : N e x t s t a t e < = S ; e n d i f ;
s1 s3 s4 1 0 if X = ' l ' t h e n
s2 s4 s4 0 1 Z<='O'; N e x t s t a t e < = 6 ; e n d i f ;
when 5 =>
s3 s5 s5 0 1
i f X='O' t h e n
s4 S5 S6 1 0
S5 so so 0 1 Z<='O'; N e x t s t a t e < = O ; e n d i f ;
S6 so - 1 - i f x='l' t h e n
Z<=' 1 : N e x t s t a t e < = O : e n d i f :
when 6 =>
i f X='O' t h e n
Z<='l'; N e x t s t a t e < = O ; e n d i f ;
n when o t h e r s => n u l l : --should n o t o c c u r
e n d case;
end p r o c e s s ;
p r o c e s s (CLK) --State Register
begin
i f CLK='l' t h e n - - r i s i n g e d g e of c l o c k
S t a t e <= N e x t s t a t e ;
end i f ;
end process;
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-- The f o l l o w i n g i s a d e s c r i p t i o n of t h e Final Design Pro~ect
-- s e q u e n t i a l m a c h i n e of Table1 i n terms
-- of i t s n e x t s t a t e e q u a t i o n s . The s t a t e Students do a final design project which integrates
-- assignment follows:
-- SO-->O; S1-->4; S2-->5; S3-->7; many of the concepts taught in the course. They
-- S4-->6; S5-->3; S6-->2 carry out the following steps in their final design
project:
e n t i t y SM1-2 i s
port(X,CLK: i n b i t ;
(1) Develop a high level design consisting of a
2: out bit);
block diagram and an SM chart.
e n d SM1-2; (2) Write a behavioral level VHDL description,
simulate, test and debug it.
a r c h i t e c t u r e E q u a t i o n s of SM1-2 is
s i g n a l Ql,Q2,Q3: b i t ;
(3) Complete the logic design using appropriate
begin
components.
process (CLK) (4) Enter the logic schematic diagram using
begin Viewdraw; simulate, test and debug it using
i f CLK-'l' then Viewsim.
Ql<=not 42 after 10 ns; (5) Partition, place and route the design for FPGA
Q2<=Q1 a f t e r 1 0 n s ; imDlementation using- the XACT software from
Q3<=(Q1 a n d Q2 a n d Q3) o r ( ( n o t X ) a n d Q1 XILINX.
and (not 43)) o r (6) Download the final design to a FPGA and test it.
( X and ( n o t Q1) a n d ( n o t 43))
a f t e r 1 0 ns; Final design projects were chosen so that they will fit
end i f ;
e n d process;
into a single X3020 FPGA, which has 64 logic cells.
Z<=( ( n o t X ) and ( n o t Q 3 ) ) or ( X and Q3)
Examples of final projects are a bowling score
a f t e r 2 0 ns; computer, a 4-bit floating point adder or subtracter,
and an arithmetic-logic unit. Since the design has
been tested at steps (2) and (4), it is very likely that
Figure 3. Sequential machine model the design will work the first time it is downloaded.
using equations
Advantages and Disadvantages of
-- The f o l l o w i n g i s a STRUCTURAL VHDL Using VHDL
-- model of a s e q u e n t i a l n e t w o r k .
We previously used a hardware description language
l i b r a r y BITLIB; called DSDL (Digital System Design Language) [SI
use BITLIB.bitgack.al1; in the course. Use of VHDL offers several
e n t i t y SM1-2 i s advantages over DSDL. First, students learn an
port(X,CLK: i n b i t : industry-standard hardware description language.
2: o u t b i t ) ; Second, CAD tools which use VHDL are readily
e n d SM1-2; available for both PCs and workstations. Third,
a r c h i t e c t u r e S t r u c t u r e of SM1-2 i s VHDL is a very flexible language which is
s i g n a l A l , A2, A3, A 5 , A6, D3 : b i t : = I O * ; technology independent and which can be used to
s i g n a l Ql,Q2,Q3: b i t : = . O ' ; model a wide variety of digital systems.
s i g n a l QlN,QZN,QJN, XN: b i t : = ' l ' ;
begin
11: I n v e r t e r p o r t map (X,XN) ;
The main disadvantage of VHDL is its complexity.
GI: Nand3 p o r t map ( Q l , Q 2 , Q 3 , A l ) ; This can be overcome by teaching only part of the
G2: Nand3 p o r t map ( Q l , Q 3 N , X N , A Z ) ; language and gradually introducing new concepts as
G3: Nand3 p o r t m a p (X,QlN,Q2N,A3) ; needed. Proper use of VHDL requires a good
G4: Nand3 p o r t map (Al,A2,A3,D3); understanding of timing analysis of digital systems.
FF1: DFF p o r t m a p (Q2N, CLK, Q l , Q1N) ; In order to get correct results from a VHDL
FF2: DFF p o r t map (Ql,CLK,Q2,Q2N); simulation, it is necessary to understand the VHDL
FF3 : DFF p o r t map ( D 3 , CLK, Q3,Q 3 N ) ; simulation process. The cost of good VHDL CAD
G5: Nand2 p o r t map ( X , Q 3 , A 5 ) ; tools is rather high, but most vendors will give
G6: Nand2 p o r t map (XN,Q3N,A6);
G7: Nand2 port map (A5,A6,Z);
substantial educational discounts.
end S t r u c t u e :
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' l I ! I I ! ! l l l l l l l l l : l l , i l , l l , , , l l l l . , l l l l ~ l ~ i l i l
0 loo0 2000
Figiure 5. Timing waveform for Figure 2
~ i l l , l l l i , l l l l l , l , l i l ~ i l l l , l l l l l l i , l l l l l l l ~ i l l
0 1OOO 2000
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