Interleaving is Good for

Boost Converters, Too

By Ron Crews, Principal Applications Engineer, and
Kim Nielson, Senior Engineering Technician,
National Semiconductor, Phoenix
Long used to improve efficiency, reduce ripple,
and shrink capacitor and inductor size in buck
converters, the multiphase approach can pro-
vide the same benefits for boost converters.

T
here have been many articles describing the use As power densities continue to rise, interleaved boost
of multiphase buck converters, especially for designs become a powerful tool to keep input currents
high-performance point-of-load applications. manageable and increase efficiency, while still maintain-
However, all the advantages of interleaving, ing good power density. With mandates on energy savings
such as higher efficiency and reduced input more common, interleaved construction may be the only
and output ripple, are also realized in the boost topology. way to achieve design objectives. The benefits of this ap-
Most of the controllers used in buck applications apply proach are demonstrated by a two-phase boost converter
equally well when configured for use in an interleaved boost design built around the LM5032 pulse-width modulation
application. (PWM) controller.

L2
15 µH
J1 VOUT
12 V C1 C2 C3 C4 J3
to 2.2 µF 2.2 µF 2.2 µF 2.2 µF + C16 + C17 C18 C19
L3 C15 C20 48 Vdc
44 V L1 R5 150 µF 2.2 µF 2.2 µF 2.2 µF
15 µH D2 150 µF 0.1 µF 4.5 A
J2 330 µH 4.02 Ω
1 MBRB1560
VIN SW J4
VCC BST R3
GND C5 C6 R2 C7
0.1 µF 0.1 µF RON RCL 0.01 µF D1 22.1 Ω
110 kΩ C24
FB GND
ZHCS506TA 470 pF
R1 160 kΩ U2 R4
LM5009 7.32 kΩ R27
J5 R26 C23
R6 10 Ω
On/off 30.1 kΩ 0.1 µF
17.2 kΩ Q2
SUD50N06-9L R28
J7 24.9
R8 VCC 5 4 kΩ
C8
0.01 µF 2 kΩ R21 R20 R19 R18 R17 C25 1 –
0.1 µF U4 3 R29
0.11 Ω 0.11 Ω 0.11 Ω 0.11 Ω 0.11 Ω +
C9 U1 Q1 1.1
22 µF LM5032 2 LM8261
SUD50N06-9L kΩ
16 V 1 R11
R7 VIN OUT2 1 kΩ
1 kΩ DUTY CS2
R10
UVLO OUT1 1 kΩ R24 R22 R25
C10 VCC CS1 10 kΩ
R30 2 kΩ 4.75 kΩ
0.1 µF 69.8 kΩ REST COMP1
C11 C13 C14 R16 R15 R14 R13 R12
RT COMP2 0.11 Ω 0.11 Ω 0.11 Ω 0.11 Ω 0.11 Ω
100 pF 100 pF 100 pF R23 C21 U3
J6 SS1 PGND1 10 kΩ 0.1 µF LM4040 C22
SS2 PGND2
Sync C12 2.048 V
R9
69.8 kΩ 0.1 µF 0.1 µF
D3 CMHD4448

Fig. 1. A two-phase boost converter built around a current-mode PWM controller (U1) generates 48 V at up to 4 A, while operating
0508PETnational_F1
from an input of 12 V to 42 V.

Power Electronics Technology May 2008 24 www.powerelectronics.com

 boost converters

U3 VREF
Two-Phase Operation
2V In a two-phase converter, there are two output stages
R23 Q1
Fig. 2. Adding this that are driven 180 degrees out of phase. By splitting the
U1
10 kΩ current-sense current into two power paths, conduction (I2R) losses can be
R10 offset circuit, whichreduced, increasing overall efficiency compared to a singe-
1 kΩ
CS1 produces 185 mV, phase converter. Because the two phases are combined at
the output capacitor, effective ripple frequency is doubled,
to the circuit in Fig.
R12 to R16
0.015-Ω
1 permits the use of making ripple voltage reduction much easier. Likewise,
(composite
lower-value sense
value)
power pulses drawn from the input capacitor are staggered,
resistors and lowers reducing ripple current requirements.
losses in each phase. As in the buck counterpart, the designer has the choice
of achieving higher efficiency by using
the same rated components as in an

!EROSPACE$EFENSE-EDICAL

0508PETnational_F2
equivalent single-phase converter, by
reducing component sizes to lower costs

STATEOFTHEARTRESISTORS or by using some combination of these

two approaches.
In the example described here, a boost
converter is needed to generate a 48-V
supply with high efficiency for a telecom
application. The converter must be able to
operate over a wide input-voltage range to
accommodate a variety of input sources
including batteries. Because of the wide
input range, the converter also must be
able to operate with a wide input-voltage
to output-voltage ratio.
Here, the boost MOSFETs and induc-
tors are sized for 12 A of input current. The
output capacitors are chosen to limit out-
put-voltage ripple to 500 mV (1%) or less.
Overall, the goal is to push the efficiency to
a high-enough level to allow operation at
room temperature with no airflow, while
7HENAWINDOWOFOPPORTUNITYCANTBEMISSED
still meeting all the other requirements.
7HENBEINGONTARGETSAVESLIVES Specifically, the design goals are: VIN =
12 V to 44 V, VOUT = 48 V, ILOAD = 4 A,
7HENALIFEDEPENDSONIT VRIPPLEOUT < 500 mV, POUT = 192 W and
efficiency > 95%.
9OUNEED3TATEOFTHE!RTRESISTORS
Fig. 1 shows the schematic of the boost
3UPERIORQUALITYESTABLISHEDRELIABILITY converter. The circuit is built around a
MILLION
INSTOCK two-phase current-mode PWM control-
ler (U1) with separate inputs for current
limit and compensation for each channel.
53!MADETECHNOLOGYYOUCANTRESIST Using current-mode control ensures the
two channels share current closely.
3TATEåOFåTHEå!RTå)NC Both channels are fabricated within
2%3)34)6%02/$5#43 the same IC, so even the lot-to-lot varia-
tions are minimized. The separate inputs
WWWRESISTORCOM
for the PWM comparator are combined in
this design, because we are implementing
a two-phase single-output converter, not
15!,)&)#!4)/.3
two independent converters.
&OX(ILL2OAD3TATE#OLLEGE0!  )3/!3
-), 02&  The two current-sense inputs are used
0HONE  OR   -), 02& 
&AX  % MAILSALES RESISTORCOM -), 02& 
to keep the current balanced in each
phase. Each output phase drives its own

Power Electronics Technology May 2008 26 www.powerelectronics.com

?3TATEOFTHE!RTINDD !-
 boost converters
power channel consisting of switching
MOSFETs Q1 and Q2 and inductors
L2 and L3. Output diode D2 is a dual
common-anode device that feeds the
common bank of output capacitors C15
to C19. The IC is internally configured
to drive its two outputs 180 degrees out
of phase.
A single feedback network consist-
ing of error amplifier U4 and associated
passive-loop compensation compo-
nents drive both comparator (COMP)
inputs on U1, which are tied together
at the IC. Fig. 3. In this boost converter prototype, the PWM controller, power inductors and
To reduce the sense-resistor losses, a Schottky rectifier are placed on top of the board (a), while the bias supply and the
dc offset circuit (Fig. 2) was introduced switching MOSFETs are located on the bottom of the board (b) to complete a compact
to offset the current-sense inputs by 185 design.
mV. This allowed the use of lower-value interact with the actual sensed current waveform. More off-
sense resistors in each phase, reducing I2R losses. set could be used; however, compressing the actual current
Reference U3 is already in use as the error amplifier signal could introduce noise issues if taken too far.
reference. Resistors R23, R18 and the current-sense resis- To further reduce losses, a switching bias supply was
tors form a voltage divider from the 2-V reference. With the constructed with adjustable controller U2. As can be seen
values from Fig. 1, the dc offset is 0.185 V, effectively reduc- from the photograph of the actual prototype in Fig. 3, this
ing the current-limit threshold of 0.5 V by that amount. As circuit is very small and offers a good solution for a bias
long as R23 is much larger than R18, and with R18 much supply. The prototype board measures 2.6 in. 3 2.4 in.
larger than the sense resistors, the dc offset will not adversely If a linear regulator or zener diode were used, it would

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www.powerelectronics.com 27 Power Electronics Technology May 2008

 boost converters
be necessary to drop about 31 V from the input
100 supply at VINMAX. By supplying the necessary
98
bias with an overhead current of 500 mA, a
96
94
loss of about 16 W was avoided.
Diode D3 prevents the error amplifier
Efficiency (%)

92
90 from holding the comp pin of U1 high during
VIN = 12 V
88 VIN = 24 V
startup, effectively configuring the error ampli-
86 VIN = 36 V fier as sink only. The PWM controller contains
84 VIN = 42 V a 5-kΩ pull-up resistor.
82 A prototype of the circuit in Fig. 1 is pic-
80 tured in Fig. 3. Here, the two power inductors
0.1
0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 occupy the top part of the left photograph, with
Load (A)
rectification accomplished with the common-
Fig. 4. Measurements taken on the boost converter prototype attest to the fact that cathode Schottky diode located just below the
a compact boost design can also achieve high efficiency. inductors. The LM5032 PWM controller is
located in the lower left portion of the board.
On the bottom side of the board in Fig. 3, the bias supply
is located near the upper right, with the two switching FETs
0508PETnational_F4
at center right. The error amplifier is located near the top left
of the board. No heatsinking other than the copper in the pc
board is used. A four-layer board was used for compactness
of design and heat-dissipation properties.

Operational Results
Referring to the plots in Fig. 4, using data from the actual
prototype, efficiencies range from 95% to 98% up to the full
load current of 4 A, and over a 3.5:1 input-voltage range.
In the very low current region (less than 200 mA) where
overhead-bias currents dominate, the converter does have
Fig. 5. Thermal less efficiency, but this is true for all regulators. These plots
images of the illustrate the possibility of building a compact, high-power
prototype board boost converter without sacrificing excellent efficiency.
operating at full Referring to the thermal images in Fig. 5, the component
power. The up- with the maximum temperature is Q2, which is operating
per image is the at a case temperature of 77°C. Q2 is hotter than Q1 since it
board top side. is directly opposite D2, which also dissipates considerable
heat. Since the junction-to-case thermal resistance of Q2 is
1°C/W, and since Q2 dissipates about 4 W maximum, its
3.5
junction temperature is about 81°C. The ambient tempera-
3.0 ture is 25°C. Q2 is the hottest component on the board, and
Single phase is well within its thermal rating. Refer to the board photos
2.5 in Fig. 3 for location of components.
Two phase
Input and output ripple reduction are some of the ben-
IRMS / IOUT

2.0

1.5
efits of an interleaved converter. Since the output ripple is
double the frequency of the individual phases and at a lower
1.0 root-mean-square (rms) current value, the designer has the
0.5 choice of using smaller output capacitors with the same
0 ripple as a single-phase converter or using larger capacitors
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 to achieve even lower output ripple.
Duty cycle
Effective ripple is a function of duty cycle. Using data
from the actual prototype, Figs. 6 and 7 illustrate the input
Fig. 6. Normalized input-capacitor rms ripple current is measured and output ripple currents versus duty-cycle relationships.
as a function of duty cycle. Although the output capacitor must Ripple reduction is a function of duty cycle, as the degree
be chosen to withstand high ripple current inherent in any boost of ripple overlap is a function of duty cycle. There is near-
design, the0508PETnational_F5
capacitor can be significantly smaller in a two-phase perfect cancellation of ripple at 50% duty cycle. This opens
design than in a single-phase implementation. the intriguing possibility of building a converter with little

Power Electronics Technology May 2008 28 www.powerelectronics.com

 boost converters

1.0
0.9
Single phase
0.8 Two phase
0.7
0.6
IRMS / N

0.5
0.4
0.3
0.2
0.1
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Duty cycle

Fig. 7. The normalized input-capacitor rms ripple current is

measured as a function of duty cycle. Normalization factor
N is given by N = VIN /(L 3 fS ).
0508PETnational_F6
to no output ripple if the designer can limit VIN to the proper
value for 50% duty cycle.
In the more general case, ripple is reduced by as much
as 50% compared to an equivalent-power single-phase
converter. Likewise, inductor selection is flexible with the
two-phase design. One-half the single-phase inductor value
can be chosen, which will make each inductor smaller, but
which results in the same ripple currents as the single-phase
design. Or the inductors can remain the same value as in the For superior solutions
single-phase design, reducing the ripple by one-half.
The proper tradeoffs will depend on the overall design in consumer electronics
goal. Attention to ESR requirements will keep capacitors
within temperature ratings and the output voltage ripple s &ILMCAPACITORSFOR%-)SUPPRESSION
within specifications.
Fig. 6 plots normalized output capacitor ripple current s #APACITORSFORMOTORSTARTANDMOTORRUN
versus duty cycle. This graph shows the ripple cancellation s 7IDERANGEOF04#.4#THERMISTORS
at 50% duty cycle and the general ripple reduction across ANDTEMPERATURESENSORS
all duty cycles with the two-phase topology. The output
s 3!7COMPONENTSFORMULTIMEDIASYSTEMS
capacitor must be chosen to withstand the high ripple cur-
rent inherent in a boost design. However, as can be seen in s 3-4POWERINDUCTORSFORCONVERTERS
Fig. 6, it can be significantly smaller than in a single-phase s &ERRITESCHOKESANDTRANSFORMERS
implementation.
s 6ARISTORSFOROVERVOLTAGEPROTECTION
Fig. 7 plots normalized input-capacitor ripple current
versus duty cycle. In this case, the normalization is chosen
to simplify the graph scale.
This prototype illustrates that the many benefits of
interleaving, which are routinely used in buck regulators,
apply equally well to an interleaved boost design. In the
design presented here, the impressive power-conversion
efficiency results in a 192-W, all-surface-mount design that
will operate without airflow at room ambient.
This design could easily be upgraded to higher power
by the proper selection of power components. Also, since
the selection of output voltage and input voltage are at the
designer’s discretion, the basic design could be adapted
to many battery-powered applications. By overdesigning
the power components and/or reducing the switching
frequency, efficiency could be improved if that were the
primary design goal. PETech www.epcos.com

www.powerelectronics.com 29 Power Electronics Technology May 2008