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Examples Guide
Copyright © 2012
Tanner Tools v16 – Examples Guide
TABLE OF CONTENTS
Section 1 Designs ...........................................................................................5
Section 1.1 ADC8 .......................................................................................... 5
Section 1.1.1 ADC8_Testbench .......................................................................... 5
Section 1.1.2 DAC8_Testbench .......................................................................... 6
Section 1.1.3 COMP_DC_Testbench .................................................................. 8
Section 1.1.4 COMP_TRAN_Testbench.............................................................. 9
Section 1.2 ADC – Behavioral ..................................................................... 10
Section 1.3 Bargraph .................................................................................. 10
Section 1.4 BusesAndArrays ....................................................................... 10
Section 1.4.1 Simple Buses .............................................................................. 10
Section 1.4.2 Splitting Buses ............................................................................ 10
Section 1.4.3 Port Bundles ............................................................................... 10
Section 1.4.4 1-Dimensional Arrays ................................................................. 11
Section 1.4.5 2-Dimensional Arrays ................................................................. 11
Section 1.5 CCD Imager .............................................................................. 11
Section 1.6 Comparator – One Bit.............................................................. 11
Section 1.7 CPU .......................................................................................... 11
Section 1.8 DecayMeasurement-Verilog ................................................... 11
Section 1.9 DLatch ...................................................................................... 11
Section 1.10 GaAsAmp ................................................................................. 11
Section 1.11 GlobalNets ............................................................................... 12
Section 1.11.1 Simple Global Nets ..................................................................... 12
Section 1.11.2 Separate Power Supplies............................................................ 12
Section 1.11.3 Renaming Separate Power Supplies .......................................... 14
Section 1.11.4 Renaming Separate Power Supplies – Alternate Method ......... 15
Section 1.12 ICResistors ............................................................................... 15
Section 1.13 Inverter .................................................................................... 16
Section 1.13.1 DC Operating Point Analysis....................................................... 16
Section 1.13.2 DC Transfer Analysis and Parameter Sweep .............................. 21
Section 1.13.3 Transient Analysis ...................................................................... 24
Section 1.14 Lights (Traffic Light Controller) ................................................ 27
Section 1.15 LinearFeedbackShiftRegister ................................................... 28
Section 1.16 MonitorVoltageRange-Verilog ................................................ 28
Section 1.17 MOS_Subthreshold ................................................................. 28
Section 1.18 MultipleSymbolViews .............................................................. 28
Section 1.18.1 MOSFET with 4- and 3-terminal symbols ................................... 28
Section 1.18.2 NMOS with IEEE and IEC symbols .............................................. 29
Section 1.18.3 Adder with 3 different symbols ................................................. 29
Section 1.19 OpAmp ..................................................................................... 30
Section 1.19.1 AC Analysis ................................................................................. 30
Section 1.20 Parameterized_NAND ............................................................. 34
Section 1.20.1 Using Subcircuits ........................................................................ 34
Section 1.21 PLL-Behavioral ......................................................................... 38
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Section 1 Designs
DesignType: Mixed-Signal
Features: S-Edit, T-Spice, W-Edit
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DesignType: Digital
Features: S-Edit
This example illustrates the basic syntax and usage of buses and arrays. An 8-bit wide bus, In<1:8>, is
split into two buses, one containing the even numbered bits and the other containing the odd
numbered bits. The third value in the bus specification, indicating a step value of 2, is used to
perform this split. The even numbered bits connect to a 4x array of inverters, and the odd numbered
bits connect to a 4x array of buffers. The inverter and the buffer each have a single input and output
connection, so the 4x arrays of each of these provides a 4-bit wide input and output connection to
match the dimension of the buses that connect to them. When connecting buses to instances or
arrays of instances, it is important to make sure that the dimensions match. Invoking Tools > Design
Checks will issue warnings for mismatched bus and instance dimensions. The output of the inverters
and the output of the buffers are then combined to form an 8-bit wide output bus, Out<1:8>.
This example illustrates the labeling requirements when splitting buses. An 8-bit wide bus, In<0:7>,
is input to an 8x array of inverters, and an 8-bit wide bus, D<0:7>, is output. The 8-bit bus D<0:7> is
then split into a 5-bit wide bus, D<3:7>, and a 3-bit wide bus, D<0:2>. Note that whenever there is a
T-junction of buses, all branches of the “T” must be explicitly labeled in order to unambiguously
identify the dimension and components of each branch. Individual bits D<2>, D<1>, and D<0> are
then ripped from the bus and connected to a buffer, inverter, and another buffer, and output as
nets Q, R, and S, respectively.
This example illustrates the use of port bundles in a symbol. This example is similar to Top_SplitBus,
however here the 8-bit input bus, In<0:7>, is connected to a single instance, Inv8a, rather than to an
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array. The symbol of Inv8a contains an 8-bit port bundle, A<0:7>, to which the input bus is
connected, thereby matching dimensions of the bus with the instance connection. The port bundle
can be a single bus, A<0:7>, as is the case in this example, or it could be a collection of buses and
nets, such as A<0:4:2>, B<0:3>, C. The output of the instance is an 8-bit port bundle, Out<0:7>
which connects to an 8-bit wide bus, Qu, Rb, Su, D<3:7>. The 8-bit bus Qu, Rb, Su, D<3:7> is then
split into a 5-bit wide bus, D<3:7>, and a 3-bit wide bus, Qu, Rb, Su. Individual bits Qu, Rb, and Su
are then ripped from the bus and connected to a buffer, inverter, and another buffer, and output as
nets Q, R, and S, respectively.
This example illustrates how to connect the input and output of an array to form a connection in
series. The input into the 5x array of inverters is In, N<0>, N<1>, N<2>, N<3>, and the output is
N<0>, N<1>, N<2>, N<3>, Out. Notice the offset by one in the position of N<0:3> in the naming of
the input and output buses. This causes the output of one inverter to be connected to the input of
the next inverter. The connection is formed by naming the output and input labels with the same
name. There does not need to be a wire actually making a connection. In addition, as can be seen
for the input, no physical wire connection is made between the In port and the bus. For the output,
a wire connection is made and the net is labeled Out to match that of the Out port. Either method
will produce the same result.
This example illustrates the usage and syntax of two dimensional arrays. Arrays Left, Top, Bottom,
and Right are 1-D arrays which are connected to around the perimeter of a 2-D array Cen using a
connection by name, similar to that used in Top_1DArrays.
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DesignType: Digital
Features: S-Edit
Global nets in S-Edit are connected through the design hierarchy, without explicitly placing ports for
them at every level. In this example there are two cores, CoreHV_Global and CoreLV_Global
instanced in cell Top_GlobalNets. Inside CoreHV_Global, we have instances of Block2 and Block3,
and inside CoreLV_Global we have instances of Block1 and Block2. These can be seen in the .subckt
definitions of CoreHV_Global and CoreLV_Global in the netlist below. Each schematic of Block1,
Block2, and Block3 has a global symbol for Vdd and Gnd.
In this design, Vdd and Gnd are global, and are connected through the entire design hierarchy.
XCoreHV_Global_1 N_3 N_5 N_2 N_4 N_1 N_6 Gnd Vdd CoreHV_Global
XCoreLV_Global_1 N_10 N_8 N_11 N_9 N_12 N_7 Gnd Vdd CoreLV_Global
.end
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This example illustrates how to isolate the global Vdd nets contained inside two cells. Consider the
two core cells in the Top_GlobalNets design. We wish to isolate the global Vdd in CoreHV_Global
from the global Vdd in CoreLV_Global.
The design in Top_VddIsolation has been modified by adding netcaps for Vdd in CoreHV_VddNetCap
and CoreLV_VddNetCap. The name of the netcap must match the name of the net being capped,
including case sensitivity, in order for the net to be properly capped. Notice now that Vdd no longer
appears in the parameter list for the definition of CoreHV_VddNetCap and CoreLV_VddNetCap in the
netlist below, and is correspondingly absent in the calls to CoreHV_VddNetCap and
CoreLV_VddNetCap in the main circuit. The Vdd inside subcircuit CoreHV_VddNetCap and the Vdd
inside subcircuit CoreLV_VddNetCap are therefore not connected to each other.
.end
The Vdd nets in CoreHV_VddNetCap and CoreLV_VddNetCap can be reconnected by removing the
netcaps, or alternatively by placing the following command in the SPICE netlist:
.global Vdd
The .global command can be automatically put into the netlist in S-Edit, by creating a symbol with
the following property:
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The symbol can then be instanced at the top level of the design. An example of this can be viewed
by opening design example Top_VddReconnectNetCap.
This example illustrates how to isolate the global Vdd nets in two cells from each other, and to
connect to them with unique names. Consider the two core cells in the Top_VddIsolationRename
design. In Top_VddIsolation, we isolated the Vdd in CoreHV_VddNetCap from the Vdd in
CoreLV_VddNetCap. We now wish to connect to CoreHV_VddNetCap with a net named Vdd_5v and
to CoreLV_VddNetCap with a net named Vdd_3v.
In this example, the design in Top_VddIsolationRename has been modified by adding “In” ports
Vdd_HV and Vdd_LV to cores CoreHV_VddRename and CoreLV_VddRename respectively, both on
the schematic and symbol views. On the schematic views, the new ports are connected to the
netcaps, thus continuing the propagation of the Vdd net up the hierarchy, but with a different
name. In the calls in the main circuit, you can see nets Vdd_5v connecting to cores
CoreHV_VddRename and Vdd_3v connecting to CoreLV_VddRename.
.end
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This example illustrates another way to isolate the global Vdd nets in two cells from each other, and
to connect to them with unique names. Consider the two core cells in the Top_VddIsolation design.
In Top_VddIsolation, we isolated the Vdd in CoreHV_Global from the Vdd in CoreLV_Global. We now
wish to connect to CoreHV_Global with a net named Vdd_5v and to CoreLV_Global with a net
named Vdd_3v.
In this example, the design in Top_VddIsolation has been modified by adding “Global” ports Vdd_5v
and Vdd_3v to the schematic views of cores CoreHV_VddRenameGlobal and
CoreLV_VddRenameGlobal respectively. The new ports are connected to the netcaps, thus
continuing the propagation of the Vdd net up the hierarchy, but with a different name. The name of
the Global port takes precedence over the name of the netcap. In the calls in the main circuit, you
can see net Vdd_5v connecting to CoreHV_VddRenameGlobal and Vdd_3v connecting to
CoreLV_VddRenameGlobal.
.end
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DesignType: Digital
Features: S-Edit
T-Spice – Analysis Examples – DC_Op_Point, DC_Sweep, Monte_Carlo,
Parameter_Sweep, Transient
DC operating point analysis finds a circuit’s steady-state condition, obtained (in principle) after the
input voltages have been applied for an infinite amount of time.
Each of the components visible in the schematic has properties associated with it. Properties are
textual elements, created in S-Edit, that are attached to an object and provide key information
about its design and simulation commands in T-Spice. If you "push in" to open a specific instance,
you can see that the physical dimensions of the component
M1n in the inverter are defined by the properties:
M=1
W = 1.5u
L = 0.25u
M1n is an instance of the symbol NMOS_2_5v, which represents an n-channel MOSFET transistor.
Properties that describe the operation of a generic n-channel MOSFET are defined at the symbol
level. Properties specific to component M1n, such as length and width, are defined when M1n is
created. Property values defined at the component level take precedence over default (symbol)
values.
Prior to running the T-Spice simulation, the analysis commands and all processing options need to
be established. This is accomplished using the Setup SPICE Simulation dialog in S-Edit.
Ensure that you are viewing the top level schematic. For this example, the top level cell is named
Inverter_TestBench. Right-click on Inverter_TestBench in the Libraries window and use Open View to
select the schematic OperatingPoint.
Use Setup > SPICE Simulation… to launch the Setup SPICE Simulation dialog. The proper simulation
settings for the Inverter_TestBench example have already been entered for you. Note that the DC
Operating Point Analysis box is checked. Also note the settings in the General options for File Search
Path and Library Files. Export the Netlist to T-Spice.
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In the Inverter_Testbench - Operating Point schematic, use Tools > Design Checks > View and
Hierarchy to execute the Design Checker. The Design Checker will display any violation or errors in
the Command window. There should not be any errors in Inverter_Testbench - Operating Point.
Press the T-Spice icon ( ) to export a T-Spice netlist file named InverterOP.sp. S-Edit will launch T-
Spice with the InverterOP.sp netlist open:
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.end
Two transistors, MM2p and MM1n, are defined in InverterOP.sp. These are MOSFETs, as indicated
by the key letter M that begins their names. Following each transistor name are the names of its
terminals in the required order: drain–gate–source–bulk. Then the model name (PMOS25 or
NMOS25 in this example) and physical characteristics, such as length and width, are specified. A
capacitor CC1 (signified by the key letter C) connects nodes N_1 and GND with a capacitance of 1p.
Strictly speaking, the capacitor could be omitted from the circuit for this example, since it does not
affect the DC operation of the inverter. Two DC voltage sources are defined: VVin, which sets node
N_2 to 1.0 volt relative to ground and VVpower, which sets node Vdd to 3.3 volts as defined by the
variable Vpwr.
Notice that the simulation settings which were entered in the SPICE Simulation Setup dialog resulted
in .option, .lib, and .op commands being written to the T-Spice input file. The .lib
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command causes T-Spice to read the contents of the Generic_025.lib library file for the evaluation
of transistors MM2p and MM1n, and the search option identifies the path to the library files. In this
case, the library file contains two device .model commands, describing MOSFET models PMOS25
and NMOS25, as shown below for PMOS25:
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Generic_025.lib assigns values to various Level 49 MOSFET model parameters for both n- and p-
channel devices. T-Spice uses these parameters to evaluate Level 49 MOSFET model equations. The
.op command performs a DC operating point calculation and writes the results to the file specified
in the Simulation > Run Simulation dialog.
With InverterOP.sp open in T-Spice, use File > Save to save the file. Click the Run Simulation button
( ) in the T-Spice simulation toolbar. T-Spice will open a new window displaying the simulation
log.
1.13.1.5. Output
The output file lists the DC operating point information for the circuit. You can read this file in T-
Spice or any text editor.
If not already displayed, select View > Simulation Manager from the T-Spice menu to open the
Simulation Manager:
Right-click the InverterOP.out display line in the window, then click Show Output… to open the
output file InverterOP.out in a new T-Spice window. If you prefer to view the output in a text
editor, simply open InverterOP.out as a text file. It is located in the same directory as the input file.
The output file contains the following DC operating point information (in addition to comments of
various kinds, not shown here. (You can also view DC operating voltages, currents and small-signal
parameters in S-Edit.)
DC ANALYSIS - temperature=25.0
v(N_1) = 3.1819e+000
v(N_2) = 1.0000e+000
v(Vdd) = 3.3000e+000
i1(VVin) = -0.0000e+000
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i2(VVin) = 0.0000e+000
i1(VVpower) = -1.9514e-004
i2(VVpower) = 1.9514e-004
DC transfer analysis is used to study the voltage or current at one set of points in a circuit as a
function of the voltage or current at another set of points. This is done by sweeping the source
variables over specified ranges and recording the output.
This schematic includes a .print command, which measures and records voltages at the input and
output nodes of the circuit. The command is contained within the DC analysis output cell.
Press the S-Edit icon ( ) to run the simulation from S-Edit. S-Edit will automatically launch T-Spice
and will create and run a T-Spice netlist file named InverterOP.sp. The netlist will be exported as
follows:
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.end
The .DC command, indicating transfer analysis, is followed by the parameter lin, which specifies a
linear sweep. Next is a list of sources to be swept, and the voltage ranges across which the sweeps
are to take place. In this example, VVin will be swept from 0 to Vpwr volts in 0.02 volt increments.
The .step command then sweeps Vpwr from 2.3 to 4.3 volts in 0.5 volt increments.
The transfer analysis will be performed as follows: Vpwr will be set at 2.3 volts and VVin will be
swept over its specified range; Vpwr will then be incremented to 2.5 volts and VVin will be reswept
over its range; and so on, until Vpwr reaches the upper limit of its range.
The .DC command ignores the values assigned to the voltage sources Vpwr and VVin in the voltage
source statements; however, they must be declared in those statements. The resulting voltages for
nodes “In” and “Out” are reported by the .PRINT DC command to the specified destination.
1.13.2.3. Output
When W-Edit launches, simulation results of the same data type, which in this case is voltage, are
automatically plotted on a single chart. In this example, traces were separated into different charts
and reorganized (according to data type) using the commands in Chart > Expand Chart (page 109) of
the W-Edit menu.
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The charts below show input and output voltages to the circuit, with separate traces for each sweep
of v(Out). To view detailed information about a trace, double-click on the trace or on the trace label
located in the upper right corner of the chart.
The Trace Properties dialog displays the value of parameter v(Out) corresponding to each trace, as
well as labels and line properties. For more information on trace properties, see "Properties" on
page 100 of the W-Edit User Guide.
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Transient analysis provides information on how circuit elements vary with time. The basic T-Spice
command for transient analysis has three modes. In the Op mode (default), the DC
operating point is computed, and T-Spice uses this as the starting point for the transient simulation.
This example illustrates this option. The other startup modes, Powerup and Preview, are shown in
the proceeding examples titled Transient Analysis, Powerup Mode and Transient Analysis, Preview
Mode.
Press the S-Edit icon ( ) to run the simulation from S-Edit. S-Edit will automatically launch T-Spice
and will create and run a T-Spice netlist file named InverterTRAN.sp. The netlist will be exported as
follows:
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.end
This circuit is similar to that of DC Operating Point Analysis, except that voltage source VVin in this
schematic generates a pulse (indicated by the keyword PULSE) to “In”, rather than setting a
constant value.
The times and voltages that define the “legs” of the waveform are specified in the arguments to
PULSE. The initial current is zero amperes and the peak current is Vpwr, with an initial delay of
zero seconds. The rise and fall times are one nanosecond, with a pulse width of 49 nanoseconds and
a pulse period of 100 nanoseconds. The .tran command specifies the characteristics of the
transient analysis to be performed. In this example, the maximum time step allowed is 250 pico
with a total duration of 300 nanoseconds.
1.13.3.3. Output
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DesignType: Digital
Features: S-Edit
L-Edit – SPR, StdDRC, StdExtract, HiPer Verify
LVS
This example shows the organization of a project into libraries. Here Lights is the main design. The
schematic can be exported to a TPR netlist for use in Standard Place and Route in L-Edit.
This example shows how to perform Standard Cell Place and Route. Use netlist file Lights.tpr
exported from S-Edit with Standard Cell Library Lightslb.tdb to perform SPR.
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\Process\Generic250nm\Generic250nmTech\Generic_025-DRC.cal
Completed layout can be extracted with Standard Extraction using extraction definition file
Lights.ext.
Compare the extracted layout netlist Lights.spc with the schematic netlist Lights.sp to track down
any discrepancies.
DesignType: Digital
Features: S-Edit
This example illustrates the use of multiple views in a cell. The cell NMOS in the Devices library is an
NMOS MOSFET, and there is a 4-terminal symbol and a 3-terminal symbol whose fourth terminal is
automatically connected to ground. Cell NMOS consists of two interface views and two symbol
views, as follows:
There is no schematic view for cell NMOS as the cell is a SPICE primitive.
The fourth terminal of the 3-terminal MOSFET in view NMOS3 is connected to ground by writing 0 in
the SPICE.OUTPUT property. Compare the SPICE properties of each symbol.
SPICE.PREFIX = M
SPICE.PINORDER = D G S B
SPICE.MODEL = $Model
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SPICE.PARAMETERS = W= L= M~ AS= PS= AD= PD= NRD~ NRS~ RDC~ RSC~ RSH~ GEO~
TABLES~
SPICE.PREFIX = M
SPICE.PINORDER = D G S
SPICE.MODEL = $Model
SPICE.PARAMETERS = W= L= M~ AS= PS= AD= PD= NRD~ NRS~ RDC~ RSC~ RSH~ GEO~
TABLES~
SPICE.OUTPUT = ${SPICE.PREFIX}$Name %% 0 $Model $$
This example illustrates the use of multiple symbol views in a cell. The cell NOR2 is a NOR gate, and
there is an IEEE and IEC symbol view. Cell NOR2 consists of one interface view, two symbol views,
and one schematic view, as follows:
Both symbols IEEE and IEC each reference the same interface and the same schematic. The only
difference is how the symbol will look when instanced into a schematic.
This example illustrates the use of multiple symbol views in a cell. The cell is an Adder, and there are
three symbol views, one interface view, and one schematic view, as follows:
When drawing a schematic, it is sometimes convenient to have the pins of a symbol arranged in one
particular order for making connections, and at other times one wants the pins arranged in a
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different order. This can be accomplished by having multiple symbol views, each of which has a
different arrangement of pins. Here, one symbol (Pins_Sequential) has input pins ordered on the left
side as A0, A1, A2, A3, B0, B1, B2, B3, a second symbol (Pins_Interleaved) has pins ordered as A0, B0,
A1, B1, A2, B2, A3, B3, and a third symbol (Pins_Bus) has pins grouped in busses. This is purely for
drawing convenience, and does not affect the order of pins as written to SPICE.
DesignType: Analog
Features: S-Edit
T-Spice – Analysis Examples – AC, AC_Noise, DC_Op_Point, DC_Sweep
This example involves a standard operational amplifier, consisting of one PMOS, one NMOS, a
transconductance amplifier and one capacitor.
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.end
Vdiff sets the DC voltage difference between nodes “in2” and “in1” to 0 volts. The AC magnitude is
1 volt and its AC phase is 0 degrees.
Vcm sets node “in2” to 2 volts, relative to GND.
Vbias sets node “vbias” to 700 millevolts, relative to GND.
The .ac command performs an AC analysis. Following the .ac keyword is information concerning
the frequencies to be swept during the analysis. In this case, the frequency is swept logarithmically,
by decades (dec); 10 data points are to be included per decade; the starting frequency is 1 Hz and
the ending frequency is 100 MHz. The .PRINT command writes the voltage magnitude (in
decibels) and phase (in degrees), respectively, for the node “Out” to the specified file. The other
print and measurement commands are discussed in
alternate examples.
1.19.1.2. Output
The AC simulation will result in AC small-signal model parameters being written to the output file, in
addition to all output generated from the .print statements.
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DesignType: Digital
Features: S-Edit
T-Spice – Analysis Examples – Transient
Subcircuit definitions allow arbitrarily complex arrangements of nodes and devices to be easily
reused multiple times in a circuit. A subcircuit definition in S-Edit is contained within a cell definition,
and is comprised of both a schematic view and a symbol view. Each instance of the symbol
encapsulates the subcircuit schematic, allowing a simple but complete representation of subcircuit
dynamics. This example uses a NAND gate to illustrate the use of subcircuit definitions and
subcircuit parameters.
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An instance of the subcircuit NAND2C is created in the schematic and labeled X1. To access NAND2C
from the main schematic, double-click on the NAND2C item in the Libraries list.
As discussed in DC Operating Point Analysis, symbol properties are used to define component
properties such as length and width. This example introduces a new symbol property,
SPICE.PARAMETERS, which allows parameters to be passed through a hierarchical netlist.
The symbol that represents NAND2C has the SPICE parameter property:
SPICE.PARAMETER = L= NW= PW=
This property specifies that the cell properties L, NW, and PW are subcircuit parameters of NAND2C.
The cell also contains the three additional property definitions:
L = 0.5u
NW = 4.0u
PW = 8.0u
These parameters define properties of all n-channel and p-channel MOSFETS within the subcircuit
such that L represents the length property of both n- and p-channel MOSFETS, NW represents n-
channel width and PW represents p-channel width.
Attaching these parameters to NAND2C allows component properties within the subcircuit
definition to be controlled in the subcircuit call.
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(2*650n+if(0,NW/1,NW)+if(0,NW/1,NW)*1+floor(1/2)*2*(750n+if(0,NW/1,N
W)*1)), floor(1/2)*2*(750n+if(0,NW/1,NW)*1))'
MM6p Outbar Out Vdd Vdd PMOS25 W=PW L=L M=2 AS='if(0,
(650n*if(0,PW/1,PW)+floor(2/2)*750n*if(0,PW/1,PW)),
(2*650n*if(0,PW/1,PW)+(floor(2/2)-1)*750n*if(0,PW/1,PW)))' PS='if(0,
(2*650n+if(0,PW/1,PW)+if(0,PW/1,PW)*1+floor(2/2)*2*(750n+if(0,PW/1,P
W)*1)), (2*2*650n+if(0,PW/1,PW)+if(0,PW/1,PW)*1+(floor(2/2)-
1)*2*(750n+if(0,PW/1,PW)*1)))' AD='if(0,
(650n*if(0,PW/1,PW)+floor(2/2)*750n*if(0,PW/1,PW)),
floor(2/2)*750n*if(0,PW/1,PW))' PD='if(0,
(2*650n+if(0,PW/1,PW)+if(0,PW/1,PW)*1+floor(2/2)*2*(750n+if(0,PW/1,P
W)*1)), floor(2/2)*2*(750n+if(0,PW/1,PW)*1))'
.ends
.end
Subcircuits are defined by blocks of device statements bracketed with the .subckt and .ends
commands, and instanced by statements beginning with the key letter X. The .subckt command
includes the name of the subcircuit being defined (NAND2C), a list of terminals, and three subcircuit
parameters. The terminals do not have a predefined order, but whatever order is used in the
definition must be used in instances. Parameters can be written in any order in both the definition
and the instances. If a parameter value is not specified in the instance the value in the definition is
used as the default.
Within the subcircuit definition, four MOSFETs are defined in the usual manner—and in these
statements the order of terminals is important: drain–gate–source–bulk. Node 1 is the source of
transistor MM2n and the drain of transistor MM1n. Subcircuit parameters, enclosed by single
quotes, are used in place of numerical values.After the subcircuit is defined, you can create an
instance of the subcircuit. The instance statement
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begins with the key letter X. The name of the instance, by which it is to be identified in the rest of
the
input file, is X1 (not "XX1.")
The list of terminals in the instance statement must have the same order as on the first line of the
subcircuit definition so that A B Out Gnd in the definition corresponds to Vin N_1 OUT Gnd in the
instance. The next argument of the instance statement is the original subcircuit name NAND.
The default subcircuit parameter values, as specified by the definition, are overridden by
instancespecific
value assignments, which can appear in any order. Any parameters omitted from the instance
statement retains its default value.
A standard DC operating point calculation (.OP) analysis is carried out on this circuit, with a duration
of
300 nanoseconds and a maximum timestep of 250 picoseconds. The .param command sets the
initial
node voltages to 3.3 volts. The .PRINT command reports simulation results for the voltages at nodes
Vin, OUT, and X1/N_1.
1.20.1.2. Output
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DesignType: Digital
Features: S-Edit
This example illustrates the use of the SPICE.OUTPUT property to output SPICE for a primitive
device. A primitive device is the lowest level device, for which there is no schematic, and the output
to SPICE is determined by the SPICE.OUTPUT property on the symbol. The symbol of cell NMOS4 (an
NMOS transistor), view NMOS4, has several properties:
AD = ${W}*1.25u*${M}
AS = ${W}*1.25u*${M}}
L = 0.25u
M=1
Model = NMOS
NRD = 0
NRS = 0
PD = 2*(${W}+1.25u)*${M}
PS = 2*(${W}+1.25u)*${M}
RDC = 0
RSC = 0
RSH = 0
W = 2.50u
A SPICE.OUTPUT property on the symbol specifies the SPICE call written for each instance of the
symbol, and a SPICE.PRIMITIVE property set to “True” on the symbol indicates that the device is a
primitive. The SPICE.OUTPUT and SPICE.PRIMITIVE properties for the symbol are as follows:
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SPICE.OUTPUT = M${Name} %{D} %{G} %{S} %{B} ${Model} W=${W} L=${L} M=${M} AS=${AS}
PS=${PS} AD=${AD} PD=${PD}
SPICE.PRIMITIVE = True
The SPICE Export Control Property to enter when exporting SPICE is the name of the property that
contains the sub properties OUTPUT and PRIMITIVE. In this case, the word “SPICE” is the Export
Control property. Inspecting the SPICE.OUTPUT statement in detail, each element of the property is
written out as follows:
The symbol of cell PMOS4, view PMOS4, has similar properties and a similar SPICE.OUTPUT property
as cell NMOS4, view NMOS4. Cell INV makes use of cells NMOS4, view NMOS4 and PMOS4, view
PMOS4. The SPICE output for the schematic of INV is as follows:
We can see the substitutions of the instance name, net names, and property values in each SPICE
call line, according to the table above.
An alternate method that may be used instead of defining one SPICE.OUTPUT property to specify
the SPICE call is to define the SPICE.PREFIX, SPICE.PINORDER, SPICE.MODEL, and SPICE.PARAMETERS
properties. These four properties when used in conjunction with each other will also specify the
SPICE call written for each instance of the symbol. An example of this is shown in symbol NMOS4,
view NMOS4_Expand. The SPICE.PREFIX, SPICE.PINORDER, SPICE.MODEL, and SPICE.PARAMETERS
properties are as follows:
SPICE.PREFIX = M
SPICE.PINORDER = D G S B
SPICE.MODEL = $Model
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SPICE.PARAMETERS = W= L= M~ AS= PS= AD= PD= NRD~ NRS~ RDC~ RSC~ RSH~
The output of SPICE.PREFIX will be followed by the SPICE.PINORDER statement, the SPICE.PINORDER
property is written out as follows:
The output of SPICE.PINORDER will be followed by the SPICE.MODEL statement, the SPICE.MODEL
property is written out as follows:
W= Write “W=” literally followed by the value of the property “W” on this instance
L= Write “L=” literally followed by the value of the property “L” on this instance
M~ Write “M=” literally followed by the value of the property “M” on this instance
only if the value of M differs from its default value
AS= Write “AS=” literally followed by the value of the property “AS” on this
instance
PS= Write “PS=” literally followed by the value of the property “PS” on this
instance
AD= Write “AD=” literally followed by the value of the property “AD” on this
instance
PD= Write “PD=” literally followed by the value of the property “PD” on this
instance
NRD~ Write “NRD=” literally followed by the value of the property “NRD” on this
instance only if the value of NRD differs from its default value
NRS~ Write “NRS=” literally followed by the value of the property “NRS” on this
instance only if the value of NRS differs from its default value
RDC~ Write “RDC=” literally followed by the value of the property “RDC” on this
instance only if the value of RDC differs from its default value
RSC~ Write “RSC=” literally followed by the value of the property “RSC” on this
instance only if the value of RSC differs from its default value
RSH~ Write “RSH=” literally followed by the value of the property “RSH” on this
instance only if the value of RSH differs from its default value
This example illustrates how parameters can be passed down the hierarchy and written to SPICE.
Cell Top_Inverters contains three instances of cell INV. The symbol for INV contains a property:
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match=0
The first instance has no local override of match; the second instance has a local override:
match=1
match=2
This example illustrates how to use the SPICE.OUTPUT and SPICE.DEFINITION properties to control
the SPICE output written for a subcircuit. A subcircuit is a symbol that is not a primitive. The symbol
for cell Dig0 has no SPICE.OUTPUT or SPICE.DEFINITION properties. When no SPICE.DEFINITION
property is present, the subcircuit definition will contain all pins listed in alphabetical order, with
global ports listed last, also in alphabetical order. When no SPICE.OUTPUT property is present (nor
the SPICE.PREFIX, SPICE.PINORDER, SPICE.MODEL, or SPICE.PARAMETERS properties), the SPICE
written, corresponding to each symbol instance, will contain all pins followed by all interface
parameters. An interface parameter is a parameter with sub-property:
IsInterface = True
Exporting SPICE for cell Top_Subcircuits, we see the definition and call for Dig0 appears as follows:
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Now consider cell Dig1. Cell Dig1 demonstrates the use of the SPICE.DEFINITION property to pass
parameters to the definition of a subcircuit. The symbol for cell Dig1 has a SPICE.DEFINITION
property as follows:
Inspecting the SPICE.DEFINITION statement in detail, each element of the property is written out on
the SPICE definition interface as follows:
Exporting the SPICE for cell Top_Subcircuits, we see the definition and call for Dig1 appears as
follows:
Now consider cell Dig2. Cell Dig2 demonstrates the use of the SPICE.OUTPUT and SPICE.DEFINITION
properties to customize the pin order and to add special syntax to the definition and call for a
subcircuit. The symbol for cell Dig2 has a SPICE.DEFINITION and SPICE.OUTPUT property as follows:
Inspecting the SPICE.DEFINITION statement in detail, each element of the property is written out on
the SPICE definition interface as follows:
Inspecting the SPICE.OUTOUT statement in detail, each element is similarly constructed. Exporting
the SPICE for cell Top_Subcircuits, we see the definition and call for Dig2 appears as follows:
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This example illustrates the use of the SPICE Export Control Property to control the SPICE output for
a device. For a given device, one may want to define several SPICE output properties, for example a
default property, a basic property, and a detailed property. Each property might have different
parameters for different levels of simulation. The SPICE Export Control property determines which
output property is used when writing out a SPICE netlist. When a list of property names is entered in
the Export Control Property, SPICE will be written according to the first Export Control Property in
the list that exists on the device being written. The Export Control Property can be set in the File >
Export > Export SPICE… Property Name field or in the Setup > SPICE Simulation… Netlisting
Options SPICE Export Control Property field.
Consider cell PMOS4 (a PMOS transistor), view PMOS4. Three SPICE.OUTPUT properties are
defined, as shown below. The SPICE Export Control Properties for these Output properties are
SPICE_BASIC, SPICE, and SPICE_DETAILED.
SPICE.OUTPUT = M${Name} %{D} %{G} %{S} %{B} ${Model} W=${W} L=${L} M=${M} AS=${AS}
PS=${PS} AD=${AD} PD=${PD}
SPICE_DETAILED.OUTPUT = M${Name} %{D} %{G} %{S} %{B} ${Model} W=${W} L=${L} M=${M}
AS=${AS} PS=${PS} AD=${AD} PD=${PD} NRD=${NRD} NRS=${NRS} RDC=${RDC} RSC=${RSC}
RSH=${RSH}
If we export SPICE from cell INV, and enter SPICE_DETAILED, SPICE, SPICE_BASIC for the SPICE
Control Property, we get the following output:
The SPICE_DETAILED.OUTPUT property was used to export the PMOS4 instance because it was first
in the SPICE Control Property list and it existed on the PMOS4 instance. No SPICE_DETAILED.OUTPUT
property exists on the NMOS4 instance, so the next property in the list was used, which is the
SPICE.OUTPUT property.
If we export SPICE from cell INV, and enter SPICE_BASIC, SPICE for the SPICE Control Property, we
get the following output:
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The SPICE_BASIC.OUTPUT property was used to export the PMOS4 instance because it was first in
the SPICE Control Property list and was present on the PMOS4 instance. No SPICE_BASIC.OUTPUT
property exists on the NMOS4 instance, so the next property in the list was used, which is the
SPICE.OUTPUT property.
If we export SPICE from Cell INV and enter only SPICE for the SPICE Control Property, we get the
following output:
The SPICE.OUTPUT property was used for both the PMOS4 and NMOS4 instances.
Section 2 Process
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This sample TCL script illustrates how to cycle over all schematic views in the design, and change all
ports and netlabels called “vdd” to “VDD”.
After loading the script, there are two functions:
fix_vdd_names: Renames ports and net labels in the current cell from “vdd”
to “VDD”
ForEachSchematicView Iterates through all schematic views in the database, calling
“fix_vdd_names”
fixall: Calls “ForEachSchematicView” so that it will in-turn call
“fix_vdd_names”
To run this script, first drag and drop it into the command window, then enter fixall to run the script.
A full list of S-Edit TCL commands is available by typing help in the Command window. Help on
any specific command, as well as a list of subcommands and options, can be obtained by entering the
command name followed by -help.
This sample TCL script illustrates how to cycle through all views in a design (schematic and symbol
views) and modify the size of Ports, Netlabels, and Textlabels. It also shows how to use TK to write a
dialog to enter parameters into a script. Note the use of the toplevel command to declare a window
to write into. This is required for all TK scripts as the default toplevel window is the S-Edit
application window, which the user is not permitted to modify.
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After loading the script by dragging-and-dropping it into the command window, the following dialog
appears:
Enter appropriate text sizes, then press OK to resize Ports, Netlabels, and Textlabels in all views.
A button to run the script can be created on a toolbar by removing the comment symbol (#) from
the workspace command. Also comment out the ResizeText command so the script does not
execute immediately when it is loaded, but only when the button is pressed.
…
workspace userbutton set ResizeText
# ResizeText
The button can then be added to the toolbar by right-clicking the toolbar and selecting Customize…,
selecting the Commands tab and then the category Custom. Drag the command Execute button
text as Tcl to the location the button should appear on the toolbar. Right-Click the new button and
change the name to ResizeText. To use the button the TCL script must first be loaded by dragging-
and-dropping it into the command window.
If this is a commonly used script, it can be placed in the scripts\startup folder to automatically load
when S-Edit starts up. The location of the startup folder is:
Scripts can also be loaded automatically whenever a design is opened, or when S-Edit is shutdown.
The location of the folders for these scripts is:
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Diode_DLL.sp Description
Diode_Interpreted.sp Description
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mos1.c Description
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resistor.c Description
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