Continuous Modeling of Open-Loop Control Based Negative Sequence

Current Control of Modular Multilevel Converters for HVDC Transmission

Noman Ahmed, Lennart Ängquist, Hans–Peter Nee

Department of Electrical Energy Conversion
School of Electrical Engineering
KTH Royal Institute of Technology
Stockholm, Sweden

noman.ahmed@ee.kth.se, lennart.angquist@ee.kth.se, hansi@kth.se

Keywords
«Modeling», «Multilevel converters», «Power transmission», «Fault handling strategy», « HVDC »

Abstract
Negative sequence currents are obtained during ac-side asymmetrical faults of converters in high-
voltage direct current (HVDC) transmission systems. Consequently, second order harmonics in the dc-
side voltage and current, unbalanced ac-side currents, and power oscillations can be observed. This
paper presents a negative sequence current control (NSCC) scheme that eliminates second order
harmonic ripples in the voltage and current of the dc-side during unbalanced grid conditions.
Controllers for this purpose are investigated using a continuous model of the modular multilevel
converter (M2C). The proposed scheme utilizes an open-loop controller for lower level control of the
M2C. The continuous model used also has the capability to model blocking and deblocking events
which may be used during protective actions. Simulation results reveal that the proposed NSCC
scheme is effective in suppressing dc-side voltage and current ripples. Moreover, it keeps the ac-side
phase currents balanced during asymmetrical fault
conditions. idc
iUa iUb iUc

Introduction ucap C
uUa uUb uUc
The modular multilevel converter (M2C) is
considered to be a strong converter candidate for
high-voltage direct current (HVDC) transmission R V R V R V
systems. As compared to conventional two-level or
three-level voltage source converters (VSCs), M2C L V L V L V
iVa
offers advantages such as high scalability, low u
iVb Va
switching losses, better output voltage waveform u u
dc iVc Vb
uVc
and no requirement for a common dc-link capacitor
L L L
[1]–[3]. V V V

The three-phase M2C has three phase legs, each R V

R V R V

consisting of an upper and a lower arm, constituted

by a number of series-connected submodules. Each
submodule contains two insulated gate bipolar uLa uLb uLc
transistors (IGBTs) with antiparallel diodes, and a
dc storage capacitor. The number of submodules
iLa iLb iLc
can be adjusted to get the desired output voltage.
Fig. 1 shows the basic circuit configuration of a
three-phase M2C. Fig. 1: Circuit configuration of a three phase M2C.
Detailed simulation models of M2C need to represent hundreds or even thousands of semiconductor
switches. Besides, a high number of levels requires a large number of switching operations; which
essentially need high computational time. To overcome this, simplified or continuous models, which
provide similar dynamic behavior from a system perspective as the detailed models, must be
developed. Several simplified simulation models of M2Cs have been proposed in the literature [4]–
[6]. Recently, a continuous model of the M2C for power system simulation has been proposed [7]. The
model also has the blocking/deblocking feature of the M2C, which can be used during start-up and
protective actions. For M2C lower-level control, the proposed model uses open-loop control using
estimation of stored energies, which utilizes the measured output currents to estimate the total
capacitor voltage [8]. In [9] it is evaluated that the open-loop control provides the fastest arm voltage
response and dynamic performance. It is also found to be less complicated to implement than other
control methods proposed for the M2C.
Negative sequence currents are obtained during ac-side asymmetrical faults of converters in HVDC
transmission systems. As a consequence, second order harmonics in the dc-side voltage and current,
large and unbalanced ac-side currents, and power oscillations can be observed. Therefore, it is
necessary to control this negative sequence current during unbalanced grid conditions. Several
schemes to control negative sequence current based on closed-loop control of M2C are proposed in the
literature [10]–[12]. This paper presents a negative sequence current control (NSCC) scheme based on
open-loop control of M2C, to eliminate second order harmonic ripples in the dc-side voltage and
current during unbalanced grid conditions. Controllers for this purpose are investigated using the
continuous model of the M2C proposed in [7]. Simulations performed in PSCAD demonstrate the
effectiveness of the proposed scheme in suppressing ripples in the dc-side voltage and current.
Moreover, it is capable of maintaining balanced ac-side currents during unbalanced grid conditions.
The blocking/deblocking capability for fast over-current protection during transient conditions is also
studied.

Continuous model
The open-loop controller for the M2C provides six insertion indices (narm) governing each arm in the
converter. These are defined as the instantaneous ratio between the number of inserted submodules
and the total number of submodules in the arm. The inserted voltage in an arm depends on the arm
insertion index, which controls the “instantaneous” (averaged) portion of inserted submodules in the
respective arm. The insertion indices are calculated based on the ratio between the desired arm voltage
and the total capacitor voltage (sum of all capacitor voltages) in the arm. Control of the total capacitor
voltage and its uniform distribution among the submodules in an arm is extremely important and quite
challenging as well. Thus, detailed modeling of the operation of the M2C is quite complex and
requires representation of all the individual submodule capacitor voltages. Therefore, in a simulation
program, a large number of nodes are required and the model will contain a high number of states. As
a consequence, the simulation becomes time-consuming and produces a vast amount of output data.
A continuous model can overcome these disadvantages. The continuous model is characterized by the
arm inductance, the arm resistance and the resulting capacitance of all submodules when connected in
series. The inserted voltage from an arm depends on the respective insertion index, which is assumed
to be a continuous variable, varying between zero and one. The capacitor current, and the voltage
inserted by an arm at a certain instant can be expressed as
icap = narmiarm (1)
Σ
uarm = narmucap (2)
Σ
where ucap is the total available capacitor voltage of the arm and is given by
t
N
C t∫o
Σ
ucap = icap dt (3)

where C is the cell capacitance and N is the number of submodules per arm.
Assuming even voltage distribution within each
arm, the state of the M2C can then be described iarm
in terms of the total capacitor voltage in each Σ
ucap
narm icap N
arm. This greatly reduces the complexity even if C
∫ uarm
large numbers of submodules are modeled. The
model has a capability to represent any number
of levels. A schematic diagram of the proposed M2C Arm Module

continuous model of an M2C arm module is Fig. 2: Schematic diagram of the proposed continuous
shown in Fig. 2. model of an arm module.
The novelty of the proposed model is the
implementation of the blocking capability of an arm, which gives an edge to this model over other
simplified models. This feature is helpful to study the protective measures during unbalanced grid
conditions. Here blocking refers to a state when both switches in the half-bridge are OFF
simultaneously. Fig. 3 shows the implementation of the blocking capability in the arm, and also the
flow of current during the blocked mode. The switch shown in the figure is open when the arm is
blocked. When the switch is open the “Blk/Dblk” signal forces the insertion index to 1. During the
blocked mode, the charging current can pass through the submodule capacitor chain, while the
discharging current commutates to the bypass diode. When the switch is closed during the deblocked
mode, the discharging current can pass through the submodule capacitor chain.

(a) (b)

Fig. 3: Implementation of the blocking capability in the arm module and flow of (a) Charging current (b)
Discharging current through the arm.

HVDC system based on the continuous M2C model

System configuration
A point-to-point HVDC transmission system using the continuous M2C model is shown in Fig. 4. The
pole-to-pole dc link voltage is 640 kV. Both M2Cs are rated 1000 MVA, and use open-loop control
for lower level control. The ac networks have 400 kV rms line-to-line (L-L) voltage, and are
connected to the converters through 400/400 kV transformers. M2C 1 operates as a rectifier feeding
power to the dc link, while M2C 2 operates as an inverter and delivers active power to the ac network
2. Both M2Cs are connected to the ac networks through YnD transformers, with delta connection on
the M2C-side which inherently prevents zero sequence components in the converter phase currents.
The ac networks have a short-circuit strength of 10 GVA at the point of connection. The dc-link is
modeled using a π-link cable model.
 iV iV
uB uV uV uB
udc

narm narm
θ PLL θ PLL

meas
Qmeas uV ϕuV udc uV ϕuV Qmeas
ref ref ref
Qref iVq ref
iVd ref
udc Pref iVd iVq Qref

iVdq Pmeas iVdq i

iVabc Vabc

θ PLL θ PLL

Fig. 4: Schematic diagram of the studied HVDC system based on the continuous M2C model with control
implementation.
System control
Fig. 4 also shows the control scheme implemented at both converter stations. The control system for
each M2C consists of slower outer controllers and a fast inner current controller. The outer controllers
provide the reference currents in the dq-reference frame for the inner controller, while the inner
control provides voltage references for the open-loop controller in the dq-reference frame. The outer
controllers for M2C 1, control the direct voltage of the system as well as the reactive power to given
references, while outer controllers of M2C 2 are set to control active and reactive power. The active
power order is set to 400 MW. The reactive power controllers are set so that each M2C provides 100
Mvar reactive power.
If the ac-side currents of the M2Cs flowing towards the ac-grid are taken as positive, the basic
relationship between currents and voltages in the synchronous dq-reference frame can be expressed as

d ⎡iVd ⎤ ⎡ − R L ω ⎤ ⎡iVd ⎤ 1 ⎡uVd − uBd ⎤

⎢i ⎥ = ⎢ ⎢ ⎥+ ⎢ ⎥ (4)
dt ⎣ Vq ⎦ ⎣ −ω − R L ⎥⎦ ⎣iVq ⎦ L ⎣ uVq − uBq ⎦
where uVd, uVq and uBd, uBq are the ac-side voltages of the converter and ac-bus in the dq-reference
frame, while iVd and iVq are the converter ac-side currents in the dq-reference frame. R and L are
resistance and inductance of the converter transformer. Rearranging (4), the output voltage of the
M2C in the dq-reference frame can be obtained as follows
⎡uVd ⎤ d ⎡iVd ⎤ ⎡ R −ω L ⎤ ⎡iVd ⎤ ⎡uBd ⎤
⎢u ⎥ = L ⎢ i ⎥ + ⎢ ⎢ ⎥+⎢ ⎥ (5)
⎣ Vq ⎦ dt ⎣ Vq ⎦ ⎣ω L R ⎥⎦ ⎣ iVq ⎦ ⎣ uBq ⎦
From (5) the inner current control equations to get the positive sequence reference voltages in the dq-
reference frame are given as

uVd = u Bd − ω LiVq + k p (iVdref − iVd ) + ki ∫ (iVdref − iVd ) (6)

uVq = u Bq + ω LiVd + k p (iVqref − iVq ) + ki ∫ (iVqref − iVq ) (7)

where uVd and uVq are the reference phase voltages in the dq-reference frame, which are converted into
polar coordinates. The amplitude and phase of the reference voltage is then given to the open-loop
controller for each phase of the M2C, which generates insertion indices for each arm. The overall
control scheme is shown in Fig. 5.
 udcmeas

udcref
iVd ω LiVq
Δudc
ref Σref
ref f n udc ucap
iVd

P ref ΔP uVd
uBd uV narm
ϕuV
P meas uBq uVq
ref ref
Q ΔQ i
Vq
uBabc θ PLL iVabc
meas
Q iVq ω LiVd

Fig. 5: Block diagram of the overall control scheme.

Converter blocking during a three-phase fault

During fault conditions when the protection operates, along with other fault clearing actions the
converter is also blocked (temporarily or permanently). To demonstrate the blocking feature of the
converter, a permanent three-phase fault is applied at the ac network 1 at t = 3.0 s. The dynamic
behavior of M2C 1 is shown in Fig. 6. As shown in Fig. 6(b) M2C 1 is blocked as soon as the peak
value of the ac-side current of the converter reaches 1.5 times the current flowing previous to the fault.
The ac-side circuit breakers are opened at t = 3.05 s. Blocking of the converter before the operation of
the ac circuit breakers limits the fault current, which otherwise could reach unsafe values.

(a) (c)
400
200 P1 Q1
P,Q (MW,Mvar)

200
0
Uac (kV)

0
-200
-200
-400
-400

(b) (d)
2 700
Upper Lower
1
650
Iac (kA)

U (kV)

0
600
-1

-2 550
2.95 3 3.05 3.1 2.95 3 3.05 3.1
time (s) time (s)

Fig. 6: Dynamic response of M2C 1 when the converter is blocked during a three phase-fault (M2C 1 side). (a)
Output phase voltages. (b) Output line currents. (c) Active and reactive powers. (d) Total capacitor voltage of
upper and lower arms of phase A.

Negative sequence current control (NSCC) scheme

During ac-side asymmetrical faults, negative sequence current may flow through the converter,
making the line currents very large and unbalanced. This can also affect the capacitor voltages, and
may generate second order harmonics in the dc-side voltage and current. Therefore, it is necessary to
control this negative sequence current during unbalanced grid conditions. According to [13], under
unbalanced grid conditions the measured instantaneous ac-bus voltage (uB) in the fixed two-coordinate
system (called αβ-frame) can be expressed as

( )
*
u B(αβ ) (t ) = U Bofs + U Bpos e jθ PLL
+ U Bneg e jθ PLL
(8)
where U Bofs , U Bpos and U Bneg are complex constants or phasors that represent the offset, positive and
negative sequence component of the measured ac-bus voltage. θPLL obtained from the phase-locked
loop (PLL), represents the angle of the positive sequence voltage.
The instantaneous output voltage (uV) of the M2C in the fixed two-coordinate system can be calculated
according to

( )
*
uV(αβ ) (t ) = U Vofs + U Vpos e
jθ PLL jθ PLL
+ U Vneg e

+ (U e )
jθ PLL jθ PLL *
= U Bofs + U Bpos e neg
B
(9)

+ R ⎡ IVofs + IVpos e + ( I e ) ⎤ + L ⎡ jω I ( ) ⎤⎦
jθ PLL jθ PLL * jθ PLL jθ PLL *
neg pos
e + jω IVneg e
⎣ V
⎦ ⎣ V

where R and L are resistance and inductance of the converter transformer. Neglecting the offset
components, the positive and negative sequence components of UV are given by
U Vpos = U Bpos + ( R + jω L ) IVpos (10)

U Vneg = U Bneg + ( R + jω L ) IVneg (11)

Basically, the control is performed separately for the positive and the negative sequence components.
For this purpose a negative sequence current controller is applied to the M2C in addition to the already
discussed positive sequence current controller. Based on (5) the current and voltage relationship for
the negative sequence in the dq-reference frame can be written as
⎡uVdn ⎤ d ⎡iVdn ⎤ ⎡ R ω L ⎤ ⎡iVdn ⎤ ⎡uBdn ⎤
⎢u ⎥ = L ⎢i ⎥ + ⎢ ⎢ ⎥+⎢ ⎥ (12)
⎣ Vqn ⎦ dt ⎣ Vqn ⎦ ⎣ −ω L R ⎦⎥ ⎣iVqn ⎦ ⎣uBqn ⎦
Hence, the inner current control equations to get the negative sequence reference voltages in the dq-
reference frame are given by

uVdn = u Bdn + ω LiVqn + k pn (iVdn

ref
− iVdn ) + kin ∫ (iVdn
ref
− iVdn ) (13)

uVqn = u Bqn − ω LiVdn + k pn (iVqn

ref
− iVqn ) + kin ∫ (iVqn
ref
− iVqn ) (14)

The subscript n denotes the negative sequence. The negative sequence current references in the dq-
reference frame are set to zero. Sequence estimators are used to extract the positive and negative
sequence voltage and current responses in the dq-reference frame. The desired reference phase
voltages in the dq-reference frame for the positive and negative sequences are obtained separately
from the positive and negative inner current controllers. To get the voltage references for each phase,
the projections of the positive and negative sequence reference voltages in the dq-reference frame
2π 2π
j −j
along the directions 1, e 3
,e 3
are obtained as follows

uVda = uVdpos + uVdneg (15)

uVqa = uVqpos + uVqneg (16)

1 3
uVdb = − (uVdpos + uVdneg ) + (uVqpos − uVq
neg
) (17)
2 2

3 1
uVqb = − (uVdpos − uVdneg ) − (uVqpos + uVqneg ) (18)
2 2
 1 3
uVdc = − (uVdpos + uVdneg ) − (uVqpos − uVqneg ) (19)
2 2

3 1
uVqc = (uVdpos − uVdneg ) − (uVqpos + uVqneg ) (20)
2 2

After obtaining the projections of the reference voltages for each phase in the dq-reference frame, the
polar references for each phase are calculated as follows

uVi = (uVdi ) 2 + (uVqi )2 ⎫

⎪
u ⎬, i = a , b, c (21)
ϕuVi = tan −1 Vqi ⎪
uVdi ⎭
where uVi and φuVi represent the amplitude and phase of the reference voltages for each phase of the
M2C. Similarly the amplitude and phase of the reference currents for each phase of the M2C are
obtained. The amplitude and phase of the reference voltages and currents for each phase of the M2C
are then given to the open-loop controller. The open-loop controller estimates the desired
instantaneous inserted voltage for each arm, and based on that generates insertion indices respectively.

Simulation results
This section presents selected simulation results out of a series of tests performed on the studied
system to verify the performance of the proposed NSCC scheme.
Negative sequence voltage addition
To verify the effectiveness of the proposed NSCC scheme, 100 kV (0.25 pu) rms L-L negative
sequence voltage is added to the ac network 1 at t = 3.0 s, which was operated at 300 kV (0.75 pu) rms
L-L positive sequence voltage. Upon the addition of the negative sequence voltage, the q-component
of the reference current ( iVqref ) obtained from the reactive power controller of M2C 1 increases and
oscillates significantly. Therefore, during unbalanced grid conditions iVqref is held constant and set to its
previous value. The dynamic behavior of the studied system is shown in Fig. 7.
Fig. 7(a) shows the three-phase voltages of M2C 1. Balanced three-phase line currents of M2C 1
observed in Fig. 7(b), verify the performance of the proposed NSCC scheme. Fig. 7(c) and (d) show
that the addition of negative sequence voltage to ac network 1 has no effect on the three-phase
voltages and currents of M2C 2. It can be observed from Fig. 7(e) and (f) that upon the introduction of
the negative sequence voltage very small oscillations are produced in the dc-side voltages and currents
of both converters. However, the dc-side voltage and currents regain their normal values very quickly.
Fig. 7(g) and (h) show large second order oscillations in active and reactive powers of M2C 1, but no
oscillations are observed for M2C 2. Fig. 7(i) shows insignificant change in total capacitor voltage
ripple in the arms of M2C 1, while the ripple in total capacitor voltages in the arms of M2C 2 remain
unchanged as shown in Fig. 7(j). Fig 7(k) shows that small oscillations are produced in the circulating
currents of M2C 1 when the negative sequence voltage is added but the currents become constant
within 70 ms. Fig. 7(l) shows slight variations in the circulating currents of M2C 2 upon the addition
of the negative sequence voltage but resume their constant values very quickly. This shows the ability
of the proposed NSCC scheme to properly control circulating currents, which otherwise tend to
increase the amplitude of the capacitor voltage ripple. The constant contributions of circulating
currents show that the proposed NSCC scheme offers stability in the open-loop control. The stability
seems to be robust, so that changes of the operating conditions may appear without loss of stability.
 (a) (g)
400
500
P1 P2
200

P (MW)
Uac (kV)

0 0

-200
-500
-400

(b) (h)
2 300
Q1 Q2
1 200

Q (Mvar)
Iac (kA)

0 100

-1 0

-2 -100

(c) (i)
400 680
Upper Lower
200 660
Uac (kV)

U (kV)
0 640

-200 620

-400 600

(d) (j)
2 680
Upper Lower
1 660
Iac (kA)

U (kV)

0 640

-1 620

-2 600

(e) (k)
645
Udc1 Udc2 Phase A Phase B Phase C
-0.1
Udc (kV)

-0.2
I (kA)

640
-0.3

-0.4

635 -0.5

(f) (l)
2
Idc1 Idc2 Phase A Phase B Phase C
0.4
1
Idc (kA)

0.3
I (kA)

0
0.2
-1
0.1

-2 0
2.95 3 3.05 3.1 3.15 3.2 3.25 3.3 2.95 3 3.05 3.1 3.15 3.2 3.25 3.3
time (s) time (s)

Fig. 7: Dynamic response of the studied system when a negative sequence voltage is added to ac network 1. (a)
M2C 1 output phase voltages. (b) M2C 1 output line currents. (c) M2C 2 output phase voltages. (d) M2C 2 output
line currents. (e) M2C 1 and M2C 2 dc-side voltages. (f) M2C 1 and M2C 2 dc-side currents. (g) M2C 1 and M2C
2 active powers. (h) M2C 1 and M2C 2 reactive powers. (i) M2C 1 total capacitor voltage of upper and lower
arms of phase A. (j) M2C 2 total capacitor voltage of upper and lower arms of phase A. (k) M2C 1 circulating
currents. (l) M2C 2 circulating currents.

Single line-to-ground (SLG) fault

Fig. 8 shows the studied system response to a temporary single line-to-ground (SLG) fault, applied at t
= 3.0 s and cleared after 200 ms at the ac network 1. It is assumed that the fault is detected after 50
ms, and hence iVqref is set to the constant value that it has previous to the fault. iVqref is again obtained from
 (a) (e)
400 700
Udc1 Udc2
200
650
Uac (kV)

Udc (kV)
0
600
-200

-400 550

(b) (f)
2 2
Idc1 Idc2
1 1
Iac (kA)

Idc (kA)
0 0

-1 -1

-2 -2

(c) (g)
400
500 P1 P2
200
Uac (kV)

P (MW)
0 0

-200 -500

-400

(d) (h)
2 300
Q1 Q2
1 200
Q (Mvar)
Iac (kA)

0 100

-1 0

-2 -100
2.95 3 3.05 3.1 3.15 3.2 3.25 3.3 2.95 3 3.05 3.1 3.15 3.2 3.25 3.3
time (s) time (s)

Fig. 8: Dynamic response of the studied system under an SLG fault (M2C 1 side). (a) M2C 1 output phase
voltages. (b) M2C 1 output line currents. (c) M2C 2 output phase voltages. (d) M2C 2 output line currents. (e)
M2C 1 and M2C 2 dc-side voltages. (f) M2C 1 and M2C 2 dc-side currents. (g) M2C 1 and M2C 2 active
powers. (h) M2C 1 and M2C 2 reactive powers.

(a)
the reactive power controller after 50 ms of 700
Upper Lower
removal of the fault. The dynamic behavior of 650
U (kV)

the studied system is shown in Fig. 8.

600
Fig. 8(a) and (b) show the three- phase output
voltages and currents of M2C 1. It can be 550

observed that although the line currents are

(b)
increased during the fault, the NSCC scheme is 700

successful in keeping balanced line currents. Fig. Upper Lower

650
8(c) and (d) show that the three-phase voltages
U (kV)

and currents of M2C 2 remain unaffected during 600

the fault. Although the dc-side voltages of M2C

1 and M2C 2 drop by 9% during the fault, no 550
2.95 3 3.05 3.1 3.15 3.2 3.25 3.3
time (s)
second harmonic ripple is observed as shown in
Fig. 8(e). Very small oscillations in the dc-side Fig. 9: Dynamic response of the system under an SLG
currents of both converters can be seen in Fig. fault (M2C 1 side). (a) M2C 1 total capacitor voltage of
8(f) during the fault but no second order upper and lower arms of phase A. (b) M2C 2 total
harmonics are observed. In Fig. 8(g) and (h), capacitor voltage of upper and lower arms of phase A.
effects of the negative sequence current can be
observed in the active and reactive powers of
M2C 1, where second order harmonic oscillations can be seen during the fault. No oscillations are
observed in the active and reactive powers of M2C 2. Fig. 9(a) shows that the total capacitor voltages
of M2C 1 decrease during the fault, and the voltage ripple is increased from 6% to 11%. For M2C 2
the total capacitor voltages also decrease but the voltage ripple remains the same as shown in Fig.
9(b). Hence, no severe impact is observed in the total capacitor voltages.

Conclusion
An open-loop control based negative sequence current control scheme for modular multilevel
converters in HVDC systems is proposed. The control method has been evaluated using a continuous
model of the M2C. Simulation results reveal that the proposed scheme is effective in suppressing the
dc-side voltage and current ripples under unbalanced grid conditions. Additionally, it keeps the ac-side
phase currents balanced during asymmetrical fault conditions. The proposed negative sequence current
control scheme was capable of keeping the open-loop control in stable operation both with the
presence of a large negative sequence grid voltage and during a single line-to-ground fault. The
stability seems to be robust, so that changes of the operating conditions may appear without loss of
stability. It is shown that the blocking capability of the continuous M2C model can be used to
demonstrate fast over-current protection during fault conditions.

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