EXPERIMENT:1

TIME DIVISION MULTIPLEXING

AIM:
1. Study of 4 channel analog Multiplexing and Demultiplexing technique.
2. Study of effect of sampling frequency variation on the output.
3. Study of input signal amplitude and variation of duty cycle on the output.
EQUIPMENT:

1. Time Division Multiplexing and Demultiplexing Trainer kit.

2. Oscilloscope-30MHz dual channel.
3. Patch chords.
4. Power supply.
THEORY:

The TDM is used for transmitting several analog message signals over a
communication channel by dividing the time frame into slots, one slot for each message signal.
The four input signals, all band limited by the input filters are sequentially sampled, the output of
which is a PAM waveform containing samples of the input signals periodically interlaced in
time. The samples from adjacent input message channels are separated by Ts/M, where M is
number of input channels. A set of M pulses consisting of one sample from each of the input M-
input channels is called a frame.

At the receiver the sample from individual channels are separated by carefully
synchronizing and is critical part of TDM. The samples from each channel are filtered to
reproduce the original message signal. There are two levels of synchronization. Frame
synchronization is necessary to establish when each group of samples begin and word
synchronization is necessary to properly separate samples within each frame. Besides the space
diversity & frequency diversity there is a method of sending multiple analog signals on a channel
using “TIME DIVISION MULTIPLEXING & DEMULTIPLEXING” technique.
CIRCUIT DESCRIPTION:

Function Generator:
A 4.096 MHz clock is used to derive the modulating signal, which is generated by an
comprising circuit a 4.096MHz crystal and three 74HC04 (U4) inverter gates. This 4.096MHz
clock is then divided down in frequency by a factor 4096, by binary counter 74HC4040(U3), to
produce 50% duty cycle, 64 KHz square wave on pin no.1 of U4,and 32 kHz square wave on pin
no.4.32KHz square wave is given to pin no.2 of IC NE555(U7) which act as a monostable
multivibrator. Potentiometer P5 adjust the pulse width.64KHz square wave is fed to the four bit
binary counter(U4 first half of 74HC393) on pin no.1 to produce 4KHz square wave at pin no.6.
This signal goes to pin no.13. This signal clocks to the second half of the counter to produce
square wave at following frequencies.
Counter output frequency
2QD 250Hz
2QC 500Hz
2QB 1KHz
2QA 2KHz
Each of these square wave outputs is then fed to its own low pass filter circuits
TL072 (U8,U9). Which generators corresponding sine wave outputs. The amplitude of this sine
wave can be varied by potentiometers P1,P2,P3,P4 respectively. These sine wave outputs are
available at TP1(250Hz),TP2(500Hz),TP3(1KHz),TP4(2KHz) respectively and have amplitudes
upto 10V max.( variable amplitudes)
Transmitter:

Each modulating signal is applied to IC TL074(U6) (pin nos. 3,5,10,12 respectively).

This IC buffers the applied signal and is fed to pin nos.3,14,11,6 respectively of IC DG211(U5).
The pulse input (32KHz(clock)) is applied to pin nos. 1,16,9,8 of U5. Corresponding PAM
outputs are available at test points TP5,TP6,TP7,TP8 respectively. These each PAM outputs are
applied to IC 4052(U1) which act as multiplexer.

4 Channel multiplexer:
 CD4052 is a channel analog multiplexer which can accept analog signal in the range
from 0 to +/- 5V p-p. The channel selection is done by the signals A&B. these outputs are
available at TP10, TP11( 4 to1) decoder decodes these two signals and controls the switch
position. The common output (TDM analog output) is available at pin 13 of IC U1 and at TP9.

4 Channel demultiplexer:

The multiplexed PAM signal is given to the 4 channel Demultiplexer input at pin
3(TP12). The A&B timing wave forms selects the channel and accordingly connects the same to
the output. This at the PAM signal of each channel is separated. These separated demultiplexed
outputs are monitored at test points 13, 14, 15, 16 respectively.

Low pass filter:

Each separated PAM outputs are being connected to corresponding channel‟s butter
worth Low Pass Filter. This is 4th order filter having roll of rate of 24 dB/octave(40dB/decade)
and cut-off frequency of 250Hz, 500Hz, 1KHz, 2KHz respectively. The output of these filters
goes to corresponding sockets termed as CH1, CH2, CH3, CH4. The reconstructed signal can be
monitored at test points 17, 18, 19, 20 respectively. These outputs are at lower amplitude.

MODEL GRAPHS:Draw on your own

PROCEDURE:

Multiplexing:

1. Connect the circuit as shown in diagram.

2. Switch ON the power supply.
3. Set the amplitude of each modulating signal as 5Vp-p.
4. Monitor the outputs at test points 5, 6, 7, 8. These are natural sampling PAM outputs.
5. Observe the outputs by varying the duty cycle pot(P5). The PAM outputs will varying
with 10% to 50% duty cycle.
6. Try varying the amplitude of modulating signal corresponding each channel by using
amplitude pots P1, P2, P3, P4. Observe the effect on all outputs.
 7. Observe the TDM output at pin no. 13(at TP9) of 4052. All the multiplexer channels are
observed during the full period of the clock (1/32 KHz).

Demultiplexing & low pass filter:

1. Connect the circuit as shown in diagram.

2. Observe the demultiplexed outputs at test points 13, 14, 15, 16 respectively.
3. Observe the effect on the outputs by varying the duty cycle pot P5.
4. Observe the low pass filter outputs for each channel at test points 17, 18, 19, 20 and at
sockets channels CH1, CH2, CH3, CH4. These signals are true replica of the inputs.
These signals have lower amplitude.

OBSERVATIONS:

S NO Amplitude(Vp-p) Frequency Time Period

Message signals:
CH1 3.8V 250Hz 4msec
CH2 4.0V 500Hz 2msec
CH3 4.4V 1KHz 1msec
CH4 4.0V 2 KHz 5msec
TDM signal 6.96V 32KHz; 0.31µsec
Demultiplexed signal
CH1 1.9V 250Hz 4msec
CH2 2V 500Hz 2msec
CH3 2.1V 1KHz 1msec
CH4 2.4V 2 KHz 5msec

PRECAUTIONS:

1. Connect power supply with proper polarity.

2. Do not make any interconnections when power supply is ON.

RESULT:
 1. The 4 channel analog Multiplexing and Demultiplexing techniques are observed.
2. If sampling frequency is increased the can be signal reconstructed close to input.
3. There is no effect of input signal amplitude variation on the output and variation of duty
cycle distorts the output.
EXperiMENT2
PULSE CODE MODULATION AND DEMODULATION

AIM:-

1.To study the Pulse Code Modulation and Demodulation.

2.To study the effect of A-law PCM and Linear modulation by varying the input
signal amplitude.

3.To study the variation of sampling frequency on the demodulation output signal
and to prove the Nyquist sampling theorem.

4.Observing Quantizing noise at demodulation output for 1KHz sine wave input
according to A-law and linear by varying input signal amplitude.

EQUIPMENT REQUIRED:-

1.Hi-Q ELECTRONICS PCM Modulation &Demodulation Trainer kit.

2.Hi-Q ELECTRONICS 1MHz Function generator

3. 30 MHz Dual Channel CRO.

4.Two Telephone Instruments.

5.4 mm patch cords.

CIRCUIT DESCRIPTION

MODULATION:-

Low pass filter:-

This LPF is used for band limiting the input message signal to satisfy the
nyquist theorem.The cut of frequency of LPF is 3.4 KHz.TL074 IC is used as LPF.

Level shifter:-
 This shifts up the input message to +2.5V ,because we have used single
polarity ADC IC . Given input signal that is centered around zero. ADC supply is 0-
5V so input of ADC should not be more than these ranges.

Sampler and A/D Quantizer:-

This converts input analog signal into digital quantized levels.For this
process 14 bit serial ADC IC used.

Timing logic:-

This produces clock pulses for sampler depending upon sampling rate
switch ,i.e. 4KHz and 8KHz.

Serial to parallel converter:-

It converts serial data of ADC output into parallel data for encoding the
quantised levels.

Encoder:-

It encodes the parallel quantised levels into coded output according the
switch i.e. A-law or linear. If linear is selected it reduce the 13 bit quantised levels
into 8 levels. If A-law is selected it encode 13 bit input into 8-bit compressed PCM
output using lookup table. For this process microcontroller is used.

Output LED's:-

These LED's are for indicating data which is transmitting to decoder.

This data should be considered like as indicated on the panel.If switch is in A-law
position then bit pattern is MSB is sign bit next 3 bits for chord and next 4 bits for
step size. If switch is in linear position there is no bit pattern only MSB and
LSB.Test points are provided for watching data in CRO for high frequency inputs.

DEMODULATION:-

Decoder:-
 It decodes 8-bit compressed A-law PCM output into 13-bit digital data.
For this purpose microcontroller is used.
Parallel to Serial Converter:-

In demodulation 13-bit serial DAC has used, so parallel to serial

converter converts parallel data into serial then sends to DAC.

Digital to Analog Converter:-

It converts digital data into analog output.It is serial DAC supply this is 0-
5V. It is interfaced with microcontroller with three wires. One is serial data,
second one is clock and third one is chip select

Low Pass Filter:-

DAC output is in type of steps. LPF is shaped neatly that output is

demodulated output.

Level Shifter:-

In modulation input signal shift up by 2.5V,here that signal shifts down

by -2.5V.

Quantization noise:-

1KHz notch filter is used for watching quantizing noise for 1KHz sine
input at modulator. This noise is for 1KHz input only.

Internal inputs:-

1KHz sine wave :-At TP1 1KHz sine wave is internally generated. Its
amplitude can vary by POT P1.

Variable DC:- At TP2-2.5V to +2.5V DC available.

External Inputs:-

There is a provision to give external input signal from Function

Generator maximum amplitude 5Vp-p and maximum frequency 3.4KHz at TP4.
Another sorce for voice signal through telephone. For this purpose there is a
provision for telephone a TP5.

EXPERIMENTAL PROCEDURE:-

1.To study the Pulse Code Modulation and Demodulation:

1.Switch on power supply.

2.Connect the CRO probe at TP2 and set CRO in DC mode then vary the pot P2,
observe the variable DC voltage (-2.5V to +2.5V).

3.Observe the DC voltage at TP7, it is 2.5V. This is origin for ADC (single supply).
Any input signal applied at MOD. Input shifted to this voltage level. This voltage is
indicating on output LED's when no ipnut is applied.

4.Connect the patch cord from TP2 to MOD Input. Observe the level shifter
output at TP7 which is shifted by +2.5V.

5.Keep pot P2 -2.5V side (fully anti clockwise),now observe all LED's OFF.Now turn
P2 slowly clock wise and Observe LED's glowing.Observe the serial data at TP9.

6.Connect CRO channel 1 probe at TP2 and channel2 probe at Demod. Output
TP21. Vary pot P2,observe that same DCvoltage should appear at two points.

7.Keep some DC voltage,select one type of Encoding method by selecting toggle

switch(A-law or Linear) then observe LED's. Now change the switch position by
toggle and observe LED's.Identify the bit pattern between A-law and Linear
modulation.

8.Remove DC from input and connect 1KHz sine wave at Tp1.

9.Observe sampling rate clock at TP8 by changing sampling rate by toggle switch
(4KHz and 8KHz).

10.Observe LPF output at TP6,Level shifter output at TP7.

11.Observe the Sampling clock at TP8 by changing SAMPLING RATE swich and also
observe A/D QUANTIZER output at TP9(serial data output).

12.Observe the Demod.Output at TP21.Identify the difference betweeen output

waveforms when sampling frequency is 4 KHz and 8 KHz.

13.By changing Amplitude of sine wave observe Demod outputs.

2.To study the effect of A-law in PCM:

1.Connect Mod.Input from external input at TP4. Connect external sine wave
from Function generator at TP4.Maximum amplitude of this wave form is 5Vp-p.

2.connect CRO CH1 at TP4 and CH2 at TP21. Set input amplitude 200mVp-p in
function generator.Keep sampling rateswitch in 8KHz and keep encoding switch in
A-law.

3.Observe demod output at TP21. Now change encoding switch to Linear,observe

Demoid. Output at TP21. Identify difference between A-law PCM and Linear
modulation. In Linear modulation demod output is not same as input in shape. In
A-law PCM output is same as input in shape.Repeat this process for decreasing
input amplitude and varying frequency.

4. Now connect the input signal to audio input at TP5 and connect a patch cord at
TP21 to audio output. Connect two telephone sets to telephone sockets.

5.Keep encoding switch in A -law side.One person speaks at telephone audio

input and listen another person at audio telephone output. Observe clarity of
voice. Now change encoding switch to Linear side,repeat above process and
observe clarity of voice. You can observe clarity of voice is better when switch
position is in A-law.

3.Observing quantizing noise for 1KHz sine:

1.Adjust the function generator to 1KHz sine. change CRO CH2 to TP22. That is
notch filter output. Keep sampling rate switch to 8KHz.

2.Adjust the input signal amplitude to 100mVp-p,keep encoding switch to A-

law,and observe noise. Vary input signal amplitudeto 5Vp-p,observe noise.

3.Keep encoding switch to Linear and repeat above process then observe noise.

4.Observing nyquist theorem by changing sampling rate:

1.Keep sampling rate switch in 4KHz, give input signal 5Vp-p 1Hz to 1KHz.Observe
Demod output at TP21.

2.Change sampling rate to 8KHz then repeat above step observe demod output at
TP21.Identify difference between two cases.

DC&AC INPUT
Frequency i/p Linear PCM
4 KHZ 0 01001101 01110011
0.2 01111111 01111111
0.4 01111111 01111111
0.6 01111111 01111111
0.8 11111111 01111111
1 11111111 11111111
8KHZ 0 01001101 01110011
0.2 01001101 01111010
0.4 01001111 01111111
0.8 01111111 01111111
1 11111111 11111111
Frequency i/p o/p Linear PCM
4 KHz -2.5 -2.59 00000000 00000000
-1.5 -2.59 00000001 00010000
-1.08 -2.14 00010101 01010110
-0.5 -1.57 00110011 01101001
1.5 0.66 10011111 11011111
2.5 1.66 11010001 11110100
8 KHz -2.5 -2.59 00000000 00000000
-1 -2.1 01001011 01011010
1 0.12 10010001 10110010
1.5 0.64 10011110 11100110
2.5 1.67 11010000 11110100
EXP-3 DIFFERENTIAL PULSE CODE MODULATION
AIM:
To Study differential pulse code modulation & demodulation technique.
EQUIPMENT REQUIRED:
1. Differential pulse code modulation trainer kit (FALCON ADCL-07)
2. Connecting chords.
3. Power supply.
4.20MHz Dual Trace Oscilloscope
THEORY:
DPCM is a good way to reduce the bit rate for voice transmission .However it causes some other
problems that deals with voice quality .DPCM quantizes and encodes the difference between a
previous sample input signal and a sample input signal .DPCM quantizes the difference signal
using uniform quantization. uniform quantization generates an SNR that is small for small input
sample signals and large for large input sample signals .Therefore, the voice quality is better at
higher signals.
CIRCUIT DESCRIPTION:
DPCM MODULATOR
Clock Generator
The crystal oscillator generates a 2.048MHz clock.1.024MHz clock is generated by dividing the
2.048MHz clock. 512KHz,256KHz,128KHz and 64KHz clocks are generated using
U(74HCT393) a 4-bit binary counter.
Timing Logic
This logic generates the various timing signals for the transmitter. The operation of ADC673 is
controlled by two inputs: CONVERT and/DATA ENABLE. The transmited clock is fed to a 4-
bit binary counter(IC74LS393) whose output is ANDED using(IC74HC08). A pulse(plrst) is
generated which is further fed to D flipflop to generate the CONVERT pulse and the /DATA
ENABLE signal.
Sine Wave Generator
8 KHz frequency is fed to serial to parallel shift register (IC74HC164) which generates the sine
wave, by serial shift operations. The serial to parallel shift register (IC74HC164) has resistive
ladder network at the output. For 8 shifts of register, one staircase sine wave is generated. So if
8KHz clock is fed to the shift register,500Hz sine wave is generated with amplitude variable
from 0 to 4Vpp.
Sample and Hold Logic
This logic samples the information signal with the clock frequency of 16KHz,(IC4016) is used
for sampling. It is a quad bilateral switch intended for the transmission or multiplexing of analog
or digital signals.
Analog to Digital Converter
The analog to digital converter converts the analog samples to digital bits. This device performs
both the quantizing and encoding operations. The analog to digital converter IC,AD673 forms
the heart of this logic. The timing of the A/D conversion is controlled by the convert pulse,
which is generated in the timing logics. As soon as the data is ready, the AD673 gives a data
ready(DR active low) output.The data latch is used for latching the valid outputs of the A/D
converter. The timing and latching interval of the data latch is controlled by the latch enable
signal(74HCT374). Each sample is coded to a 8 bit data by AD673. These coded data is fed to a
parallel to serial shift register, which gives a serial 8-bit quantized data.
Quantising
The signal level of the input signal assumed to vary from 0 volt to 4.96 volts. The entire level is
dividing to 126 uniform steps. Each step corresponds to 4.96/128=40mv
The quantizing level is chosen to be the midway of the steps. If the signal level falls below the
quantizing level, and then the signal level is rounded off to the upper level. This type of
quantizing is called “uniform quantizing”, where the step levels are uniform. Then corresponding
to the level choosen, code words are assigned to the samples. The code words vary from
0000000 to 1111111 for the 0 to 4.96V. Thus the analog to digital converter assigns the code
MODEL WAVEFORMS:
Linear Predictor
D flip-flops (74HCT74) are used as delay elements to give two bit delays in the quantized data.
The two delayed data‟s are ORED using (IC74HC32).The ORED data is fed to the integrator
circuit, which is built around(ICTL084)
Comparator
The comparator circuit is built around (ICLM311). This circuit compares the two inputs and the
differenced output is fed to the quantizer.
DPCM DEMODULATOR
Linear Predictor
D flip-flops(74HCT74) are used as delay elements to give two bit delays.The received data and
the delayed is ORED using(74HC32).The delay element is placed in feedback loop with the OR
circuit.
Integrator
The integrator is built around (ICTL084). Integrator output is the integration of the input signal
applied.
Butterworth Filter
The butterworth low pass filter is built around (ICTL084),which filters out the sampling
frequency components from the demodulation out
PROCEDURE:
1. Connect the circuit as per the block diagram and switch settings.
2. Connect power supply in proper polarity to the kit ADCL-07 and switch it ON.
3. Keep the clock frequency at 512KHz, by changing the jumper position of JP1 in the clock
generator section.
4. Keep the amplitude of the onboard sine wave, of frequency 500Hz to 1Vpp.
DPCM modulation:
5. Connect the 500Hz sine wave to the IN post of analog buffer.
6. Connect OUT post of analog buffer to IN post of DPCM modulator section.
 7. Observe the sample output at the given test point. The input signal is sampled at clock
frequency of 16KHz.
8. Observe the linear predicted output at the PREDICTED OUT post of the linear predictor in
the DPCM modulator section.
9. Observe the differential pulse code modulated data (DPCM) at the DPCM OUT post of
DPCM modulator section.
10. Observe the DPCM data at DPCM OUT post by varying input signal from 0 to 2 volts
DPCM demodulation:
11. Connect the DPCM modulated data from the DPCM OUT post of the DPCm modulator to
the IN post of the DPCM demodulator.
12. Observe the demodulated data at the output of summation block.
13. Observe the integrated demodulated data at the DEMOD OUT post of the DPCM
demodulator.
14. Connect the demodulated data from the DEMOD OUT post of the DPCM demodulator to the
IN post of low-pass filter.
15. Observe the reconstructed signal at the OUT post of the filter .use RST switch for clear
observation of the output.
16. Now, simultaneously reduce the clock frequencies from 512KHz to 256KHz,and 128KHz by
changing the jumper position of JP1 and observe the difference in the DPCM modulated and
demodulated data. As the frequency of clock decreases, DPCM demodulated data at DEMOD
OUT becomes distorted.
17. Observe various waveforms for different frequencies.
OBSERVATIONS:
DPCM->At 64 KHZ

Parameter DATA Sinusoidal Predicted DPCM Summation Demodulated Filter

CLK output output output output output output
Time
Frequency
Vpp
V amp

PRECAUTIONS:
1) Connect the power supply with proper polarity.
2) Do not make any interconnections when the power supply is on.
3) Keep all the switch faults in off position.
.
 EXP-4 DELTA MODULATION AND DEMODULATION

AIM: To study the delta modulation and demodulation.

EQUIPMENT:

1.Hi-Q Electronics,DELTA MODULATION AND DEMODULATION

Trainer kit .

2. oscilloscope-30MHz dual channel.

3. patch chords.

THEORY:

The DM-2023 trainer can be configured to illustrate and study the techniques &
advantages of deltamodulation. The

Effect of various inputs and parameters on the particular

Modulation system can be studied by varying following parmeters.

(A) Sampling frequency

(B) Sampling step size
(C) Input amplitude

These variables help in the comparing the effect of sampling frequency ,quantization noise
, signal to noise ratios,

Frequency, slope overload , amplitude overload on various modulation systems. Various

test points at input of every block are provided for easy observation by oscilloscope.

Delta modulation is a system of digital modulation developed after pulse code

modulation . In this system , at each sampling time , say the Kth sampling time , the
difference between the sampling time K and the sample value at the previous sampling time
(K-1) is encoded into just a single bit .

Circuit description:

Oscillator circuit:
 The oscillator circuit comprising of a 4.096MHz crystal, three 74HC04 inverter
gates U1 forms the timing element of the whole system .The 4.096MHz square wave is
applied to IC U2, which is a 14 stage binary counter.

Function generator:

The higher order output IC produces square wave in the audio range and these are low
pass filtered to provide sine waves . the square wave output is 32KHz which is transmitter
clock available at TP2.

DC Supply:

The function generator block also provides a simple variable DC supply of range -5V to +5V
. The voltage can be varied by

P2,U4B(part of TL074) acts as a buffer.

D FLIP-FLOP and unipolar and bipolar converter:

This circuit latches input data and converts to a bipolar output signal for integrator
operation. Consider the circuitry around ICU5A(74HC74). The resistors R25 &R26 prevents
the data input (ID- T.P5) & clock input (clk,tp6) from floating like all other c-mos inputs on
board the input current is limited by R23 & R24 if voltage exceeds the given rating . this circuit
latches input data converts it to a bipolar output signal .

The data present at its data input is latched on rising edge of the clock and appears at data
output at tp7.

Unipolar converter:

The next stage is unipolar converter based around transistors Q1 & Q2. When the data
output is low ,Q1 is turned out via R22, and the bipolar output (t.p 8) rises. With data output
is high , Q2 is turned on via R21 and D3, and the bipolar output voltage falls .

Data i/p bipolar o/p

0 +4V
1 -4V
The collector network R15 & R18 and P3 sets the output level to +/-4v . The level adjust A
adjusts the symmetrical about 0V. the fast transistors, low value resistors & schotley diodes
ensure that thetransitions are quite fast to follow the high frequency signal input.

INTEGRATORS:-

Consider the circuitry around ICU6 (74HC4052) is dual 4 channel analog multiplexer and
ICU4A (TL074). Input op-amp ICU4A (TL074) is used as integrator.

VOLTAGE COMPARATOR:-

U7(LM311) is wired as a fast voltage comparator with hysteresis. The open-collector OUTPUT
(t.p.5) has a 1k pullup(R61) to +5V. the output is at logic „0‟ when the voltage on the (-) input
(t.p. 9) exceeds that on the (+) input (t.p.4). and logic „1‟ when the input conditions are reversed .
The input voltages range is about -11.5V to +10V. The inputs have 10K pull-down resistors R40
,R42,R43,R44 &R61. With a signal connected to the (+) input , the hystresis is about 3mV.With
no signal on the (+) input the hysteresis is about 22mV.

Low pass filter :

This is a standard fourth order low pass filter circuit with a roll off 24dB octave & cut off
frequency 3.4KHz. The resistors R48,R49 attenuate the input signal ICU8A (TL074) buffers the
attenuated input : The gain of this stage has been kept at 0.4.

ICU8B and ICU8C are wired as active low pass filters in the butterworth configuration . The
output can be examined on t.p.12. The pass band gain has been kept equal to 2.56 to prove over
all gain of unity .

Modulation :

The analog signal which is to be encoded into digital data is applied to the +V input of the
voltage comparator which compares it with the signal applied to its –Ve input from the
integrator output (more about this signal in forth coming pharagraph) .

The comparators output is logic ‟0‟ or „1‟ depending on whether the input signal at positive
terminal is lower or greater than the negative terminal input signal.

The comparator‟s output id then latched into a D flip flop which is clocked by the transmitter
clock , thus the output of D flip flop is a latched „1‟ or „0‟ synchronous with the transmitter clock
edge.
 This binary data stream is transmitted to receiver and is also fed to the unipolar – to bipolar
converter .This book converts logic „0‟ to voltage level of +4V and logic „1‟ to voltage level -4V.

The bipolar output is applied to the integrator whose output is :

1. Rising linear ramp signal when -4V is applied to it , (corresponding to binary 1 ).

2. Falling linear ramp signal when +4V is applied to it , (corresponding to binary 0 ).

The integrator output is then connected to the –ve terminal of voltage comparator , thus
completing the modulator circuit.

Let us understand the working of modulator circuit with the analog input waveform applied
as shown in figure 1.

Suppose at some time constant t=0,the integrator output voltage is lower than the analog
input. This causes the voltage comparator voltage to go high i.e. logic „1‟.This data is latched
in the f-flip flop at the rising edge of transmitter clock. The latched „1‟ output of D-flip flop
is translated to -4V by the unipolar to bipolar converter block . the integrator then ramps up
to catch analog signal.

At the next clock cycle t=1, the integrator output becomes more than the analog input . so
a‟0‟is latched into D-flip flop. The integrator now ramps downwards as +4V voltage signal
from unipolar to bipolar converters appears at its input . Thus the ramp signal again try to
catch the fallen analog signal.

As we can observe ,after several clock cycles the integrator output is approximation of the
analog input which tries to catch up the analog input at each sample time . The data stream
from D flip flop is the delta modulator output.

The delta demodulator consists of a D-flip flop a unipolar to bipolar converter followed by
an integrator and alow pass filter . The delta demodulator receives the data from D-flip flop
of delta modulator .It latches this data at every rising edge of receiver clok which is delayed
by half clock period with respect to transmitter clock. This has been done so that the data
from transmitter may settle down before being latched into the receiver flip flop .

The unipolar to bipolar converter changes the output from D-flip flop to either -4V or +4V
for logic „1‟ and „0‟ respectively.

As it has been seen in case of modulator when the output from unipolar to bipolar converter
is applied to integrator,its output tries to follow the analog signal in the ramp fashion and
hence is a good approximation of the signal itself . The integrators output contains sharp
edges which are smoothened out by the low pass filter, whose cut-off frequency is just above
the audio band .
Distortion in delta modulation occurs due to , following causes:-

As it has been seen , when the analog signal is greater then the integrator output , the
integrator ramps up to meet the analog signal. The ramping rate of integrator output , the
integrator ramps up to meet the analog signal. The ramping rate of integrator is constant .
Therefore if rate of change of analog input is faster than the ramping rate,the modulator is
unable to catch up with the information signal. This causes a large disparity between the
information signal and its quantized approximation . This error /phenomenon is known as
slope over loading and causes the lass of rapidly changing the information .

At first it may look as through the problem of slope overloading can be solved increasing
the ramping rate of the integrator. But as it can be seen from the figure the effect of the large
step size is to add large sharp edges at the integrator output and hence it add to noise
problem faced at receiver . This effect itself leads to distorted receiver output.

Increasing sampling rate cannot be the solution to the slope-overloading problem as it

determines how fast the samples are taken and not the ramping of the integrator.

(C)Another problem with delta modulation is that it is unable to pass DC information. This is
not a serious limitations of speech communication but for the systems like video (picture).
Transmission DC level does not provide information about brightness level of the picture.

The above stated limitations of the delta modulation may be traded for acceptable price in
speech application but is totally unsatisfactory for music or video signals.

Procedure:-

1. Switch ON the power supply.

2. Connect TX clock from TP2 to TX clock input TP6. The clock frequency should be
32KHz.
3. In order to ensure for correct operation of the system, we first take the input to 0V from
Dc variable at TP3.
So connect the + input of the delta modulator‟s VOLTAGE COMPARATOR to 0V.
4. Observe the output of integrator at TP9 and the output of the level change the TP8.
5. IF the transmitter‟s LEVEL CHANGER output has equal positive and negative output
levels, integrator‟s output will be a triangle wave centered around „0‟ volts , as shown in
fig 4. However, if the level changer‟s negative level is greater than the positive level, the
integrator‟s output will appear as shown in fig4 should the level changer‟s positive
output level be the greater of the two levels , the integrator‟s output will resemble that
shown in fig.4.
6. The relative amplitudes of the level changer‟s positive and negative output levels can be
varied by adjustind the LEVEL ADJUST present in the BISTABLE AND LEVEL
CHANGER CIRCUIT .
7. The output from the Transmitter‟s BISTABLE circuit (tp7) will now be a stream of
alternate „1‟ and „0‟ „s‟, this is also the output of the delta modulator itself. The delta
modulator is now said to be „balanced‟ for correct operation.
8. Disconnect the voltage comparator‟s „+‟ input from 0V, and reconnect it to the 2KHz
sine wave from TP1.
9. Observe the integrator output by varying the amplitude.
10. Observe the Bistable output together with the analog input at TP4, and note that the
2KHz sine wave has effectively been encoded into a stream of data bits at the Bistable‟s
output.
11. Connect the modulation output to the integrator input at TP10 and observe the output at
TP11.
12. Now connect TP11 to the lowpass filter input TP12 and observe the output.
13. Connect TP13 to the amplifier input TP14 and observe the demodulation output at TP15.
EXPERIMENT NO:5
FREQUENCY SHIFT KEYING
AIM:-
1. To generate FSK Modulation,
2. To Demodulate the FSK signals.

EQUIPMENT REQUIRED:-
1. FSK Modulation & Demodulation trainer kit.
2. 30 MHz dual channel storage oscilloscope.
3. Patch cords.
THEORY:-
Binary FSK is a form of constant-amplitude angle modulation and the modulating
signal is a binary pulse stream that varies between two discrete voltage levels but not
continuous changing analog signal. In FSK, the carrier amplitude(Vc) remains constant with
modulation and the carrier radian frequency(Wc) shifts by an amount equal to ±∆w/2. The
frequency shift (∆w/2) is proportional to the amplitude and polarity of the input binary signal.
For example, a binary 1 could be +1 volt and a binary zero could be -1 volt producing frequency
shifts of +∆w/2 and -∆w/2 respectively. The rate at which the carrier frequency shifts is equal to
the rate of change of the binary input signal Vm(t)(that is the input bit rate). Thus the output carrier
frequency deviates(shifts) between Wc+∆w/2 and Wc -∆w/2 at the rate equal to fm.
Data Formatting:-

A modulation code is defined as a rule by which a serial train of binary data (comprising
ones and zeroes) is converted to a signal suitable for transmission.
Non-return to zero(NRZ):-
This is a level type code and is one that is widely used in serial data transmission . A `0` is
low level and a `1` is a high level.
CIRCUIT DESCRIPTION:-
Data Clock Generator:-
The Bit clock Generator is designed around the IC 555(U1) operated in Astable mode.
The 100KΩ preset P1 in conjunction with 0.0047µf capacitor in the timing circuit
facilitates the frequency to be set and at any chosen value from 300Hz to 1KHz. This output is
available at TP1.
Data Selection:-
The 8 Bit parallel Load Serial shift IC 74165(U2) is used to generate the required
word pattern. A DIP switch (DATA SELECTION) is used to set ONE & ZERO pattern. The Bit Pattern set
by the switch is parallely loaded by controlling the logic level at pin 1(DATA ON-OFF).The last
stage output Q7 is coupled to the first stage input D0 in the Shift Register. The Serial Shift Clock is
given at Pin 2. The 8 bit data set by the switch and loaded with the register parallely is now
shifted serially right(Q0Q1,Q1Q2…) and circulated repetitively. Thus the 8 Bit Word pattern is
generated cyclically which is used as modulating signal in the FSK modulator. It is available at TP12.
NRZ(L) Output:-
The Q output(pin 2) of Flip-Flop IC U3(74HC 175) is applied to the data input ID pin
2 of flip flop IC U5(74HC74 dual D type flip flop). This flip flop clocked at its clock input 1 CLK IC
U5 pin 3 by the original DATA CLOCK signal. The device which is positive edge triggered gives the
NRZ(L) output at its 1 Q output Pin 5(TP 2) . The generation of the NRZ(L) signal is shown in
Timing Diagram each bit represented by the NRZ(L) waveform is delayed by one half cycle of
the DATA CLOCK signal, with respect to the data selection at TP 12.The output shown at TP 2.

FSK MODULATION:-

The XR-2206 can be operated with two separate timing resistors, R24 and R25,
connected to the timing pin 7&8, respectively. Depending on the polarity of the logic signal at
Pin 9, either one or the other of these timing resistors is activated. If pin 9 is open – circuited or
connected to a bias voltage ≥ 2V, only R24 is activated. Similarly, if the voltage level at Pin 9 is
≤ 1V, only R25 is activated. Thus, the output frequency can be keyed between two levels, F1 and
F2. F1 = 1/R24C9 and F2 = 1/R25C9. In our circuit R24=3.9kΩ, R25= 6.8kΩ, C9=100nF.For split-
supply operation, the keying voltage at pin 9 is referenced to V. The FSK output can be
monitored at TP 8.
MODEL WAVEFORMS:
DEMODULATION:-

Square Wave Converter:-

The incoming FSK modulated signal can be monitored at TP9. This signal is
then attenuated by resistor network R43,R44 then AC coupled via capacitor C12 to remove
any dc component in the signal. The signal is connected to SIGN Input (pin 14) of the U12
(74HC 4046 Phase comparator). The signal is first squared up by an inbuilt comparator and
is connected to one of the input of a chip 2 Input EX-OR gate. The other 5 input of the
gate is connected to the COMPIN Input (pin 3) of IC U12.The output is monitored at
TP10.
PLL Detector:-
A very useful application of the 565 PLL is as a FSK demodulator. In the 565
PLL the frequency shift is usually accomplished by driving a VCO with the binary data
signal so that the two resulting frequencies correspond to the logic 0 and logic 1states of
the binary data signal. The frequencies corresponding to logic 1 and logic 0 states are called the
mark and space frequencies.
Capacitive coupling is used at the input to remove a dc level. As the signal
appears at the input of the 565 , the loop locks to the input frequency and tracks it
between the two frequencies with a corresponding dc shift at the output. Preset P2 and
capacitor C15 determine the free-running frequency of the VCO.A three-stage RC ladder(low-
pass) filter is used to remove the carrier component from the output. The high cut off
frequency ( fH = 1/2πRC ) of the ladder filter is chosen to be approximately halfway between
the maximum keying rate and twice the input frequency. This output signal can be made logic
compatible by connecting voltage comparator (U11)(LM 311) between the output of ladder
filter and pin 6 of PLL (LM 565)(U16).

Phase Adjustment Circuit:-

U17 , U18 (NE 555) used as Phase Adjustment Circuit. The output of voltage
comparator (pin 7 of U11) is fed to pin 2 of U17 which is connected as monostable mode.
And the output of U17(pin 3) is again fed to U18(pin 2).The output is available at pin 3 of
U18 and can be monitored at TP11.This is serial data of output.

PROCEDURE:-
Modulation:-
1. Switch ON the power supply.
2. Set the Data selection switch (`DATA SELECTION`) to the desired code(say 11001100)
3. Set the switch (DATA ON-OFF) ON position. Observe the 8 Bit Word pattern at TP 12.
4. Observe the Data Clock at TP1 and also observe the NRZ (L) at TP2.
5. Connect the patch cord as per block diagram. Observe the corresponding FSK output at (when
Data is logic `1`,the frequency is high and Data is logic `0` the frequency is low)TP8.
6. Now change the Data selection and repeat the above steps 3 to 6 and observe the
corresponding FSK outputs.
7. Connect the patch cord as per block diagram. Observe the corresponding FSK output at (when
Data is logic `1`,the frequency is high and Data is logic `0` the frequency is low)TP8.
8. Now change the Data selection and repeat the above steps 3 to 6 and observe the
corresponding FSK outputs.
Demodulation:-
1. Connect the circuit according to the circuit diagram.
2. The incoming FSK input is observed at TP 9.
3. The output of `Square wave converter` is available at TP 10. The serial Data output is available at
TP11.
4. Repeat the above steps 1,2,3 for other serial data inputs and observe the corresponding
serial data outputs. These outputs are true replica of the original inputs.
OBSERVATIONS:-

Signal Amplitude Frequency

Data Clock
NRZ Data
Carrier signal
Modulated output
Demodulated Data

PRECAUTIONS:-

1. Do not make any inter connections on the board while the power supply is ON.
2. Whenever the input data is changed, Switch OFF and ON the Data Select switch.
3. Connect the power supply with proper polarity.
RESULT:-
 EXP-6 PSK MODULATION & DE-MODULATION

AIM:
To study the operation of PHASE SHIFT KEY modulation and demodulation
techniques.

EQUIPMENT:
1. Hi-Q Electronics, PSK MODULATION and DEMODULATION trainer.

2. Oscilloscope 30MHz, Dual Channel.

3. Patch Chords

THEORY:

Phase-Shift Keying (PSK):

The PSK is a form of angle modulated, constant amplitude digital modulation.
Digital communications because important with the expansion of the use of
computers and data processing and have continued to develop into a major industry
providing the interconnection of computer peripherals and transmission of data
between distant sites. Phase Shift Keying (PSK) is a relatively new system, in which
the carrier may be phase shifted by+90 degrees for a mark, and by -90 degrees for a
space. PSK has a number of similarities to FSK in many aspects, as in FSK,
frequency of the carrier is shifted according to the modulating square wave.

Circuit Description:
In this IC 8038 is a basic wave form generator which generates Sine, Square,
Triangular waveforms. The sine wave generated by this 8038 IC is used as carrier
signal to the system. This square wave is used as a clock input to a decade counter
(IC 7490) which generates the modulating data outputs.

The digital signal applied to the modulation input for PSK generation is bipolar
i.e., have equal positive and negative voltage levels. When the modulating input is
negative the output of modulator is a sine wave in phase with the carrier input.
Whereas for the positive voltage levels, the output of modulator is a sine wave which
is shifted out of phase by 180 degrees from the carrier input compared to the
differential data stream. This happens because the carrier input is now multiplied by
the negative constant level.

Thus the output changes in phase when a change in polarity of the modulating
signals results. Fig. shows the functional blocks of the PSK modulator and
demodulator.

Modulation;
IC CD 4051 is an Analog multiplexer to which carrier is applied with and without
180 degrees phase shift to the two multiplex inputs of the IC. Modulating data input
is applied to its control input. Depending upon the level of the control signal, carrier
signal applied with or without phase shift is steered to the output. The 180 degrees
phase shift to the carrier signal created by an operational amplifier using 741 IC.

Demodulation:
During the demodulation the PSK signal is converted into a+5 volts square wave
signal using a transistor and is applied to one input of an EX-OR gate. To the second
input of the gate carrier signal is applied after conversion into a +5 volts signal. So
the EX-OR gate output is equivalent to the modulating data signal.

Procedure:
1. Now switch ON the trainer and see that the supply LED glows.

2. Observe the carrier output at TP1.

3. Observe the data outputs (D1, D2, D3, and D4).

4. NOW, connect the carrier output TP1 to the carrier input of PSK modulator TP2
using patch chord

5. Connect the D1 to data input of PSK modulator TP3.

6. Observe the phase shifted PSK output waveform on C.R.O on channel 1 and
corresponding data output on channel2.

7. Connect the PSK modulation output TP6 to the PSK input of demodulation TP4.

8. Connect the carrier output TP1 to the carrier input of PSK demodulation TP5.

9. Now, observe the PSK demodulated output at TP7 on C.R.O at channel 1 and
corresponding data output on channel 2.

10. The demodulated output is true replica of data output.

EXPERIMENT:7
DIFFERNETIAL PHASE SHIFT KEYING
AIM :
To Study Carrier Modulation & Demodulation Techniques by Differential phase shift keying
(DPSK) method.
EQUIPMENT REQUIRED :
1. DPSK Trainer kit ADCL-01
2. Connecting Chords
3. Power supply
4. 20MHz Digital Storage Oscilloscope
THEORY :
In BPSK communication system, the demodulation is made by comparing the instant phase of
the BPSK signal to an absolute reference phase locally generated in the receiver. The modulation
is called in this case BPSK absolute .The greatest difficulty of these systems lies in the need to
keep the phase of the regenerated carrier always constant. This problem is solved with the PSK
differential modulation, as the information is not contained in the absolute phase of the
modulated carrier but in the phase difference between two next modulation intervals.

The block diagram shows DPSK modulation and demodulation system .The coding is obtained
by comparing the output of an EX-OR ,delay of a bit interval ,with the current data bits.As total
result of operation , the DPSK signal across the output of the modulator contains 180 deg.phase
variation at each data bit “1” .The demodulation is made by a normal BPSK demodulator,
followed by a decision device supplying a bit “1” each time there is a variation of the logic level
across its input.

The DPSK system has a clear advantage over the BPSK system in that the former avoids the
need for complicated circuitry used to gemerate a local carrier at the receiver .To see the relative
disadvantage of DPSK in comparison with PSK ,consider that during some bit interval the
received signal is so contaminated by noise that in a PSK system an error would be made in the
determination of whether the transmitted bit was a 1 or 0. In DPSKa bit determination is made
on the basis of the signal received in two successive bit intervals .Hence noise in one bit interval
may cause errors to two-bit matter of fact , there is a tendencyfor bit errors to occurs in pairs .It is
not inevitable however that error occur in pairs. Single errors are still possible.

CIRCUIT DESCRIPTION

Clock And Data Generator

This block generates data of a variable pattern depending on positions of eight bit switch SW1
also Reference clock of frequency 250 KHz (CLOCK) is generated . The crystal oscillator
generates a 2MHz clock ,from which a 250 KHz clock is recovered by using U4 (74HCT393) 4-
bit binary counter. For data generation output of SW1 is given to Parallel to serial shift register
U6(IC 74LS165).Output of shift register is taken as reference data .This reference data then
given to NRZ-L coder to generate the NRZ-L data,which is then used as basic modulating
signal for all modulation techniques.

Carrier Generator

The SIN 1 (500 KHz 0 deg.) signal is generated from U4 (74HCT393). The signal shaper
circuits and LC filters components are used to get a pure sine wave .SIN 2 (500 KHz 180
deg),which is 180 deg out of phase with SIN 1 obtained by feeding SIN 1 to inverting buffering
U3 (IC TL084) .

Carrier Modulation

The carrier modulator section consists of U17 (IC 4053) which is a dual channel analog
Multiplexer. At the output of the modulator analog buffer U3(TL084) is connected to avoid
loading.To obtain BPSK signal, SIN Carriers 1 and 2 are fed to inputs of modulator i/p 1 and
i/p2. Connect NRZ-L data to the control input C1 of the modulator.
The BPSK Modulated signal will get at the output of U3.
BPSK Demodulation Section

The PHASE DETECTION SECTION works on the principle of squaring loops. First step in
BPSK detection is the sine to square wave conversion using a Schmitt trigger U8 (IC 74HCT
14). This enables the BPSK detector to be built around digital IC‟s. The biphase splitter
basically doubles the frequency component of the modulated date and also ensures that the out
of phase component of the modulate signal does not reach the PLL. This is achieved by using
U11 (IC74LS123). The PLL recovers the carrier frequency from the output of the phase
splitter, but the frequency of the recovered carrier is twice that of the transmitted carrier. So a
D flip-flop is used as a divide by 2 counters to divide the frequency of the PLL output by 2, thus
recovering the reference carrier. The D flip-flop is used to compare the phase of the incoming
data and the reference carrier thereby recovering the data.

Delay Section

Delay section is used to delay the input data by one bit. It is done by using U16 (74HCT74).

Decoding Logic

DPSK Decoder

Since the NRZ-L data is differentially encoded before being applied to the carrier modulator at
the transmitter, it is therefore necessary to decode the data at the receiver. The DPSK decoder
consists of a decision device U 18 (74 HC85). The output of the BPSK receiver (say b (t) is
passed through the delay section U18 (74HCT74) to provide one bit delay (say (b (t-Tb)) to the
received data. This b (t) and b (t-Tb) are the inputs of the decision device. The output of the
decision device is then passed through the digital logic. The output of the digital logic is
recovered data.

PROCEDURE:
1) Carry out the connections as per the block diagram and switch settings .
2) Connect power supply in proper polarity to the kit ADCL-01 and switch it on.
3) Select Data pattern of simulated data using switch SW1.
OBSERVATIONS:

Signal Amplitude Frequency Time period

Input Data 8.2V 64KHz 15.6 µs
Differentially encoded data 10.6V 96KHz 10.4 µs
DPSK modulated output 4.2V 44.8KHz 2.23µs
Demodulated output 10.6V 96KHz 10.4 µs
4) Connect DATA generated to DATA IN of NRZ-L CODER.
5) Connect the NRZ-L DATA output to the DATA IN of the DIFFERENTIAL ENCODER.
6) Connect the clock generated SCLOCK to CLK IN of the DIFFERENTIAL ENCODER.
7) Connect differentially encode data to control input C1 of CARRIER MODULATOR.
8) Connect carrier component SIN 1 to IN 1 and SIN 2 to IN 2 of the carrier modulator logic.
9) Connect DPSK modulated signal MOD OUT to MOD IN of the BPSK Demodulator.
10) Connect output of BPSK demodulator b(t) OUT to input of DELAY SECTION b(t) IN and
one input b(t) IN of decision device.
11) Connect the output of delay section b(t-Tb) OUT to the input b(t-Tb) IN of decision
device .
12) Compare the DPSK decoded data at DATA OUT with respect to input SDATA.
13) Observe various waveforms as mentioned below (Fig.3.3), If recovered data mismatches
with respect to the transmitter data , then use RESET switch for clear observation of data output
PRECAUTIONS:-
1. Do not make any inter connections on the board while the power supply is ON.
2. Whenever the input data is changed, Switch OFF and ON the Data Select switch.
3. Connect the power supply with proper polarity.
RESULT:
The differential coding of data to be transmitted makes the bit “1”to be transformed into carrier
phase variation .In this way the receiver recognizes one bit “1” at a time which detects a phase
shift of the modulated carrier, independently from its absolute phase .In this way the BPSK
modulation, which can take to the inversion of the demodulated data, is overcome.
EXPERIMENT:8
COMPANDING
AIM:
Implementation of µ-law companding and expansion of signal.
EQUIPMENT:

DSP Processing kit.

THEORY:

The united states and Japan support m-law companding. Limiting sample values to 13 magnitude
bits, m-law compression can be defined mathematically by the following continuous equation:

F(x)=sgn(x) ln(1 + m lxl ) / ln( 1+ m ) -formula(1)

Where m is the compression parameter (m=22510 for the U.S and japan ), and x is the
normalized integer to be compressed. Following figure illustrates a piece-wise linear
approximation to this compression equation.

The least significant bits of large amplitude values are discarded during compression. The
number of deleted bits is encoded into a field of the of the encoded word, called the segment.
Each segment of this piece- wise linear approximation is equally divided into quantization levels.
The segment size between adjacent codewords is doubled for each succeeding segment.
Moreover, the most significant bit of the codeword contains the sign of the original integer. An
8-bit m-255 codeword is comprised of one sign bit, concatenated with a 3-bit segment,
concatenated with a 3- bit segment, concatenated with a 4-bit quantization value. Prior to
transmission, all the bits are inverted so a positive value will have a sign bit “1” (one). Prior to
segment determination, sign of the original integer is set aside and a bias of 33 10 is added to the
absolute value (magnitude) of the integer. The bias limits the maximum allowable input to
815910, and reduces the minimum step size to 2/815910. The bias simplifies the calculation by
making the endpoints of each segment powers of two. Locatings the segment is determined by
detecting the most significant “1” of the biased magnitude, while the quantization value is
comprised of the four bits following it. The translation from linear to m-law compression is
illustrated in following table of the compressed codeword, bits 0-3 represent the quantization and
bits 4-6 represent the segment. The sign of the compressed codeword is left out for simplicity.

The entire m-law codeword is inverted prior to transmission. The inversion is performed because
low amplitude signals occur more frequently than large amplitude signals. Consequently,
inverting the bits increases the positive pulse density on the transmission line, which improves
system performance. m-law expansion can be defined mathematically by the folloeing
continuous equation:

F-1(y) = sgn(y) (1/m) [(1+m) lyl -1] -formula(2)

Prior to expansion, the m-law codeword is inverted again during expansion, the least significant
bits discarded but are approximated by the median interval, to reduce the loss in accuracy. For
example, if five of the least significant bits of the original integer were discarded during
compression, 100002 will approximate them during expansion. The translation from m-law to
linear expansion is illustrated in following table. Again, the sign bits are left out for simplicity.
After decoding the m-law codeword, the bias is removed and the bit is applied to obtain the final
linear value.

PROCEDURE:

1. Open code composer studio, make sure that DSP kit is turned ON.
2. Load program in the following location.
PATH: DSP320PROGRAMS \ mu-law
3. Then run program from debug.

RESULT:

 Here we generated a sample 1KHz sine wave from sin function available in C.
 When you run program, it will ask to enter amplitude level. Enter amplitude level say
5V.so generated sine wave have amplitude from -5v to +5v
To view original signal
Graph settings & graph
EXPERIMENT 9:

IMAGE COMPRESSION USING HUFFMAN CODING

AIM:

Image compression using Huffman coding.

THEORY:

Huffman coding

Huffman encoding , an algorithm for the lossless compression of files based on the
frequency of occurrence of a symbol in the file that is being compressed. The Huffman
algorithm is based on statistical coding , which means that the probability of a symbol has a
direct bearing on the length of its representation .The more probable the occurrence of a symbol
is, the shorter will be its bit-size representation. In any file, certain characters are used more
than others. Using binary representation , the number of bits required to represent each
character depends upon the number of characters that have to be represented. Using one
bit we can represent two characters , i.e, 0 represents the first character and 1 represents
the second character. Using two bits we can represent four characters , and so on.

Unlike ASCII code, which is a fixed-length code using seven bits per character ,
Huffman compression is a variable-length coding system that assigns smaller codes for
most frequently used characters and larger codes for less frequently used characters in order to
reduce the size of files being compressed and transferred.

The basic idea in Huffman coding is to assign short code word to those input blocks
with high probabilities and long codeword to those with low probabilities. This concept is
similar to that of the Morse code.

A Huffman code is designed by merging together the two least probable characters,
and repeating this process until there is only one character remaining. A code tree is thus
generated and the Huffman code is obtained from the labeling of the code tree . An example
of how this is done is shown below.
Example:

 It does not matter how the characters are arranged. I have arranged it above so that
the final code tree looks nice and neat.
 It does not matter how the final code tree are labeled (with 0s and 1s). I choose to
label the upper branches with 0s and lower branches with 1s.
 There may be cases where there is a tie for the two least probable characters. In
such cases, any tie-breaking procedure is acceptable.
 Huffman codes are not unique.
 Huffman codes are optimal in the sense that no other lossless fixed-to-variable
length code has a lower average rate.
 The rate of the above code is 2.94 bits/character.
 The entropy lower bound is 2.88 bits/character.

PROCEDURE:

 Open code compressor Studio, make sure the DSP kit is turned on.
 Load program using `Fileload_program`. Which is in Program, CD-ROM at
following location.
PATH:PROGRAMS \ HUFFMAN_CODING \ Debug \ HUFFMAN_CODING.out
 Then run program from debugRun .

RESULT:

 Here we have generated pixels value from MATLAB for image of lena.
 Then we calculate frequency of same pixel value & a sine new values from 0 to
256 as per occurrence.
 To view original image
 Select Tool Image Analyzer.

After completing property go on imageright click refresh in image.

 To view compressed image

Select Tool Image Analyzer.
After completing property go on imageright click refresh.

Program:
#include<stdio.h>
#include<math.h>

#define N 64
#include "coe.h"
char image_in[N][N];
char image_out[N][N];
void main()
{

int out[N][N];
int temp[256],hist[256],a;

int i,j,count,value,b=0,k=0;
for(value=0;value<256;value++)
{
count=0;
for(i=0;i<N;i++)
{

for(j=0;j<N;j++)
{
if(in[i][j]==value)
count++;
}
}

if(count!=0)
{
temp[b]=value;
b++;
}

}
 for(k=0; k<b; k++)
{
for(i=0; i<N; i++)
{
for(j=0; j<N; j++)

{
if(temp[k]==in[i][j])
out[i][j]=k;
}
}
}

for(i=0;i<N;i++)
for(j=0;j<N;j++)
{
image in[i][j]=in[i][j];
image out[i][j]=out[i][j];
}

}
EXPERIMENT: 10
LINEAR BLOCK CODE – ENCODER AND DECODER
AIM:
To study Linear Block Code encoding and decoder .
EQUIPMENT REQUIRED:
1) Experimental kits DCL-03 & DCL-04
2) Connecting chords
3) Power supply
4)50 MHz Digital Storage Oscilloscope
THEORY:
Linear Block Coding Technique
When the data is transmitted in the channel, bit errors may be introduced by noise and other
factors existing in the channel. Error control coding techniques are used for detecting and
correcting the errors. They can be used for controlling single bit, two bit, and three bit errors.
Even Parity Codes, Odd Parity Codes, Hamming Codes are the normal error control coding
techniques, used for the detection and correction of all single bit errors that occur in the
transmission of data.
Hamming Codes
Hamming codes are the most effective single error detecting and correcting codes, used in
practice. The hamming distance for such a code is 3, ensuring an effective correction of all single
bit errors occurring in transmission:
The general format for Hamming Codes is as follows:

If N is the length of the coded sequence and n is number of error check bits

Then, N=2n –1 (Where n = 0,1,2,3)

Bit position of the check bits = 2n

The typical size of some of Hamming Code normally used in practice is given below:
Size of the coded sequence Size of Data Size of Error Check bits

7 4 3

15 11 4

31 26 5

63 57 6

Thus depending upon the size of the coded sequence, hamming parity bits are generated. At the
receiver the parity check is done and error bit is located and is corrected by bit reversal. Thus all
single bit errors occurring in data transmission can be detected and corrected by this error check
option.

The (7, 3) Hamming code, which is illustrated in “DCL - 03” and “DCL - 04” has:
Bit length of the coded sequence = 7
Number of error check bits = 3
Number of data bit = 4
In the coded sequence:
Let K1, K2, K3 be the error check bits.
L4, L5, L6, L7 be the data bits.
Now K1, K2, K3 are chosen in such a manner that
K1 - Even parity for the data bits L4, L5, and L7
K2 - Even parity for the data bits L4, L6, and L7.
K3 - Even parity for the data bits L5, L6, and L7.

The K1, K2, K3 hamming bits and L4, L5, L6, and L7 are the data bits where L7 is the most
significant data bit. Thus the coded sequence will be transmitted following format:

K1, K2, K3, L4, L5, L6, L7

L7 is shifted out first and K1 is the last.

Truth table for (7, 3) Hamming Code is given below:

Data(In decimal) Bit position

K1 K2 K3 L4 L5 L6 L7

0 0 0 0 0 0 0 0

1 1 1 0 1 0 0 0
2 1 0 1 0 1 0 0
3 0 1 1 1 1 0 0
4 0 1 1 0 0 1 0
5 1 0 1 1 0 1 0
6 1 1 0 0 1 1 0
7 0 0 0 1 1 1 0
8 1 1 1 0 0 0 1
9 0 0 1 1 0 0 1
10 0 1 0 0 1 0 1
11 1 0 0 1 1 0 1
12 1 0 0 0 0 1 1
13 0 1 0 1 0 1 1
14 0 0 1 0 1 1 1
15 1 1 1 1 1 1 1
At the Receiver to detect and correct the error occurred during transmission, EVEN Parity Check
is done at bit positions.
Let K1*, K2*, K3* be the even parity check for the following bit of the coded sequence:

K1*: Even parity check bit for K1, L4, L5, and L7 of the coded sequence

K2*: Even parity check bit for K2, L4, L6, and L7 of the coded sequence
K3*: Even parity check bit for K3, L5, L6, and L7 of the coded sequence

From the recovered K1*, K2*, and K3* the error bits are located and corrected.

Truth Table for error bit location is given below:

Error in data bit K3* K2* K1*

No error 0 0 0

Error in data bit L4 0 1 1

Error in data bit L5 1 0 1

Error in data bit L6 1 1 0

Error in data bit L7 1 1 1

Once the error bits are located the error is corrected by bit reversal.

PROCEDURE

1) Carry out the following connections as per the block diagram.

2) Connect power supply in proper polarity to the kits DCL-03 and DCL-04 and switch it on.
3) Connect DC input signal DC 1 to the input CH 0 and CH 1 of the Sample and Hold logic.
4) Set the speed selection switch SW1 to FAST mode.
5) Select parity selection switch to HAMMING mode on both the kit DCL-03 and DCL-04 as
shown in switch setting diagram (Fig. A).
6) Connect TXDATA, TXCLK and TXSYNC of the transmitter section DCL-03 to the
corresponding RXDATA, RXCLK, and RXSYNC of the receiver section DCL-04.
7) Vary the amplitude of input DC signal from 0V to 4.96V and observe the variation on LED
on the transmitter and receiver as mention below.
8) Create a single bit fault in any one of the 4 – MSB data bit by putting switch in below
position of SF 1 and observe the status of PARITY ERROR.
9) You will receive the data at the receiver side with the single bit error corrected and with the
indicator as to which of the 4 data bits had the error.
 10) This proves that Hamming Code can not only detect the single bit error but also correct the
error.

PRECAUTIONS
1) Connect the power supply with proper polarity.
2) Do not make any interconnections when the power supply is on.
3) Keep all the switch faults in of position.
RESULT

The three LSB data bit of the A/D converter output is neglected in this mode of operations and
three Hamming parity bit occupies the positions in transmission.Also four MSB bit of the D/A
converter forms the data and three LSB bit are always zero, as in that position Hamming parity
bit were transmitted. Whenever the transmission of data is error free, all the LED of Error
Detection/ Correction logic remains OFF.Whenever a single bit error occurs the corresponding
bit position is indicated by LED of Error Detection/ Correction Logic and corrected data bit are
observed at the input of D/A Converter which are same as the A/D Converter output (4MSB)
Thus in Hamming Parity mode, single bit error is detected as well as corrected.
EXPERIMENT: 11

BINARY CYCLIC CODE – ENCODER AND DECODER

AIM:

To study Cyclic Redundancy code encoding and decoding.

EQUIPMENT REQUIRED:

1) Cyclic Redundancy code encoding and decoding trainer kit.

2) 50 MHz Digital Storage Oscilloscope
3) Power supply
4) Patch cords
THEORY:
A cyclic redundancy check (CRC) or polynomial code checksum is a non-secure hash function
designed to detect accidental changes to raw computer data, and is commonly used in digital
networks and storage devices such as hard disk drives. A CRC-enabled device calculates a short,
fixed-length binary sequence, known as the CRC code or just CRC, for each block of data and
sends or stores them both together. When a block is read or received the device repeats the
calculation; if the new CRC does not match the one calculated earlier, then the block contains a
data error and the device may take corrective action such as rereading or requesting the block be
sent again.

CRCs are so called because the check (data verification) code is a redundancy (it adds zero
information) and the algorithm is based on cyclic codes. The term CRC may refer to the check
code or to the function that calculates it, which accepts data streams of any length as input but
always outputs a fixed-length code. CRCs are popular because they are simple to implement in
binary hardware, are easy to analyze mathematically, and are particularly good at detecting
common errors caused by noise in transmission channels
Operation

The theory of a CRC calculation is straight forward. The data is treated by the CRC algorithm as
a binary number. This number is divided by another binary number called the polynomial. The
rest of the division is the CRC checksum, which is appended to the transmitted message. The
receiver divides the message (including the calculated CRC), by the same polynomial the
transmitter used. If the result of this division is zero, then the transmission was successful.
However, if the result is not equal to zero, an error occurred during the transmission.
The CRC-16 polynomial is shown in Equation 1.below
P(x) = x16+x15+x2+1 -- Equation 1
Example Calculation
In this example calculation, the message is two bytes long. In general, the message can have any
length in bytes. Before we can start calculating the CRC value 1, the message has to be
augmented by n-bits, where n is the length of the polynomial. The CRC-16 polynomial has a
length of 16-bits; therefore, 16-bits have to be augmented to the original message. In this
example calculation, the polynomial has a length of 3-bits; therefore, the message has to be
extended by three zeros at the end. An example calculation for a CRC is shown below.
Calculation For Generating A CRC

Checking a Message For A CRC Error

CRC Hardware Implementation

The CRC calculation is realized with a shift register and XOR gates. Figure shows a CRC
generator for the CRC-16 polynomial. Each bit of the data is shifted into the CRC shift register
(Flip-Flops) after being XOR‟ed with the CRC‟s most significant bit.

Hardware of CRC-16 generator

PROCEDURE:

1) Do the Connections as per block diagram shown in figure.

2) Connect the power supply to the kit and switch it ON.
3) Set the data pattern as shown in block diagram using SW1.Observe the 8 bit serial data at
SERIAL DATA post.
4) Connect SERIAL DATA to DATA IN post of CRC GENERATOR.
5) Observe CRC encoded signal at DATA OUT post of CRC GENERATOR.
 6) Connect DATA OUT to DATA IN post of CRC ERROR ADDER block to introduce 2
bit manual error. Introduce error by switch SW2.
7) To decode the signal Connect DATA OUT to IN post of CRC DECODER block.
8) Observe CRC decoded and corrected signal at OUT post of CRC DECODER. Calculated
CRC at receiver end is displayed on led B1 to B4.

OBSERVATIONS:

In ADCL-08 kit the generator polynomial for CRC is X4 + X3 + 1 i. e. (11001).

Select data pattern as 11100100. Internally 4 zeros are appended after actual 8 bit data for
transmitting 4 bit CRC. Thus data will be 111001000000.
To Calculate the CRC divide the input data by generator polynomial as shown below.
11100100 0000 ÷ 11001
111001000000 | 11111
11001
0010110
11001
011110
11001
0011100
11001
0010100
11001
01101 -------- Remainder is nothing but CRC.
Thus generated CRC for the data pattern is 1101. And final transmitted data will be (Data +
CRC) 111001001101.
In receiver side the same generator polynomial is used to calculate the CRC of the received data.
If remainder is zero then received data has no error. CRC can correct single bit error.
In ADCL-08 two errors can be introduced in data at 5th and 8th position using switch SW2. at
receiver CRC is being calculated is shown below for data without any errors.
111001001101 ÷ 11001
111001001101 | 11111
11001
0010110
11001
011110
11001
0011111
11001
0011001
11001
00000 ------------ Remainder is zero indicated received data has zero Errors.
If one error is introduced to data using SW2 (left side switch) in 5th position of data then data
with error will be received at receiver side. The receiver calculates CRC using same polynomial.
If there is some remainder then using look up table the bit with error are found out and simply
invert that bit to correct the data.
Data without error at receiver = 111001001101
Data with error in 5th position = 111011001101
CRC calculation is as shown below;
111011001101 ÷ 11001
111011001101 | 11111
11001
0010010
11001
010110
11001
011111
11001
0011010
11001
000111
Remainder in this case is 111. The corresponding LED indication is observed on B2, B3, and B4
at CRC DECODER section. The value 111 corresponds to Bit position 5 in look up table and that
particular bit is inverted and corrected data at receiver is available which is 11001001101.
Similarly for another error bit which is in 8th position, the remainder will be 1001 which is
indicated on B1 and B4 at CRC DECODER section.
PRECAUTIONS:
1) Connect the power supply with proper polarity.
2) Do not make any interconnections when the power supply is on.
3) Keep all the switch faults in off position.

RESULT:
Thus we have studied cyclic redundancy code encoding and decoding of given serial data
EXPERIMENT: 12
CONVOLUTION CODE – ENCODER AND DECODER
AIM:
To Study Convolution Encoding And Hard Decision Viterbi Decoding For K= 7 And Rate =1/2.
EQUIPMENTS:
1) Convolution Encoding and Decoding Experimental Kit ADCL-06.
2) Patch Chords.
3) Power supply.
4) 16 Channel Logic Analyzer
THEORY
A convolutional code works by adding some structured redundant information to the user's data
and then correcting errors using this information. A convolutional encoder is a linear system. A
binary convolutional encoder can be represented as a shift register. The outputs of the encoder
are modulo 2 sums of the values in the certain register's cells. The input to the encoder is either
the unencoded sequence (for non-recursive codes) or the unencoded sequence added with the
values of some register's cells (for recursive codes).
The convolution encoder used in ADCL-06 supports INTELSAT standard. As per the standard
the generator polynomials
For K = 7, R = 1/2 are
G0(x) = 1+x2+x3+x5+x6 G1(x) = 1+x+x2+x3+x6

Fig (a)
BLOCK DIAGRAM:
i.e. G0(x) = 133(octal) & G1(x) = 171(octal). The implementation depicted below andis used in
conjunction with an R=1/2, K=7 Hard Decision Viterbi Decoder. The intent of this experiment is
to help clarify the terms used to define the convolutional encoding and Viterbi decoding as well
as to explain how convolutional encoding and Hard decision Viterbi decoding takes place
theoretically and to observe and verify the results practically.We can approach the encoder in
terms of its impulse response i.e. the response of the encoder to a single “one” bit that moves
through it. Consider the contents of the register in Fig (a)

Branch Word
Register Contents
U1 U2
1000000 1 1
0100000 0 1
0010000 1 1
0001000 1 1
0000100 0 0
0000010 1 0
0000001 1 1
Fig (b)
Input sequence: 1000000
Output sequence: 11 01 11 11 00 10 11
The output sequence for the input “one” is called the impulse response of the encoder. Then for
the input sequence m = 1 1 1 1 1 1 1, the output may be found by the superposition or the linear
addition of the time shifted input “impulses” as follows:
 Fig (c)

Observe that this is the same output obtained in Fig (d), demonstrating that convolutional codes
are linear. It is from this property of generating the output by the linear addition of time shifted
impulses, or the convolution of the input sequence with the impulse response of the encoder, that
we derive the name convolutional encoder.

PROCEDURE:
1) Carry out the connections as per the block diagram and switch settings.
2) Connect power supply in proper polarity to the kit ADCL-06 and switch it on.
3) Keep the Data clk select switch SW2 towards slow position.
4) Select data pattern using select switch SW1 in the Data Generator block.
5) Connect SERIAL DATA generated on board to DATA IN of CONVOLUTION
ENCODER.
6) Observe RDY1 pin, convolutionally encoded data will be observed at OUT1 and
OUT2 post. The convolutionally encoded data are valid from the instant when RDY1
goes high.
7) Connect OUT1 and OUT2 post of Convolution Encoder block IN1 and IN2 of Hard
Decision Viterbi Decoder block.
8) Observe the decoded data at the DATA OUT1 post of Hard Decision Viterbi Decoder
block.
 9) Repeat the procedure by keeping the data clock select switch towards fast position.
Note1: The reason for the provision of data clock with high and low frequency, using data clk
select switch is to observe the encoded and decoded data in a slow as well as fast mode.

Note2: It is advised to observe the decoded data i.e. output of the Hard decision Viterbi Decoder
in fast mode because it takes approximately four minutes by the Viterbi decoder to decode the
data since the operating frequency is very low.

OBSERVATIONS:

Input data: 0000 0010

Encoded data:
OUT1: 1101 1010
OUT2: 1001 1110
Decoded data: 0000 0010

PRECAUTIONS:
1) Connect the power supply with proper polarity.
2) Do not make any interconnections when the power supply is on.
3) Keep all the switch faults in off position.

RESULT:
Thus we have studied convolution encoding and hard decision viterbi decoding technique of
serial data and also observed how a serial data is convolutionally encoded and when it is passed
through an error free medium how it is decoded using Hard Decision Viterbi Decoder.