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OPA659
SBOS342C – DECEMBER 2008 – REVISED NOVEMBER 2015
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SOT-23 (5) 2.90 mm × 1.60 mm
OPA659
SON (8) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
+6V
Transimpedance Gain vs Frequency
130
RF = 1MW, CF = Open
0.1mF 10mF
120
RF = 100kW, CF = Open
Transimpedance Gain (dBW)
110
RF = 10kW,
VOUT ROUT 100 CF = Open
50W Load
OPA659 RF = 100kW,
90 CF = 0.5pF
RF 80
RF = 10kW, CF = 1.5pF
Photo 70
Diode ID CD RF = 1kW, CF = Open
CF 60
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA659
SBOS342C – DECEMBER 2008 – REVISED NOVEMBER 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 9 Application Information....................................... 14
2 Applications ........................................................... 1 9.1 Application Information............................................ 14
3 Description ............................................................. 1 9.2 Typical Application .................................................. 18
4 Revision History..................................................... 2 10 Power Supply Recommendations ..................... 20
5 Related Operational Amplifier Products.............. 3 11 Layout................................................................... 21
6 Pin Configuration and Functions ......................... 3 11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 22
7 Specifications......................................................... 3
11.3 Thermal Pad Information ...................................... 22
7.1 Absolute Maximum Ratings ...................................... 3
11.4 Schematic and PCB Layout .................................. 23
7.2 ESD Ratings.............................................................. 4
11.5 Evaluation Module................................................. 24
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information .................................................. 4 12 Device and Documentation Support ................. 25
7.5 Electrical Characteristics........................................... 4 12.1 Device Support .................................................... 25
7.6 Typical Characteristics .............................................. 6 12.2 Community Resources.......................................... 25
12.3 Trademarks ........................................................... 25
8 Detailed Description ............................................ 13
12.4 Electrostatic Discharge Caution ............................ 25
8.1 Overview ................................................................. 13
12.5 Glossary ................................................................ 25
8.2 Feature Description................................................. 13
8.3 Device Functional Modes........................................ 13 13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Deleted THERMAL CHARACTERISTICS row from Electrical Characteristics ..................................................................... 5
• Removed lead temperature specification from Absolute Maximum Ratings table ................................................................. 3
• Added DRB package to test condition for Input Offset Voltage parameter, TA = –40°C to 85°C .......................................... 5
• Added performance specifications for Input Offset Voltage parameter, DBV package.......................................................... 5
• Added performance specifications for Average Offset Voltage Drift parameter, DBV package ............................................ 5
• Added footnote (2) to Electrical Characteristics (VS = ±6V) table .......................................................................................... 5
• Added paragraph (f) to the Board Layout section ................................................................................................................ 22
• Changed Changed ordering information for SOTS23-5 (DBV) package and added footnote; availability expected 2Q
2009 ....................................................................................................................................................................................... 3
DRB Package
8-Pin VSON With Exposed Thermal Pad DRV Package
Top View 5-Pin SOT23
Top View
NC 1 8 NC
Output 1 5 +VS
Inverting Input 2 7 +VS
Pin Functions
PIN
TYPE DESCRIPTION
NAME SOIC SOT-23
1
NC 5 — — No Connection
8
VIN– 2 4 I Inverting Input
VIN+ 3 3 I Noninverting Input
VOUT 6 1 O Output of amplifier
–VS 4 2 POW Negative Power Supply
+VS 7 5 POW Positive Power Supply
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted).
MIN MAX UNIT
Power Supply Voltage VS+ to VS– ±6.5 V
Input Voltage ±VS V
Input Current 100 mA
Output Current 100 mA
Continuous Power Dissipation See Thermal Information
Operating Free Air Temperature, TA –40 85 °C
Maximum Junction Temperature, TJ 150 °C
Maximum Junction Temperature, TJ (continuous operation for long term reliability) 125 °C
Storage Temperature, Tstg –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
AC PERFORMANCE
VO = 200 mVPP, G = 1 V/V C 650 MHz
VO = 200 mVPP, G = 2 V/V C 335 MHz
Small-Signal Bandwidth
VO = 200 mVPP, G = 5 V/V C 75 MHz
VO = 200 mVPP, G = 10 V/V C 35 MHz
Gain Bandwidth Product G > 10 V/V C 350 MHz
Bandwidth for 0.1dB Flatness G = 2 V/V, VO = 2VPP C 55 MHz
Large-Signal Bandwidth VO = 2 VPP, G = 1 V/V B 575 MHz
Slew Rate VO = 4-V Step, G = 1 V/V B 2550 V/μs
Rise and Fall Time VO = 4-V Step, G = 1 V/V C 1.3 ns
Settling Time to 1% VO = 4-V Step, G = 1 V/V C 8 ns
Pulse Response Overshoot VO = 4-V Step, G = 1 V/V C 12%
Harmonic Distortion, 2nd harmonic VO = 2 VPP, G = 1 V/V, f = 10 MHz C –79 dBc
Harmonic Distortion, 3rd harmonic VO = 2 VPP, G = 1 V/V, f = 10 MHz C –100 dBc
Intermodulation Distortion, 2nd VO= 2 VPP Envelope (each tone 1 VPP),
C –72 dBc
intermodulation G = 2 V/V, f1 = 10 MHz, f2 = 11 MHz
Intermodulation Distortion, 3rd VO= 2 VPP Envelope (each tone 1 VPP),
C –96 dBc
intermodulation G = 2 V/V, f1 = 10 MHz, f2 = 11 MHz
(1) Test levels: (A) 100% tested at 25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
4 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
4 4
G = +1V/V G = +1V/V
2 2
G = +2V/V G = +2V/V
Normalized Signal Gain (dB)
Figure 1. Noninverting Small-Signal Frequency Response Figure 2. Noninverting Large-Signal Frequency Response
(VO = 200 mVPP) (VO = 2 VPP)
4 4
G = +1V/V G = -1V/V
2 2 G = -2V/V
G = +2V/V
Normalized Signal Gain (dB)
Figure 3. Noninverting Large-Signal Frequency Response Figure 4. Inverting Small-Signal Frequency Response
(VO = 6 VPP) (VO = 200 mVPP)
4 4
G = -1V/V G = -2V/V G = -1V/V
2 G = -2V/V 2
Normalized Signal Gain (dB)
0 0
-2 -2
G = -5V/V G = -5V/V
-4 -4
-6 -6
G = -10V/V G = -10V/V
-8 -8
-10 -10
-12 VS = ±6.0V -12 VS = ±6.0V
RL = 100W RL = 100W
-14 -14
VO = 2VPP VO = 6VPP
-16 -16
100k 1M 10M 100M 1G 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)
Figure 5. Inverting Large-Signal Frequency Response Figure 6. Inverting Large-Signal Frequency Response
(VO = 2 VPP) (VO = 6 VPP)
0.1 0.5
VIN/VOUT (V)
VIN/VOUT (V)
0 0
-0.1 -0.5
-0.2 -1.0
-0.3 -1.5
0 10 20 30 40 50 0 10 20 30 40 50
Time (ns) Time (ns)
Figure 7. Noninverting Transient Response (0.5-V Step) Figure 8. Noninverting Transient Response (2-V Step)
3.5 0.3
VOUT
VIN
2.5 0.2
VOUT
1.5 VIN
0.1
VIN/VOUT (V)
VIN/VOUT (V)
0.5
0
-0.5
-0.1
-1.5
-2.5 -0.2
-3.5 -0.3
0 10 20 30 40 50 0 10 20 30 40 50
Time (ns) Time (ns)
Figure 9. Noninverting Transient Response (5-V Step) Figure 10. Inverting Transient Response (0.5-V Step)
1.5 3.5
VOUT VOUT
VIN VIN
1.0 2.5
1.5
0.5
VIN/VOUT (V)
VIN/VOUT (V)
0.5
0
-0.5
-0.5
-1.5
-1.0 -2.5
-1.5 -3.5
0 10 20 30 40 50 0 10 20 30 40 50
Time (ns) Time (ns)
Figure 11. Inverting Transient Response (2-V Step) Figure 12. Inverting Transient Response (5-V Step)
Figure 13. Harmonic Distortion vs Frequency Figure 14. Harmonic Distortion vs Noninverting Gain at
10 MHz
-50 -50
VS = ±6.0V Second VS = ±6.0V
-55 RL = 100W -55 Gain = 1V/V
Harmonic
-60 R F = 0W
Harmonic Distortion (dBc)
-60
Harmonic Distortion (dBc)
VOUT = 2VPP
f = 10MHz -65 VOUT = 2VPP
-65
f = 10MHz
-70 -70
-75 -75
Second
-80 -80 Harmonic
Third
-85 Harmonic -85
-90 -90 Third
Harmonic
-95 -95
-100 -100
0 2 4 6 8 10 0 100 200 300 400 500 600 700 800 900 1k
Inverting Gain (V/V) RLOAD (W)
Figure 15. Harmonic Distortion vs Inverting Gain at 10 MHz Figure 16. Harmonic Distortion vs Load Resistance at
10 MHz
-50 -70
VS = ±6.0V
Second
6
Gain = 1V/V -75 Harmonic
-60 RF = 0W
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
RL = 100W Second
6 -80
-70 Harmonic
f = 10MHz -85
-80 -90
Third
Harmonic Third
-95
-90 Harmonic
-100 f = 10MHz
Gain = +2V/V
-100
-105 RL = 100W
VOUT = 2VPP
-110 -110
0 2 4 6 4.0 4.5 5.0 5.5 6.0
VOUT (VPP) ±Supply Voltage (V)
Figure 17. Harmonic Distortion vs Output Voltage Figure 18. Harmonic Distortion vs ±Supply Voltage
-60 1 2
Third-Order
VOUT(V)
VIN(V)
-70 0 0
VS = ±6.0V VOUT
-80 -1 -2
RL = 100W Right Scale
Gain = +2V/V
-90 -2 -4
Two-Tone, 1MHz Spacing
1VPP Each Tone
-100 -3 -6
0 50 100 150 0 20 40 60 80 100 120
Frequency (MHz) Time (ns)
Figure 19. Two-Tone, Second- and Third-Order IMD vs Figure 20. Overdrive Recovery (Gain = 2 V/V)
Frequency
3 6 1000
0 0
Input-Referred
Voltage Noise
-1 -2 10
VS = ±6.0V Input-Referred
6
-2 -4 Current Noise
RL = 100W
Gain = -2V/V
-3 -6 1
0 20 40 60 80 100 120 10 100 1k 10k 100k 1M 10M
Time (ns) Frequency (Hz)
Figure 21. Overdrive Recovery (Gain = –2 V/V) Figure 22. Input-Referred Voltage and Current Noise Density
80 100
+PSRR
70
60
CMRR, PSRR (dB)
-PSRR
50
RISO (W)
CMRR
40 10
30
20
10
0 1
100k 1M 10M 100M 10 100 1000
Frequency (Hz) Capacitive Load (pF)
Figure 23. Common-Mode Rejection Ratio and Power- Figure 24. Recommended RISOvs Capacitive Load
Supply Rejection Ratio vs Frequency (RLOAD = 1 kΩ)
CL = 1000pF, RISO = 5W
-10 20 AOL Phase -90
10
-15
0 -135
-20
VS = ±6.0V -10
G = +1V/V
-25 -20 -180
100k 1M 10M 100M 1G 10k 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)
Figure 25. Frequency Response vs Capacitive Load Figure 26. Open-Loop Gain and Phase
(RLOAD = 1 kΩ)
1k 130
VS = ±6.0V RF = 1MW, CF = Open
Closed Loop Output Impedance (W)
G = +1V/V 120
RF = 100kW, CF = Open
50
RF = 1kW, CF = 3.3pF
0.01 40
100k 1M 10M 100M 1G 100k 1M 10M 100M
Frequency (Hz) Frequency (Hz)
Figure 27. Closed-Loop Output Impedance vs Frequency Figure 28. Transimpedance Gain vs Frequency (CD = 10 pF)
130 130
RF = 1MW, CF = Open RF = 1MW, CF = Open
120 120
RF = 100kW, CF = Open RF = 1MW, RF = 100kW, CF = Open
Transimpedance Gain (dBW)
40 40
100k 1M 10M 100M 100k 1M 10M 100M
Frequency (Hz) Frequency (Hz)
Figure 29. Transimpedance Gain vs Frequency (CD = 22 pF) Figure 30. Transimpedance Gain vs Frequency (CD = 47 pF)
RF = 1MW, 3
110
CF = 0.25pF RF = 10kW, CF = Open 2
100
±VOUT (V)
RF = 100kW, RF = 1kW, 1 VS = ±6.0V
90
CF = 0.5pF CF = Open 0 G = +1V/V
80 RF = 249W
-1
70 RF = 10kW, CF = 1.5pF
-2
60 -3
VOUT Low
50 RF = 1kW, CF = 4.7pF -4
40 -5
100k 1M 10M 100M 10 100 1000
Frequency (Hz) RLOAD (W)
Figure 31. Transimpedance Gain vs Frequency Figure 32. Maximum/Minimum ±VOUTvs RLOAD
(CD = 100 pF)
3000
VS = ±6.0V Rising
6
G = +2V/V Slew Rate
RLOAD = 100W
Falling
Slew Rate
Slew Rate (V/ms)
2000
1000
0
0 1 2 3 4 5
VOUT / VSTEP (V)
8 Detailed Description
8.1 Overview
The OPA659 is high gain-bandwidth, voltage feedback operational amplifier featuring a low noise JFET input
stage. The OPA659 is compensated to be unity gain stable. The OPA659 finds wide use in optical front-end
applications and in test and measurement systems that require high input impedance.
External Internal
Pin Circuitry
-VCC
These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection
diodes can typically support 30-mA continuous current. Where higher currents are possible (for example, in
systems with ±12-V supply parts driving into the OPA659), current limiting series resistors should be added into
the two inputs. Keep these resistor values as low as possible because high values degrade both noise
performance and frequency response.
9 Application Information
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
0.1mF 10mF
VIN
50W Source
VOUT ROUT
50W Load
OPA659
RT
0.1mF 10mF
-6V
Voltage-feedback op amps can use a wide range of resistor values to set the gain. To retain a controlled
frequency response for the noninverting voltage amplifier of Figure 36, the parallel combination of RF || RG should
always be less than 200 Ω. In the noninverting configuration, the parallel combination of
RF || RG forms a pole with the parasitic input and board layout capacitance at the inverting input of the OPA659.
For best performance, this pole should be at a frequency greater than the closed-loop bandwidth for the
OPA659. For this reason, TI recommends a direct short from the output to the inverting input for the unity-gain
follower application. Table 2 lists several recommended resistor values for noninverting gains with a 50-Ω input
and output match.
+6V
0.1mF 10mF
VOUT ROUT
50W Load
OPA659
RT
RF
RG
0.1mF 10mF
-6V
Table 2. Resistor Values for Noninverting Gains With 50-Ω Input/Output Match
NONINVERTING GAIN RF RG RT ROUT
+1 0 Open 49.9 49.9
+2 249 249 49.9 49.9
+5 249 61.9 49.9 49.9
+10 249 27.4 49.9 49.9
0.1mF 10mF
VOUT ROUT
50W Load
OPA659
VIN RG RF
50W Source
RT
0.1mF 10mF
-6V
The inverting circuit can also use a wide range of resistor values to set the gain; Table 3 lists several
recommended resistor values for inverting gains with a 50-Ω input and output match.
Table 3. Resistor Values For Inverting Gains With 50-Ω Input/Output Match
INVERTING GAIN RF RG RT ROUT
–1 249 249 61.9 49.9
–2 249 124 84.5 49.9
–5 249 49.9 Open 49.9
–10 499 49.9 Open 49.9
Figure 37 shows the noninverting input tied directly to ground. Often, a bias current-cancelling resistor to ground
is included here to nullify the DC errors caused by input bias current effects. For a JFET input op amp such as
the OPA659, the input bias currents are so low that dc errors caused by input bias currents are negligible. Thus,
TI does not recommend a bias current-cancelling resistor at the noninverting input.
RT IBN OPA659 eO
4kTRT
RF
IBI
4kTRF
4kT RG
RG
The total output spot noise voltage can be computed as the square root of the squared contributing terms to the
output noise voltage. This computation adds all the contributing noise powers at the output by superposition, then
takes the square root to arrive at a spot noise voltage. Equation 1 shows the general form for this output noise
voltage using the terms shown in Figure 38.
2
RF RF
eO = [4kTR T
2
+ (IBNRT) + eN 2
] 1+
RG
+ (IBIRF)2 + 4kTRF 1 +
RG
(1)
Dividing this expression by the noise gain (GN = 1 + RF/RG) gives the equivalent input-referred spot noise voltage
at the noninverting input, as Equation 2 shows.
2
Putting high resistor values into Equation 2 can quickly dominate the total equivalent input-referred noise. A
source impedance on the noninverting input of 5 kΩ adds a Johnson voltage noise term equal to that of the
amplifier alone (8.9 nV/Hz). While the JFET input of the OPA659 is ideal for high source impedance applications
in the noninverting configuration of Figure 35 or Figure 36, both the overall bandwidth and noise are limited by
high source impedances.
0.1mF 10mF
VOUT ROUT
50W Load
OPA659
RF
Photo
l
ID CD
Diode
CF
0.1mF 10mF
-VB -6V
Table 5. OPA659 TIA Component Values and Bandwidth for Various Diode Capacitance and Gains
CD RF CF f–3dB
CDIODE = 10 pF
13.5 pF 1 kΩ 3.50 pF 64.24 MHz
13.5 pF 10 kΩ 1.11 pF 20.31 MHz
13.5 pF 100 kΩ 0.35 pF 6.42 MHz
13.5 pF 1 MΩ 0.11 pF 2.03 MHz
CDIODE = 20 pF
23.5 pF 1 kΩ 4.62 pF 48.69 MHz
23.5 pF 10 kΩ 1.46 pF 15.40 MHz
23.5 pF 100 kΩ 0.46 pF 4.87 MHz
23.5 pF 1 MΩ 0.15 pF 1.54 MHz
CDIODE = 50 pF
53.5 pF 1 kΩ 6.98 pF 32.27 MHz
53.5 pF 10 kΩ 2.21 pF 10.20 MHz
53.5 pF 100 kΩ 0.70 pF 3.23 MHz
53.5 pF 1 MΩ 0.22 pF 1.02 MHz
Table 5. OPA659 TIA Component Values and Bandwidth for Various Diode Capacitance and
Gains (continued)
CD RF CF f–3dB
CDIODE = 100 pF
103.5 pF 1kΩ 9.70pF 23.20MHz
103.5 pF 10kΩ 3.07pF 7.34MHz
103.5 pF 100kΩ 0.97pF 2.32MHz
103.5 pF 1MΩ 0.31pF 0.73MHz
1000 1000
100 100
10 10
1 1
10k 100k 1M 10M 100M 10k 100k 1M 10M 100M
Frequency (Hz) C001
Frequency (Hz) C002
Figure 40. Simulated Total Output Noise Figure 41. Measured Total Output Noise
80
75
70
65
Output (dB)
60
55
50
45
40
1k 10k 100k 1M 10M 100M
Frequency (Hz) C003
11 Layout
Bypass
Capacitors
Output-matching
resistor close to
Minimize the
trace length of VOUT minimizes
the feedback parasitic output
element capacitance
Ground plane
removed under
VIN
Bypass
Capacitors
2 7
- 6
3
+
4
+
+
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 11-Oct-2015
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
OPA659IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BZX
& no Sb/Br)
OPA659IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BZX
& no Sb/Br)
OPA659IDRBR ACTIVE SON DRB 8 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OBFI
& no Sb/Br)
OPA659IDRBT ACTIVE SON DRB 8 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OBFI
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 11-Oct-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Oct-2015
Pack Materials-Page 2
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