Pandian Saraswathi Yadav Engineering College

Arasanoor ,Sivagangai – 630561

Department of Electronics and Communication Engineering
Course Plan
Department : CSE
Subject Code & Subject : CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN
Year/Semester : I/II
Name of the faculty Member: Mr.S.MANIKANDAN
Text and Reference Books
SI.No Title of the book Author(s) Publications
Morris Mano M. and IV Edition, Pearson
T1 Digital Design
Michael D. Ciletti Education, 2008.
Fourth Edition, Pearson
Digital Design Principles and Education,
R1 John F. Wakerly,
Practices
2007.
Fifth Edition – Jaico
R2 Fundamentals of Logic Design Charles H. Roth Jr Publishing House,
Mumbai, 2003.
R3 Digital Principles and Design Donald D. Givone Tata Mcgraw Hill, 2003.
Oxford University Press,
R4 Digital Electronics Kharate G. K.
2010

Lecture Page Numbers of

Topic to be taught
No Text book

I - BOOLEAN ALGEBRA AND LOGIC GATES

1. Review of Number Systems T1(3-9)
2. Arithmetic Operations T1(13-24)
3. Binary Codes, Boolean Algebra andTheorems T1(35-41)
4. Boolean Functions T1(42-46)
5. Simplification of Boolean Functions using Karnaugh Map T1(46-50)
6. Tabulation Methods T1(51-55)
7. Logic Gates T1(55-60)
8. NAND Implementations T1(87-92)
9. NOR Implementations T1(92-94)
II-COMBINATIONAL LOGIC
10. Combinational Circuits T1(135-136)
11. Analysis and Design Procedures T1(136-142)
12. Circuits for Arithmetic Operations T1(143-154)
13. CodeConversion T1(17-24)
14. Decoders and Encoders T1(162-168)
15. Multiplexers and Demultiplexers T1(168-174)
16. Introduction to HDL T1(174-179)
17. HDL Models of Combinational circuits T1(180-185)
 18. HDL Models of Combinational circuits T1(186-190)
III-SYNCHRONOUS SEQUENTIAL LOGIC
19. Sequential Circuits T1(197-199)
20. Latches T1(199-203)
21. Flip Flops T1(203-210)
22. Analysis and Design Procedures T1(210-221)
23. State Reductionand State Assignment T1(233-239)
24. Shift Registers T1(255-267)
25. Counters T1(268-293)
26. HDL for Sequential Logic Circuits T1(221-232)
27. HDL for Sequential Logic Circuits. T1(293-298)
IV-ASYNCHRONOUS SEQUENTIAL LOGIC
28. Analysis of Asynchronous Sequential Circuits T1(434-443)
29. Design of Asynchronous Sequential Circuits T1(443-446)
30. Analysis and Design of Asynchronous Sequential Circuits T1(446-453)
31. Reduction of State and Flow Tables T1(453-457)
32. Reduction of State and Flow Tables T1(457-460)
33. Reduction of State and Flow Tables T1(461-464)
34. Race-free State Assignment T1(464-469)
35. Hazards T1(469-473)
36. Hazards T1(473-474)
V-MEMORY AND PROGRAMMABLE LOGIC
37. RAM T1(308-314)
38. ROM T1(322-328)
39. Memory Decoding T1(314-319)
40. Error Detection and Correction T1(319-322)
41. Programmable Logic Array T1(328-332)
42. Programmable Array Logic T1(332-336)
43. Sequential Programmable Devices T1(336-339)
44. Sequential Programmable Devices T1(339-344)
45. Application Specific IntegratedCircuits T1(344-351)

Signature of faculty member Signature of HOD Signature of Principal