La MADE EASY India's Best Institute for IES, GATE & PSUs GATE 2018 + MADE EASY has taken due care in making solutions. If you find any discrepency/ typo/technical error, kindly share/post your views. If you want to contest the answer key given by MADE EASY, kindly post your suggested answer with detailed explanations at www.madeeasy.in Students are requested to share their expected marks in GATE 2018 www.madeeasy.in Corporate Office: 44-A/1, Kalu Sarai, New Delhi-110016 | Ph: 011-45124612, 9958995830 ean Indore | Pune | Bhubaneswar | Kolkata | PatnaIndia Beat Inaeiute for ES, GATE & PSUS peer ari Por ery EG Q.1. What is the missing number in the following sequence? (a) 2880 (b) 1440 (c) 720 (a) 0 Ans. (b) OO Oe: a2 ‘From where are they bringing their books? bringing books from (a) Their, they're, there (b) They're, their, there (c) There, their, they're (d) They're, there, there Ans. (b) @.3 What would be the smallest natural number which when divided either by 20 or by 42 or by 76 leaves a remainder of 7 in each case? (@) 3047 (b) 6047 (e) 7987 (a) 63847 Ans. (c) Number is divided by either by 20 or 42 or by 76 K x LOM(20, 42, 76) + constant difference = 7890 K + 7 (K is natural number) Least number will be 7890 + 7 7897.Inia Best Inatituce for IS, GATE & PSUs a4 “A investigation can sometimes yield new facts, but typically organized ones are more successful he word that best fils the blank in the above sentence is. (@) meandering (b) timely (©) consistent (@ systematic ‘Ans. (a) Meandering : wandering aimlessiyindirect. Q.5 The area of a square is d. What is the area of the circle which has the diagonal of the square as its diameter? (@) nd (b) na? dae 1 snd’ nd OF @ 3 Ans. (4) a e ia ‘Area of square = d Side one side of square = a Diagonal of square = Jd+d = J2d Area of circle = m1? Page 3India Beat Inaeiute for ES, GATE & PSUS PELE Le aed Q6 In pgr#0 and p*= 3 q= ; what is the value of the product xyz? 1 (a) 1 (b) —— c © oy 1 © par ‘Ans. (c) Put Which is true i.e. So, Alternate Solution: Eee aneIndia's Best Institute for IES, GATE & PSUs PDE a CPA 1 YEAR / 2 YEARS PROGRAMME Regular & Weekend Batches Commencement Dates Regular Batches from | Weekend Batches from Weekend Batches from \_ 26" Feb, 2018 17"Feb,2018 10” Feb, 2018 Regular Batches from Regular Batches from 19" Feb, 2018 J 12" Feb, 2018 L Regular Batches from Regular Batches from 26" Feb, 2018 8" Mar, 2018 u ) Regular Batches f Regular Batches from L 19" Feb, 2018 J 18" Feb, 2018 PU Regular Batches from | Weekend Batches from Regular Batches from \_15"Feb,2018 | 24" Feb, 201 15" Feb, 2018 ADMISSION OPEN at all Centres MADE EASY CentresInia Best Inatituce for IS, GATE & PSUs Q.7 _Inappreciation of the social improvements completed in a town, a wealthy philanthropist decided to gift Rs 750 to each male senior citizen in the town and Rs 1000 to each female senior citizen. Altogether, there were 300 senior citizens eligible for this gift However, only 8/9" of the eligible men and 2/3% of the eligible women claimed the gift How much money (in Rupees) did the philanthropist give away in total? (a) 1,50.000 (b) 2,00,000 (c) 1,75,000 (d) 151,000 Ans. (b) Male + Female = 300 (i) Total money = $Mx750+EF x 1000 _ 8000), , 6000,- 9 9 From equation (i) Total money = eo: ¢EXMEIT Q.8 In the figure below, ZDEC + ZBFC is equal to of Ne => \ 3 a i (a) Z8CD- ZBAD (b) ZBAD + ZBCF (©) ZBAD+ZBCD (d) ZCBA+ ZADC Page 5Ans. as Ans. Indias Best Inatiute for ES, GATE & PSUs peer ari Por ery (a) “e+ =? asq+e= 180 “i a+ B+ P= 180 (i) «+B + p+ q= 300 di) Equation (i) + (i) = (i) a+q+E+atP+F=a+pepeg E+F=p-a A six sided unbiased die with four green faces and two red faces is rolled seven times. Which of the following combinations is the most likely outcome of the experiment? (@) Three green faces and four red faces, (b) Four green faces and three red faces, (©) Five green faces and two red faces. (d) Six green faces and one red face. (c) Four green, two red face PIG) = a(R) = n= omni, nen." _ 95x28 _ 35x28 3 8ato Ans. Inia Best Inatituce for IS, GATE & PSUs 2, _ 35x24 _ 35x24 (Cn 2y (ay? @, P(G = 5) = Tox(3) +3) 2x2 _ 42x24 3 By ° @, PG =6)= 7exx(3) +(3) _ Tx® _ 28x2t eo Option 3 is maximum value. So, five green faces and two red faces. In a party, 60% of the invited guests are male and 40% are female, If 80% of the invited quests attended the party and if all the invited female guests attended, what would be the ratio of males to females among the attendees in the party? (@ 2:3 ()ts1 (© 3:2 (2:4 (b) 7\N oon wn \ (60 40(W) So, M must be 80 ~ 40 = 40 Ratio of male to female 40 : 40 alIndia Beat Inaeiute for ES, GATE & PSUS peer ari Por ery ae Q.1 Consider a long-lived TCP session with an end-to-end bandwidth of 1 Gbps (= 10* bits- per-second). The session starts with a sequence number of 1234. The minimum time (in seconds, rounded to the closest integer) before this sequence number can be used again is Ans. (34) 1 sec = 10° 2 x8 = 2 bytes 10° " = 34.38 sec Q.2 Consider the sequential circuit shown in the figure, where bath flip-flops used are positive edge-ttiggered D flip-flops. Clock: The number of states in the state transition diagram of the circuit that have a transition back to the same stale on some value of “in’ is Ans. (2) nf, —|> a, f+ out FEI FO State Table: PS__| input | FFinputs NS. & foe |e | =e [=a | a | a] Owt= a o}o,o|o 0 {ofo; o o}o|1|4 o |+fo] o o}1]o |] o o |ofo| o o}a]a]a o |+fo] o 1}o]o] o 1 fofal 4 sto} a |4 a ofafal oa r}a]o]o 1 fofal 4 atatali a tata] 4 Eee aneInia Best Inatituce for IS, GATE & PSUs State Transition Diagram: nae The question is on the number of self loop states. The number of self loop stales are 00 and 11 Hence answer is 2. Q.3 Let @ and © denote the Exclusive OR and Exclusive NOR operations, respectively. Which one of the following is NOT CORRECT? (a) P@Q=PaQ (b) Peg=PaQ () Pod=PoeQ (@) PeP)ea= Ans. (d) “ P@Q = PoQ tue ® Pea = Pea tue © Ped = Pea tue 0) (P@P)@Q = (PaP)aO false (P@P)@Q = 10Q= (PaP)o@ = 080-Q (P@P)@Q + PaP)oQ oO Q.4A32-bitwide main memory unit with a capacity of 1 GB is built using 256 M x 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2"*. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is Ans. (59) Number of chips required to designed 1 G8 memory = 8 Chips So, we can arrange them in 1 row to make the word size as 32 bitsas Ans. India Beat Inaeiute for ES, GATE & PSUS peer ari Por ery Rows : [C1] [C2] [C3]. [Ca] [C: Chip 1256M x4] Refresh circuit is designed for memory unit to refresh the entite chip data, To minimize this overhead, Design the chips into a banks i.e. 4 rows of chips grouped into 1 bank. So, refresh occurs in parallel Time required for refresh _ 2" x 50ns Le. Refresh overhead = ——— orn or Refresh interval 2me = 16384x50N8 _ 9 aoa6 = 40.96% ams % time available for read/write operations in the main memory unit is = 1 - 0.4096 0.5904 59.04% 50% bua Which one of the following is a closed form expression for the generating function of the sequence {a,), where a, = 2n + 3 for all n= 0, 1, 2, ....? 3 3x ® aR © GaP (a) (ie a an+3 Since generating function for 1 is, and nis a the generating function for a, is 2x (1-3? _ 2x+3(1-x)_ 3x (exh (xP As) = which is option (d). EE Page 10Inia Best Inatituce for IS, GATE & PSUs Q.6 The chromatic number of the following graph is Ans. (3) Since the largest complete sub graph is K,, chromatic number is atleast 3. We can try for a chromatic number of 3 by using 3 colors, as follows: Red tue DQ 6S Blue Green N Since we have successfully, properly coloured all vertices with only 3 colors, the chromatic number of this graph is 3 7 _InanEntity-Relationship (ER) model, suppose Ris amany-to-one relationship from entity set E1 to entity set E2, Assume that E1 and E2 participate totally in R and that the cardinality of E1 is greater than the cardinality of £2 Which one of the following is true about R? (@) Every entity in E71 is associated with exactly one entity in E2, (b) Some entity in £1 is associated with more than one entity in E2, (©) Every entity in £2 is associated with exactly one entity in E1 (A) Every entity in £2 is associated with at most one entity in E1 Ans. (a) E1 entries > £2 entities Page 11India Beat Inaeiute for ES, GATE & PSUS PELE Le aed ER — 2 Every entity in E1 is associated with exactly one entity in E2 Q8_ Consider the following C program: Finclude struct ournode { char x, ¥, z: ) int main () { uct ournade p = {'1', 0, ‘a’ + 2} struct ournode *p = &q; printi(“%e, %e”, *((char*) q + 1), *(char*) q + 2)) return 0, } he output of this program is: @ 0c (0) Oa42 © O,a+2 (@ 0,0 Ans. (a) id Q.9 The value of [2°"xc0s(x*)dx correct to three decimal places (assuming that 4) is Ans, (0.289) nis JR" rcos")ae Let t=2 dt = 2x de at = rok = 5 2 x 4 _(® when x = 0, (= O and when x = *,t=(¥ Se eee So required integral reduce to (wis? J sostat = [sin¢ a i"Inia Best Inatituce for IS, GATE & PSUs = 0.289 {rounded to 3 decimal places) Q.10 The following are some events that occur after a device controller issues an interrupt while process L is under execution, (P) The processor pushes the process status of L onto the control stack. (Q) The processor finishes the execution of the current instruction (R) The processor executes the interrupt service routine. (S) The processor pops the process status of L from the control stack. (T) The processor loads the new PC value based on the interrupt. Which one of the following is the correct order in which the events above occur? (a) QPTRS (b) PTRSQ (c) TRPOS (@) aTPRS. Ans. (a) Processor required to handle the interrupt Processor finishes the execution of the current instruction, Processor pushes the process status of L onto the control stack. Processor loads the new PC value based on the interrupt. Processor executes the interrupt service routine. Processor pops the process slatus of “L” from the control stack. eo EET Q.11_ Consider the following statements regarding the slow start phase of the TCP congestion control algorithm. Note the cwnd stands for the TCP congestion window and MSS denotes the Maximum Segment Size. () The cwndincreases by 2 MSS on every successful acknowledgment. (i) The cwnd approximately doubles on every successful acknowledgment. (ii) The cwndincreases by 1 MSS every round trip time, (iv) The cwnd approximately doubles every round trip time. Which one of the following is correct? (@) Only (i) and (i) are true (b) Only (i) and (il) are true (©) Only (iv) is true (A) Only (i) and (iv) are true Ans. (0) cwnd approximately doubles every round trip time. Eee aneQ12z Ans. Qs India Beat Inaeiute for ES, GATE & PSUS peer ari Por ery Two people, P and Q, decide to independently roll two identical dice, each with 6 faces. Numbered 1 to 6, The person with the lower number wins. In case of a tie, they roll the dice repeatedly until there is no tie. Define a trial as a throw of the dice by P and Q. Assume that all 6 numbers on each dice are equi-probable and that all trials are independent. The probability (rounded to 3 decimal places) that one of them wins on the third trial is (0.023) Pione of them wins in 3rd trial) = P(lst trial is Tie) x Pind trial is Tie) x Plone of them wins 3rd trial) P(Tie in any trial) = P(P=1 and Q=1) + P(P=2 and Q=: + P(P=6 and Q=6) 14,4 44 36°36 °36" 36°36 oi 3606 Plone of them wins) = 1 ~ P(Tie) 118 So required probability = 5x 5x 028 (rounded to 3 decimal places) Consider the following two tables and four queries in SQL. Book (isbn, bname), Stock (isbn, copies) Query 1 SELECT B.isbn, S.copies FROM Book 8 INNER JOIN Stock S ON Biisbn = Siisbn; Query 2: SELECT B.isbn, S.copies FROM Book B LEFT OUTER JOIN Stock S ON Biisbn = Siisbn; Query 3: SELECT B isbn, S.copies FROM Book B RIGHT OUT! ON Bisbn = Sisbn; Query 4: SELECT B.isbn, S.copies FROM Book B FULL OUTER JOIN Stock S ON Biisbn = Siisbn; JOIN Stock $ Which one of the queries above is certain to have an output that is superset of the outputs of the other three queries? (@) Query (b) Query2 (©) Query3 (6) Query 4Inia Best Inatituce for IS, GATE & PSUs Ans. (4) Book (abn, brame) Stock sin, copies) 2 8 4 100 48 6 20 soc 10 200 ao 12 400 we ‘Query 1: [abn copies | avery 2: [abn copies 2100 + 100 8 20 6 20 10 200 10 200 2 Null 8 Nut Query: [abn copies ] avery 4: [isbn copies 2100 + 100 8 20 6 20 10 200 10 200 12400 2 Null ut 12 400 Query 4 is full outer join so that full order join record set superset of records compare to inner join, left outer join && right outer join. EET Q.14 Consider a process executing on an operating system that uses demand paging. The average time for a memory access in the systems M units if the corresponding memory page is available in memory and D units if the memory access causes a page fault Ithas been experimentally measured that the average time taken for a memory access in the process is X units Which one of the following is the correct expression for the page fault rate experienced by the process? (a) (D ~ MAX ~ M) (b) (X = M)(D = M) (c) (D ~ X\(D ~ M) (d) (X ~ MD ~ X) ‘Ans. (b) EMAT =P *S + (1-P)*M X=P*D+(1-P)*M X=P'D+M-P'M -M=P(D-M) Paneer errant Page 15,ais Ans. a6 Ans, Qa7 Ans. arg Ans. Eee ane India Beat Inaeiute for ES, GATE & PSUS PELE Le aed The postorder traversal of a binaty tree is 8, 9, 6, 7, 4, 5, 2, 3, 1. The inorder traversal of the same tree is 8, 6, 9, 4, 7, 2, 5, 1, 3. The height of a tree is the length of the longest path from the root to any leaf. The height of the binary tree above is (4) Let G be a finite group on 84 elements. The size of a largest possible proper subgroup of Gis (42) Given |G] = 84 By Lagrang's theorem any subgroup size is a divisior of 84. But a proper subgroup cannot have same size as group. So largest divisor of 84, other than 84 is 42. So, largest proper subgroup can have in size of 42. Match the following: Field Length in bits P._ UDP Header’s Port Number Loa Q. Ethernet MAC Address a) R. IPv6NextHeader Ml, 32 S. TCPHeader's Sequence Number IM. 16 (@ Pill, 4, Rul, S41 (©) Pell, O41, RAV, Sl (©) PAV, O41, Rell, S-ll (A) P-lV, O41, Rell, Sl (c) UDP Header’s Port Number => 16 bit Ethernet MAC Address = 48 bit IPv6 Next Header => 8 bit TCP Header's Sequence Number =» 32 bot Endof Solution Let N be an NFA with a states. Let k be the number of states of a minimal DFA which is equivalent to N, Which one of the following is necessarily true? (@) Kea" (b) Ken (0) ks (d) ks2" (d) ‘nis qumber of states of given fa (may not be minimal) k is number of states of equivalent min dfa. First we convert nfa to cfa using subset construction algorithm and we get an equivalent dfa which will have atmost 2” states. Then we can convert this dfa to a minimal dfa and get a minimal dfa with k states where k < 2"4 PS SAE TUES ELCs CeCe ata eT) aa MADE EASY Meas hy ats India's Best Institute for IES, GATE & PSUs Mains batches are exclusively designed for practice of conventional questions for ESE-2018. Although the syllabus of ESE pre & ‘mains is well covered in classroom course, but stil nterested candidates can enrol in these batches to develop additional skills in ‘order to excel in main examination. The approach followed in these batches are very beneficial toimprove answer writing skillsand special emphasis is given on presentation of answers. These batches are supplemented by well-designed ESE-2018 mains offine testseresasper UPSC-ACAB pater, (is Very useful to develop numerical solving approach & + Special focus on improving answer layout specially for improving writing sil theory questions. Discussion on probable questions. + Classes wil be delivered by senior faculties Helps to develop step by step question solving approach. + Updated Mains workbook for every subject having varied practice question sets (unsolved and solved). Comprehensive and in-depth discussion on collection of, conventional questions thus strengthening fundamental + Test series will be conducted on every Sunday in concepts synchronisation with the syllabus taught in classes. cero) COURSE DURATION CLASS DURATION TEST SERIES Details ‘700 80 days | 250-300 hours 5.8 days a week and 6-7 hours a day Every Sunday evening Streams Centre (Delhi) Batch Type Date Timings ME ‘hitomi Centre Regular 5° March, 2018 | 7:30 AM10130PM ts 7:30 AM to 1:30 PM ce Kal Sarai guar patches commensina ce Kalu Sarai (Choudhary House) Regular from 7:30 AM to 1:30 PM 25° February, 2018 Lado Sarai Centre Regular 7:30 AM to 1:30 PM . Ex. MADE EASY Students | Non MADE EASY Program Commencing Date ‘elaine rng. Come, sir UAE Iver PBachee studonts Mains Exclusive Batch Insane of Mains Cason | 25th February, 2018 712,500 % 16,500 Mains Test Series 18th March, 2018 % 2,000 3,000 (OtineDnine! Documents Required ‘© 2 Photographs + Valid photo ID proof © o1r-4sz4612 “+ ExMADE EASY students shoud produce ea AT their MADE EASY ID card Ped een re cmenyInia Best Inatituce for IS, GATE & PSUs Q.19 Consider a system with 3 processes that share 4 instances of the same resource type. Fach process can request a maximum of K instances. Resource instances can be requested and released only one at a time. The largest value of K that will always avoid deadlock is Ans, (2) V1 Two desdocs Maximum each process can request for 2 resources so, that there will not be any deadlock, because we, have only 4 resource available. So, K value is ‘2! EET Q.20 Consider the following processor design characteristics: |. Register-to-register arithmetic operations only UI, Fixed-length instruction format III, Hardwired control unit Which of the characteristics above are used in the design of a RISC processor? (@) and tl only (b) Il and ill only (©) Land Ill only (@) |, Nand I Ans. (d) RISC processor characteristics 1. Itsupports mode registers, so ALU operations are performed only on aregister data. 2. Itsupport fixed length instructions. 3. Ituses hard-wired control unit Q.21 The sot of all recursively enumerable languages is (@) closed under complementation (b) closed under intersection (6) @ subset of the set of all recursive languages (@) an uncountable set ‘Ans. (b) he set of RE languages is closed under intersection, not closed under complementation, is not a subset of set of REC language and is a countable set Eee aneIndia Beat Inaeiute for ES, GATE & PSUS peer ari Por ery Q.22 Consider a matrix A= uv? where 1 of v. The largest eigenvalue of A is Ans. (3) yo “Q-() Azul 7 -[2le 1 14 = |2 2 (1-a) (2-a)-2-0 W-3h=0 Aa 3)=0 =o or, a=3 The largest eigen value is 3 Q.23 A queue is implemented using a non-circular singly linked list. The queue has a head pointer and tail pointer, as shown in the figure. Let 1 denote of number of nodes in the queue. Let enqueue be implemented by inserting a new node at the head and dequeue bbe implemented by deletion of a node from the tail t f head tal Which one of the following is the time complexity of the most time-efficient implementation of enqueue and dequeue, respectively, for this data structure? (a) (1), 6(1) {b) (1), (7) (©) @(n),0(1) (4) (7), (7) Ans. (b)Inia Best Inatituce for IS, GATE & PSUs Q.24 Consider the following C program: include int counter = 0; int cale (int a, int b) { into; counter ++; it ( 3) retum (a‘a‘a) else ( © = cale (a, b/3}: return (e*c*e}: ) int main ( ) { calc(4, 81); print(362%a!, counter) ) fhe output of this program is Ans. (4) Q.25 Which one of the following statements is FALSE? (@) Context-ree grammar can be used to specify both lexical and syntax rules. (0) Type checking is done before parsing (6) High-level language programs can be translated to different Intermediate Representations. (a) Arguments to a function can be passed using the program stack Ans, (b) Type checking is done before parsing is clearly false because in compiler type checking is done after parsing phase. Q.26 Consider an IP packet with a length of 4500 bytes that includes a 20-byte |Pv4 header and a 40-byte TCP header. The packet is forwarded to an IPv4 router that supports a Maximum Transmission Unit (MTU) of 600 bytes. Assume that the length of the IP header in all the outgoing fragments of this packet is 20 bytes. Assume that the fragmentation offset value stored in the first fragment is 0, The fragmentation offset value stored in the third fragment is Eee aneIndia Beat Inaeiute for ES, GATE & PSUS peer ari Por ery Ans, (144) 20] 40] 1440 " a x ” Fragment Bytes [20] 576] [20] 576] [20] 578] [20] 576 Fragment Ofset (0-71) (72= 148) (144-215) (216-287) EET Q.27 Consider the following four relational schemas. For each schema, all non-trivial functional dependencies are listed. The underlined attributes are the respective primary keys. Schema I: Registration (rolino, courses) Field ‘courses’ is a set-valued attribute containing the set of courses a student has registered for Non-trivial functions dependency: rolino > courses Schema II: Registration (rolino. courseid, email) Non-trvial functional dependencies rolino, courseid — email email > rollno Schema Ill: Registration (rollno_courseid, marks, grade) Non-trivial functional dependencies rolino, courseid > marks, grade marks > grade Schema IV: Registration (colina, courseid, credit) Non-trivial functional dependencies rolino, courseid — credit courseid > credit Which one of the relational schemas above is in SNF but not in BCNF? (@) Schema (b) Schema (©) Schema (d) Schemalv ‘Ans. (b) Schema Il: Registration (rolina, courseid, email) Primary key [rollno. coursaid] Non-trivial functional dependencies: { rollno, courseid —> emai email — rolino ) candidate keys (tolino, courseid,} email courseid} Given relation is in 3NF but not in BCNF EET Paneer errant Page 20,Inia Best Inatituce for IS, GATE & PSUs Q.28 Consider the following problems L(G) denotes the language generated by a grammar G. L(M) denotes the language accepted by a machine M |. Foranunvestricted grammar G and a string w, whether we L(G.) I Given a Turing Machine M, whether L(M) is regular Il, Given two grammars G, and G,, whether L(G,) = L(G.) IV. Given an NFAN, whether there is a deterministic PDA P such that N and P accept the same language. Which one of the following statements is correct? (@) Only land Il are undecidable (b) Only Ill is undecidable (©) Only land IVare undecidable —(d) Only | land Ill are undecidable Ans. (d) |. Membership problem for RE — undecidable I. Regularity problem for RE —> undecidable Ill. Equivalence problem for RE —> undecidable IV. Since DPDA P exists for every nfa N and equivalent to it, this problem is trivially decidable. Ere Q.29 Consider Guwahati (G) and Delhi (D) whose temperatures can be classified as high (4) medium (M) and low (L). Let P(Hg) denote the probability that Guwahati has high temperature. Similarly, P(Mg) and P(Lg) denotes the probability of Guwahati having medium and low temperatures respectively. Similarly, we use P(H,). P(Mp) and P(L) Delhi The following table gives the conditional probabilities for Delhi's temperature given Guwahati’s temperature. Ho [040 048 0.12 Mc | 010 085 025 lg |001 050 049 Consider the first row in the table above. The first entry denotes that if Guwahati has high temperature (H.) then the probabilly of Delhi also having a high temperature (H,) is 0.40; i.¢., P(H[Hg) = 0.40. Similarly, the next two entries are P(M,|H,) = 0.48 and P(Ly|Hg) = 0.12. Similarly for the other rows. Ifitis known that P(H) = 0.2, P(Mg) = 0.5 and P(L,) = 0.3, then the probability (correct, to two decimal places) that Guwahati has high temperature given that Delhi has high temperature is Ans. (0.60) he condition probability table given is He [040 048 0.12 Mc | 010 065 0.25 lg [001 050 049 Eee aneIndias Best Inatiute for ES, GATE & PSUs PELE Le aed P(g) = 0.2 P(Mg) = 05 Pilg) = 0.3 Drawing the tree diagram for HD we get Hy he Hy 02 05 y, OL, 4, 03 oot eon (Ha OH) P(Ho) From diagram, PlHg 0 Hp) = 0.2 x 0.4 Ply) = 0.2 x 0.44 05 x 0.1 + 0.3 x 0.01 = 0.193, P(H | Hp) x Q.30 The size of the physical address space of a processor is 2” bytes. The word length is 2" bytes. The capacity of cache memoty is 2" bytes, The size of each cache block is 2M words. For a K-way set-associative cache memory, the length (in number of bits) of the tag field is (@) P-N-Iog, K (0) P-N+0g,K (©) P-N-M-W-log, K (@) P-N-M-W + log, K Ans. (b) MM space = 2° bytes Physical Address (PA) size = P bits CM size = 2" bytes Block size = 2" words = 2! words * 2 byte = 2M bytes OM size Number of ines = void funt (char *s1, char *s2) { char “tmp; tmp = si st = 82, 82 = imp; } void fun2 (char * char “imp; tmp = *s1 ts1 = "52 *s2 = tmp char ""s2) { int main () ( char *strt = "Hi", *str2 funt (str, str2); print fund (&str1, &str2); print return 0; Bye" 5 %s", strt, str2); ‘hs %s", str1, str2); ) he output of the program above is (@) HiBye Bye Hi (b) HiBye Hi Bye (©) Bye HiHi Bye (d) Bye Hi Bye Hi ‘Ans. (a) Q.37 The number of possible min-heaps containing each value from {1, 2, 3, 4,5, 6, 7) exactly once is ‘Ans. (80) oes EXIT Q.38 Let N be the set of natural numbers. Consicer the following sets: P._Setof rational numbers (positive and negative). Q. Setof functions from (0, 1} to N R._ Sot of functions from N to {0 S. Set of finite subsets of N. Which of the sets above are countable? (@) QandS only (b) Pand S only (9) PandRonly (A) P.QandS only Page 26Inia Best Inatituce for IS, GATE & PSUs Ans. (d) P : Set of rational number -> countable Q : Set of functions from {0, 1} to N > N 0 can be assigned in N ways 1 can be assigned in N ways There are N x N functions, cross product of countable set in countable. R : Set of functions from N to (0, 1) 123456 Each of thus boxes can be assigned to 0 or 1 so each such function is a binary number with infinite number of bits. Example: 0000 .... is the binary number corresponding to 0 is assigned to all boxes and so on Since each such binary number represents a subset of N (the set of natural numbers) by characteristic function method, therefore, the set of such function is same as power set of N which is uncountable due to Cantor's theorem, which says that power set of a countably infinite set is always uncountably infinite. S : Set of finite subsets of N -> countably infinite since we are counting only finite subsets. So P, Q and S are countable. Q.99 Consider the unsigned 8-bit fixed point binary number representation below: by bg by by by. by b, by where the position of the binary pointis between b, and b,. Assume b,'s the most significant, bit. Some of the decimal numbers listed below cannot be represented exactly in the above representation: (31.500 (i) 0875 (i) 12.100 (v) 3001 Which one of the following statements is true? (@) None of i, i), i), (iv) can be exactly represented (0) Only (i) cannot be exactly represented (©) Only (ii) and (iv) cannot be exactly represented. (@) Only () and (ji) cannot be exactly represented Eee aneInds Best Iaeeuee tor ES, GATE & PSUs SRA Ans. (c¢) Binary code: (b, by by by By. by by By) (B1.5)yq = (1111.1), (0875),. = (0.111), (12.100}y5 = (01100.000110 t Only 2 bits of fraction space avaiable 0 cant bo stored, (8.001),, = (00011.000000......), It is also not accurate storage, @.40 Given a language L, define L! as follows: = Ke} Ls LL for alli> 0 The order of a language L is defined as the smallest k such that LK = L*** Consider the language L, (over alphabet 0) accepted by the following automaton. ° o The order of L, is Ans. (2) We need to find smallest value of k which satisfies rie o of) = + (00 Ty k= 0: p=) = € = L, which is false. So order is not 0 Ty k=1 Lt=L? = teh, Now, L? = (€ +0 (00) (€ + 0 (00) = € + 0 (00)* + 00 (00)" = 0° Clearly lel, So order is not 4 Ty k= 2 Leeks Now, Lp=L2.L, = O'(e +0 (00)*) = 0° Clearly Lpelz=o (G0 order of L, is 2)Inia Best Inatituce for IS, GATE & PSUs Q.41 A lexical analyzer uses the following patterns to recognize three tokens T,, T, and T, over the alphabet {a, b, Ty: a? (olojra T,: b? (alc)*b Ty: 6? (bla)*c Note that x?’ means 0 or 1 occurrence of the symbol x. Note also that the analyzer outputs the token that matches the longest possible prefix Ifthe string bbaacabc is processed by the analyzer, which one of the following is the sequence of tokens it outputs? (a) TT, (o) TT, © TT, ) TO Ans. (d) Ans is T,T, because from first T, is taken trom second T, [abd] is taken, longest possible prefix. Hence T,T, token output Q.42 Let Gbe a graph with 100! vertices, with each vertex labelled by a distinct permutation of the numbers 1, 2, .....100. There is an edge between vertices u and vif and only if the label of u can be obtained by swapping two adjacent numbers in the label of v. Let y denote the degree of a vertex in G and z denote the number of connected ‘components in G. hen, y + 10z Ans. (109) The graph has 100! vertices which each vertex labelled by one of the 100! permutation, Let us find degree of each vertex. Let us take a vertex whose labelling is say 1,2,3.4.....100. Now it will be connected to all vertices where exactly 2 of the adjacent numbers al swapped The two swapped numbers could be (1, 2), (2, 3), (3, 4)... ete. upto (29, 100) which makes for 99 edges for each such vertex So the graph is a regular graph with each vertex connected to 99 other vertices So y=99 The number of connected components = z= 1 since we can go from any vertex to any other vertex by only swapping 2 adjacent number at a time, many times i.e. there is a path from any vertex to any other verlex. Graph is connected. $0 z So y+ 107 = 99 + 10x 1 = 109 Eee aneGeneral Studies & Engineering Aptitude Batches for India's Best Institute for IES, GATE & PSUs Syllabus Covered Batch Details Batch Type Commencing from Venue 20" Feb, 2018 25th Feb, 2018 Timing Regular Batch Ghitorni Centre (Delhi) | 8:00 AM to 12:00 Noon, Weekend Batch Ghitorni Centre (Dethi) 8:00 AM to 5:00 PM Ex. MADE EASY Students Rear Seetiie Enrolled in Postal, Rank Improvement, Conventional, GS, Post-GATE, GATE, |+G-+P Batches: 22,500 GS & Engg Aptitude Books willbe issued + GS & Engg Aptitude Books wil NT be issued. + Interested students can avail books by paying the foo of Rs. 2,000) 16,500 Documents Required ADMISSION OPEN 44-A/1, Kalu Sarai, Sarvapriya Vihar, New Delhi - 110016 * 2 Photographs + Valid photo ID proof * Ex MADE EASY students should produce their MADE EASY ID card © 011-45124612 @® wwwmadeeasy.inIndias Best Inatiute for ES, GATE & PSUs PELE Le aed Q.43 The instruction pipeline of a RISC processor has the following stages. Instruction Fetch (IP), Instruction Decode (1D), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 36 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock oycle each, Assume that there are no data hazards and no control hazards, The number of clock cycles required for completion of execution of the sequence of instructions is Ans. (219) Te) 1 1 1 3 4 Tye) 1 1 1 2 4 Tes) 4 4 4 4 4 pile 1+1434127 I, 7, | USually takes 1 cycle each dus to overlapping execution but /,(PO) stage takes ls 2 cycles so, add “1” cycle extra (2 + 1) = 74241 123 4567 8 8 10 +; [1 [ 10 oF Po| Po] Po] wal te |_ [ie [0] 0F| oF | oF | Po] Po] wa b IF | 10| 10 | 1 | oF | oF | Pol Po| FD OF PO We hat 43a 4 bh1ot 4 34 bhotot 4 24 hott 4 2 4 ce wo1o1 4 44 I Type 1 ~ 2 instruction Type 2 ~ 2 instruction Type 3 ~ 2 instruction Iit+t4+t4+34127 1 1 + 2 extra oycles = Jy 1 +1 extra cycles Ig 1+ 1 extra cycles = 2 Ig: 1 extra cycles 1 extra cycles Eee aneQ.4a Ans. am Inia Best Inatituce for IS, GATE & PSUs 123 4 5 67 8 9 1H 213 4 15 16 1, [iF [1 [or] Po] Po| 12 | [iF [1] oF] oF| oF] Po| Pol Pol wa 8 iF | 10 | 10| w [oF | oF | oF | PO] PO|wa| 4 iF [ie [1 [1 [0 | w [oF | oF [Po] Po| wal 5 1 [|r | 10 10] oF | oF | Pol wa % 1 [F [10] ww [oF| Po] wa) In this way, if we compute 100 instruction number of cycles required is lt ID OF PO WB > 141414 [40x 3) + (85 x 2) + (25x +1 = 219 eo; sR Consider the following solution to the producer-consumer synchronization problem. The shared butfer size is N. Three semaphores empty, full and mutex are defined with respective intial values of 0, N and 1, Semaphore empty denotes the number of available slots in the buffer, for the consumer to read from. Semaphore full denotes the number of available slots in the butfer, for the producer to write to. The placeholder variables, denoted by P, Q, R and S, in the code below can be assigned either empty or full. The valid semaphore operations are: walt () and signal () Producer ‘Consumer eof of wait (PI: watt (R); wait (mutex): walt (mutex): ibd item to buffer {Consume item from buffer signal (mutex); signal (mutex); signal (Q) signal (5) white (1) while (1); Which one of the following assignment to P, Q, R and S will yield the correct solution? (2) P: full, Q: full, R: empty, S; empty (b) P: empty, Q: empty, R: full, S: ful (©) P: full, Q: empty, A: empty, S: full (a) P: empty, Q: full, R: full, S: empty (c) Full = N, empty = 0, mutex = 1 ‘© Initially buffer will be empty, so consumer should not start first, so option b, D are eliminated ‘+ With option A consumer will never consume the item, so itis wrong + Option’c' is correct answer which proper functionality of produce and consumer. oe EEITIndia Beat Inaeiute for ES, GATE & PSUS peer ari Por ery Q.45 Consider the minterm list form of a Boolean function F given below FIP Q, R, S) = Em(0, 2, 5, 7, 9, 11) + d{G, 8, 10, 12, 14) Here, m denotes a minterm and d denotes a don't care term. The number of essential prime implicants of the function F is Ans. (3) F(P.Q,R,S) = Em(O, 2, 5, 7, 9, 11) + (3, 8, 10, 12, 14) Number of EPI = 3 Q.46 Consider the following undirected graph G: Bhs gfe a\ 3 . Choose a value of x that will maximize the number of minimum weight spanning trees (MWSTs) of G, The number of MWSTs of G for this value of x is Ans. (4)Qa7 Ans. a8 Inia Best Inatituce for IS, GATE & PSUs Consider the following parse tree for the expression a#b$cSditeM, involving two binary operators $ and #. * a N a™N 8, # /\ /N\ S a@e f /\ bos Which one of the following is correct for the given parse tree? (a) $has higher precedence and is left associative; # is right associative (b) # has higher precedence and is left associative; $ is right associative (©) Shas higher precedence and is left associative: # is left associative (A) # has higher precedence and is right associative: $is le't associative (a) If any given parse tree or syntax free low level operators having higher precedence than upper level operators Hence here $ is higher precedence than #. $ is left associative because in the sub expression b $¢ $d, b § c will be evaluated first as per given tree As per the given tree structure right # is higher precedence than left # Hence it is right associative. Assume that multiplying a matrix G, of dimension p x q with another matrix G, of dimension qxrtequires par scalar multiplications. Computing the product of nmatrices G,G,G, .. G, can be done by parenthesizing in different ways. Define G, G,,, as an explicitly computed pair for a given paranthesization if they are directly multiplied. For example, in the matrix multiplication chain G,G,G,G,G,G, using parenthesization (G\(G,G,)(G,(G,G,)). G,G, and GG, are the only explicitly computed pairs. Consider a matrix multiplication chain F,F,F,F,F,, where matrices F,, F,, Fy, F, and Fi, are of dimensions 2 x 25, 25 x 3, 3 x 16, 16 x 1 and 1 x 1000, respectively. In the parenthesization of F,F,FFaF that minimizes the total number of scalar multiplications, the explicitly computed pairs is/are (@) FFand FF,only (b) FFonly (©) FFonly (0) FFand F,Fonly (ce) Eee aneag Ans. Q.50 am Indias Best Inatiute for ES, GATE & PSUs peer ari Por ery In a system, there are three types of resources: E, F and G. Four processes P,, P, P, and P, execute concurrently, At the outset, the processes have declared their maximum resource requirements using a matrix named Max as given below. For example Max{P,, F] is the maximum number of instances of F that P, would require, The number of instances of the resources allocated to the various processes at any given state is given by a matrix named Allocation Consider a stale of the system with the Allocation matrix as shown below and in which 3 instances of E and 3 instances of F are the only resources available. ‘Allscation Max ElFle ElFlo Plt [ols Pol 4] 3 [4 Plt [4 [2 Plz (4/4 F(t [o[s Pt [3/3 Ps[2 [| Pls l4 [4 From the perspective of deadlock avoidance, which one of the following is true? (@) The system is in safe state (b) The system is not in safe state, but would be safe if one more instance of E were available. (©) The system is not in safe state, but would be safe if one more instance of F were available. (d) The system is not in safe state, but would be safe if one more instance of G were available (a) Maxneed | Curent alocation| Gurrent avaliable | Remaining need elr[c| e| F [c | eo] role] e| ro Pl4tsia[+]o[+|4{s[1[s|s]o Pl2fti4{+]1[2| 5] s|4|1|o]2 Plifsis{1]o]3|s| «| s|o| so Plsl4{7[2]o],o)] 8] «| s|3| 4] Safe sequence: P,, P,, P,, Py Safe state Serene meer mencio tient setrim erecta rarer c(omecrnoc 2:13 (oes) values. Which one of the following queries is NOT equivalent to Q? @) o9.5(re< 8) (©) o4..(FLOJ 9) (c) rLOd(a,..(s)) (d) o,_,(r) LOUInia Best Inatituce for IS, GATE & PSUs Ans. (c) | a 2 2 a 4 44% a 4 44 % 6 8 % a6 t t Foreign key Primary key (Gheniqvary) real (ear) 2 B: 09. 5(r 245) Grr da (og .5(8) [A ial ll eeeF a D: 6g <5() 34s [A Option “c” query result not equal to given query.India Beat Inaeiute for ES, GATE & PSUS PELE Le aed Q.51 Consider the following C code. Assume that unsigned long int type length is 64 bits. unsigned long int fun (unsigned long int n) { unsigned long int i, j= 0, sum = 0, for (i =m; i> 1; 1 = i2) jae for (; /> 1; j = jf2) sum+#: return (sum); } The value returned when we call fun with the input 2%° is (a) 4 (b) 6 6 (a) 40 Ans, (b) Q.52 Consider the following languages 1. farbrorak| m+ p= n+ g, where m,n, p, gz 0} I. {anbrorak| m= nand p= q, where m,n, p, q2 0} UL, {arbrorae| m = n= pand p# q, where m,n, p, q2 0} IV. {arbrota?| mn = p+ g, where m,n, p, q2 0} Which of the language above are context‘ree? (a) Land IV only (b) | and I only (©) Hand Ill only (d) land IV only ‘Ans. (b) |. {ambrora#|m + p= n+ qhis clearly CFL since, we can rearrange the equation as m-1n+ p~q=0 which can be done by push, pop, push and pop and check if stack is empty at end 11. {ambrerat| m = n and p = q) is clearly CFL since, one comparison at a time can bbe done by pda II. {ambrerds| m = n= pand p+ gis not CFL since m= which cannot be done by PDA. IV. {a™b*oPa#| mn = p + g} is not a CFL, since mn involves multiplying number of a's and number b's which cannot be done by a PDA. So, only | and Il are CFL’. = pis a double comparison eo: ¢EMEIT Q.53_ A processor has 16 integer registers (RO, R'. .... R15) and 64 floating point registers (FO, F1, ..., F63). It uses a 2-byte instruction format. There are four categories of instructions: Type-1, Type-2, Type-3 and Type-4, Type-1 category consists of four instructions, each with 3 integer register operands (3Rs). Type-2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type-3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R+1F). Type-4 category consists of N instructions, each with a floating point register operand (IF), he maximum value of N isInia Best Inatituce for IS, GATE & PSUs Ans. (32) Instruction size Type | instruction design: 16 bit rei opcode] IR | IR | IR Tot ABH FBR FBR Number of operations = 24 =16 oD Free opcodes = 16 - 4 =12 Type Il instruction design: tebe opcode] FR | FR ao SBR Br Free opcodes after type 1 instruction =12 Free opcodes after type 2 instruction =12-8 =4 ‘Type Il instruction design: tet opcode] IR | FR oR ABR ABE Expand opcode size = 6 bil J Number of opcodes = 4 x 2? =16 Number of free opcodes after type 3 instruction = 16-14 =2 Type IV instruction design: 16. [ovcoae] FR Tb BBE Expand opcode size = 10 bit v Number of opcodes = 2 x 24 =India Beat Inaeiute for ES, GATE & PSUS peer ari Por ery Q.54 Consider a storage disk with 4 platters (numbered as 0, 1, 2 and 3), 200 cylinders (numbered as 0, 1, ..., 199) and 256 sectors per track (numbered as 0, 1, ...., 256). he following 6 disk requests of the form [sector number, cylinder number, platter number] are received by the disk controller at the same time [120, 72, 2], (180, 134, 1], [60, 20, 0}, (212, 86, 3), (86, 116, 2], [118, 16, 1 Currently the head is positioned at sector number 100 of cylinder 80 and is moving towards higher cylinder numbers. The average power dissipation in moving the head over 100 cylinders is 20 miliwatts and for reversing the direction of the head movement once is 15 milliwatts, Power dissipation associated with rotational latency and switching of head between different platters is negligible. he total power consumption in millwatts to satisfy al of the above disk requests using the Shortest Sock Time First disk scheduling algorithm is Ans. (85) (86 — 80) + (86 - 72) + (134 — 72) + (134 - 16) + 62 + 118 + 14 = 200 100 - 20 200 > 7 200 200, 29 700 * 3 direction changes 3 x 15 = 45 40 + 45 = 85 °° EE Eee aneInia Best Inatituce for IS, GATE & PSUs 1 Q.85 Consider a matrix P whose only eigenvectors are the multiples of (:] Consider the following statements 1. Pdoes not have an inverse. Il, Phasa repeated eigenvalue. III, Pcannotbe diagonalized Which one of the following options is correct? (@) Only! and Ill are necessarily true (b) Only Il is necessarily true (©) Only! andl arenecessatily true (4) Only Il and Ill are necessarily true Ans. (d) Only Eigen vector is [ tiples mean: eigen value is repeated since if eigen values were distinct we will get one more independent eigen vector. So, II Phas repeated _ yet it is invertible. Ill is true since if a 2 x 2 matrix has only one linearly independent eigen vector, surely it cannot be diagonalized. °° EEE Eee aneNEXT IAS BIG LEARNINGS MADE EASY AN INITIATIVE OF MADE ERSU GROUP + UNDER THE GUIDANCE OF Wr. 8, SINGH (6MD, MADE EASY GROUP] © QualityTeaching * WellPlannedCurriculum — + Professionally Managed > General > Regular Batches: Regular Batch 29 May / 18” June, 2018 Commencing from , 15" Feb, 2018 Weekend Batches 23" June, 2018 Peetu Ine ke Se) Deere Wee ECan eigen Features: © Classes to be taken by renowned faculty group. ADEE Geert) Targeted, focused and current based approach. Cres Inclusive of Test Series and detailed study material Provision of regular interaction with faculty, through NEXT IAS online learning platform, Well framed modules with systematic subject sequence. Timely completion of syllabus giving ample time for revision. Daily news & editorial updates (with analysis) of important newspapers. Weekly test for self appraisal for both Pre and Main exam. Facility of course fee payment in installments. PANT) CIES er ere erat Seer eI hearer Creer a Pee eer eer ner oc esr nized eer eee ete ea oe See Deer eer Ree at ree eer tr ) info@nextias.com cee Naa ately