MOS Transistor Theory nMOS Transistor

• Two types of transistors • If the gate is “high”, the switch is on

nMOS • If the gate is “low”, the switch is off

pMOS
Drain

• Digital integrated circuits use these

Gate g=0
transistors essentially as a voltage
controlled switch Source
g=1

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nMOS Transistor nMOS Transistor

MOS: Metal Oxide Semiconductor
Cross Section
Gate oxide
Polysilicon
Gate
Source Drain Field-Oxide
n+ n+ (SiO2)
L
Silicon Dioxide
SiO2 p substrate

Bulk (Body)

Gate
Source Drain
Cross-section of an n-type transistor B

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nMOS Transistor nMOS Transistor

Top View
• n areas have been doped with donor ions
Polysilicon
Gate
of concentration ND - electrons are the
Source Drain majority carriers
n+ L n+ • p areas have been doped with acceptor
W ions of concentration NA - holes are the
p substrate majority carriers

Bulk (Body)

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 nMOS Transistor nMOS Transistor

Gate oxide
Polysilicon Polysilicon
VGS ≤ 0
Gate Gate _
Source Drain Source Drain +
- - + + - - - - + + - -
+ + + + + + + + + + + +

+ + + + + + + + + + + +

Accumulation Mode

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nMOS Transistor nMOS Transistor

Depletion Region Inversion Region

Polysilicon Polysilicon
VGS ≤ VT VGS > VT
Gate Gate
+ +
Source Drain Source Drain
_ _
- - - - - - - - - -
+ + + + + + + + + + + +

+ + + + + + + + + + + +

Depletion Mode Inversion Mode

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nMOS Transistor nMOS Transistor

Depletion Region
Inversion Region
Polysilicon
VGS > VT
Gate
+
Source Drain _
- - - -
+ + + + + +

+ + + + + +
n-channel enhancement MOS

Inversion Mode

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 Threshold Voltage Threshold Voltage
VT = VT 0 + γ ( − 2Φ F + VSB − 2Φ F )

• Dependent on • γ is the body-effect coefficient and controls the impact

of the source to bulk voltage

Gate conductor material

Gate insulator material
• Φ F is the Fermi potential and is dependent on doping
levels

Channel Doping
• Fermi potential: potential difference between Fermi

Voltage difference between source and body level and intrinsic Fermi level in the bulk of
semiconductor.

kT  N A 
ΦF = ln 
q  ni 
k: Boltzmann constant, T: temperature,
q: unit (electron) charge
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pMOS Transistor pMOS Transistor

Gate oxide
Polysilicon
Gate
Source Drain
+ + - - + +
- - - - - -

- - - - - -

Accumulation Mode

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Source vs. Drain nMOS Transistor

Drain Source
Drain

Gate Gate Ids Gate +

Ids VDS < VGS - VT VDS < VGS – VT
_
+ VGS – VDS > VT
_ VGD > VT
VGS > VT
Source Drain
Source
nMOS: node with a higher voltage pMOS: node with a higher voltage
is drain, VD > VS is source, VS > VD Linear mode

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 nMOS Transistor MOS Transistor Characteristics
Linear Mode:
• VGS>VT and VGD>VT
Drain
• Assume that VT is constant

Gate 
+
VDS > VGS - VT VDS > VGS – VT V2 
+
_
VGS – VDS < VT I DS = kn (VGS − VT )VDS − DS 
_ VGD < VT  2 
VGS > VT

Source • kn’= ( µ nCox ) is called the process transconductance

parameter
Saturation mode • Gain factor of nMOS: kn = kn’ W/L

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Example MOS Transistor Characteristics

Saturation Mode:
• µn= 600 cm2 / V s
• VGS>VT and VGD<VT
• Cox = 7 x 10-8 F / cm2
• Assume that VT is constant
• W = 20 µm
• L = 2 µm
(VGS − VT )2
• Kn = µn Cox W/L = 0.42 mA / V2 I DS = kn
2

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In Summary I-V Characteristics

-4
x 10
6
VGS= 2.5 V
• Cutoff region (VGS<VT)
5

I DS = 0 Linear Saturation
• Linear region (VGS>VT, VDS<VGS-VT or VGD>VT ) 4
VGS= 2.0 V
IDS (A)

 V2  3
I DS = k n (VGS − VT )VDS − DS  VDS = VGS - VT
 2 
2
VGS= 1.5 V
• Saturated region (VGS>VT, VDS>VGS-VT or VGD<VT )
1
VGS= 1.0 V
(VGS − VT ) 2
I DS = k n 0
2 0 0.5 1 1.5 2 2.5
VDS (V)

Long channel transistor (L = 10µm)

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 MOS Transistor Secondary Effects

• Cutoff region (VGS<VT)

• Body effect
S D
• Channel-length modulation
• Linear region (VGS>VT, VDS<VGS-VT) • Drain punch-through
• Short channel effect
S D
• Velocity saturation
• Saturated region (VGS>VT, VDS>VGS-VT)

S D

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Body Effect Channel-Length Modulation

• We previously assumed a constant L
• We assumed that VSB=0 - i.e. the source
potential equals the substrate potential • In reality, when VDS > (VGS-VT), the
• In certain situations, this assumption is not channel is pinched off and the effective
true channel length is reduced.
• Net effect is that IDS is not constant in the
• Has the effect of raising the threshold
saturated region.
voltage
• A negative bias on the well or substrate causes Source Drain
the threshold to increase - - - -
VDS > (VGS-VT) + + + + + +

+ + + + + +

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MOS Transistor Channel-Length Modulation

-4
x 10
2.5

• Cutoff region (VGS<VT) VGS= 2.5 V

2
I DS = 0
• Linear region (VGS>VT, VDS<VGS-VT) 1.5
VGS= 2.0 V
I DS (A)

 V2  Linear
I DS = kn (VGS − VT )VDS − DS  VGS= 1.5 V Relationship
 2  1

• Saturated region (VGS>VT, VDS>VGS-VT)

0.5 VGS= 1.0 V

(V − V ) 2
I DS = k n GS T (1 + λVDS )
2 0
0 0.5 1 1.5 2 2.5
VDS (V)

Short channel transistor (L = 0.25µm)

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 MOS Transistor Short Channel Effect
• Cutoff region (VGS<VT)
• At small gate lengths, electric field becomes
S D more pronounced
• Linear region (VGS>VT, VDS<VGS-VT) • Electrons get excited with enough energy to
cause a substrate current
S D • This causes change of transistor parameters -
• Saturated region (VGS>VT, VDS>VGS-VT) threshold voltage, current flow, etc.

S D

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Velocity Saturation MOS Transistor

• Cutoff region (VGS<VT)

• Assumption was that carrier velocity is I DS = 0
proportional to electric field
• Linear region (VGS>VT, VDS<VGS-VT)
• When channel is small, and the voltage is
large, the velocity can saturate  V2 
I DS = k n (VGS − VT )VDS − DS 
 2 
 µ nξ ξ < ξc Saturated region (VGS>VT, VDS>VGS-VT)
υ = •
µ nξ c ξ > ξ c
 V2 
ξc is value of electric field at which velocity saturates I DS = kn (VGS − VT )VDSAT − DSAT 
 2 

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Velocity Saturation MOS Gain Characteristics

ID
Long-channel device dI DS
• Transconductance gm =
dVGS
VGS = VDD

Cutoff region
Short-channel device gm = 0

Linear region
g m = knVDS

Saturated region

V DSAT VGS - V T VDS g m = k n (VGS − VT )

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 nMOS Transistor pMOS I-V
-4
x 10
0
• Cutoff region (VGSn<VTn) VGS = -1.0V

I DSn = 0 -0.2
VGS = -1.5V
• Linear region (VGSn>VTn, VDSn<VGSn-VTn)
-0.4

IDS (A)
 V2 
I DSn = k n (VGSn − VTn )VDSn − DSn  VGS = -2.0V
 2  -0.6 Assume all variables
• Saturated region (VGSn>VTn, VDSn>VGSn-VTn) negative!
-0.8
VGS = -2.5V

(V − V ) 2
I DSn = k n GSn Tn (1 + λVDSn ) -1
2 -2.5 -2 -1.5 -1 -0.5 0
VDS (V)

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pMOS Transistor

• Cutoff region (VGSp>VTp)

I DSp = 0
• Linear region (VGSp<VTp, VDSp>VGSp-VTp)
 V2 
I DSp = − k p (VGSp − VTp )VDSp − DSp 
 2 
• Saturated region (VGSp<VTp, VDSp<VGSp-VTp)

(VGSp − VTp ) 2
I DSp = − k p (1 + λ VDSp )
2

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