Supplementary lecture notes 1

Hardware description languages

Hardware Description Languages or HDL are used to model and describe digital
electronic circuits. It can describe the circuit's operation, design and organization, and
allows testing to verify its operation by means of simulation.

Typically, HDLs are text based programming languages which look very much like
standard computer programming languages such as C++, VB. However, the main
difference is that they are used to describe the behavior of physical electronic
components and systems as opposed to abstract software variables and objects.

In the same that software components such as classes end controls can be developed and
reused via software libraries. HDL’s allow similar flexibility through the use hardware
predefined libraries which contain reusable hardware components (logic gates, adders
etc).

The two most widely used HDL languages are VHDL and Verilog.

VHDL
VHDL is a standardised and widely adopted hardware description language which allows
describing digital hardware at multiple levels ranging from large systems to single
components.

Levels of description
There are four major levels of hardware description, all but the layout level can be
described in VHDL:

Behaviour

This is the functional description of the system and the highest level in the hierarchy of
description. It describes the overall behaviour of the system without details such as clock
signals, signal transitions. The behaviour description is simulable but not synthesizable.

RTL
This stands for (Register Transfer Level) and is the next step down the hierarchy of
description. RTL description details sequential and combinational elements of the circuit
such as flipflops, as well as detailing their response to input, intermediate and clock
signals.
Logic

Logic level is the gate level, where exact components making the system are specified.
E.g. A JK flip flop can be specified at the RTL level without specifying which gates it is
made out of. At the logic level the exact gates are specified (E.g. NAND gates).

Layout
Layout level specifies the actual physical make up of the circuit by detailing the
technology used. The same NAND gates used in the logic level can have many possible
physical implementation such as TTL and CMOS.

Syntax and examples

In the same way languages such as C++ and VB have declarations and definitions of
given variables and functions, VHDL has a similar syntaxic structure with key words
such as “entity” used to declare a new circuit or system and the word “architecture” to
define the relationship between input and output.

1) Half Adder:

entity ha_en is
port (A,B:in bit;S,C:out bit);
end ha_en;

architecture ha_ar of ha_en is

begin
S<=A xor B;
C<=A and B;

end ha_ar;

2) Full adder:

entity fa_en is
port(A,B,Cin:in bit; SUM, CARRY:out bit);
end fa_en;
architecture fa_ar of fa_en is

component ha_en
port(A,B:in bit;S,C:out bit);