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1. Design, simulation and analysis of two input NAND and NOR gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nand_nor_top is
Port ( A1 : in STD_LOGIC; -- NAND gate input 1
A2 : in STD_LOGIC; -- NAND gate input 2
X1 : out STD_LOGIC; -- NAND gate output
B1 : in STD_LOGIC; -- NOR gate input 1
B2 : in STD_LOGIC; -- NOR gate input 2
Y1 : out STD_LOGIC); -- NOR gate output
end nand_nor_top;
library ieee;
use ieee.std_logic_1164.all;
entity Full_Adder is
port( X, Y, Cin : in std_logic;
sum, Cout : out std_logic);
end Full_Adder;
begin
TMP <= A xor B;
FA0:Full_Adder port map(A(0),TMP(0),OP, R(0),C1);-- R0
FA1:Full_Adder port map(A(1),TMP(1),C1, R(1),C2);-- R1
FA2:Full_Adder port map(A(2),TMP(2),C2, R(2),C3);-- R2
FA3:Full_Adder port map(A(3),TMP(3),C3, R(3),C4);-- R3
OVERFLOW <= C3 XOR C4 ;
Cout <= C4;
end struct;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity up_dn_counter_top is
Port ( CLK : in STD_LOGIC; -- input clock
-- LEDs to display count
LED : out STD_LOGIC_VECTOR (7 downto 0);
DIR : in STD_LOGIC); -- direction of counter (up or down)
end up_dn_counter_top;
-- clock divider
process (CLK)
begin
if (CLK'Event and CLK = '1') then
clk_div <= clk_div + '1';
end if;
end process;
-- up/down counter
process (clk_div(3), DIR)
begin
if (clk_div(3)'Event and clk_div(3) = '1') then
if (DIR = '1') then
count <= count + '1'; -- counting up
elsif (DIR = '0') then
count <= count - '1'; -- counting down
end if;
end if;
end process;
end Behavioral;
5. Design, simulation and analysis Mod-5 counter.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mod5 Is
PORT( CLK,CLR:IN BIT;
QOUT:BUFFER INTEGER RANGE 0 to 7);
END mod5;
END IF;
END IF;
END PROCESS;
END arc;
library ieee;
use ieee.std_logic_1164.all;
entity ROM is
port ( address : in std_logic_vector(3 downto 0);
data : out std_logic_vector(7 downto 0) );
end entity ROM;