Design and Analysis of Integrated Buck-Boost-Buck Type Unity

Power Factor Converter for Low Power Applications

Abstract– An integrated buck-boost-buck (IB3) converter is proposed as a variable DC power

supply from an AC source with unity input power factor for the low power applications. This
converter is formed by the integration of a conventional buck-boost converter (input side)
along with a buck converter (output side), with a common switch. The advantages of IB3
converter are well regulated output voltage with extensive voltage conversion range along
with unity input power factor and suitable for low-power applications (<100 W) with
universal range of input voltages (90–265 Vrms). The proposed converter configuration is
designed in such a way that the input buck-boost division is operated in discontinuous current
conduction mode (DCM) along with power factor correction (PFC) at ac mains and the buck
division is operated in continuous current conduction mode (CCM). A comprehensive
analysis is carried out for the IB3 converter so as to obtain the essential design equations. An
example for a 100W, 230V/60V 50Hz converter is designed using MATLAB/SIMULINK
software in order to validate the effectiveness of the proposed converter. A laboratory model
has been developed to confirm the simulation results.
Key words: ac-dc converter, buck-boost-buck, integrated converter, power factor
correction (PFC), low power applications

I. INTRODUCTION

Currently ac/dc converters have been extensively used in numerous applications, such
as solar energy applications and utilizations, battery charging for electric vehicles, battery
energy storage systems (BESSs), renewable energy sources-utility interface for example solar
PV etc., adjustable speed drives (ASDs), uninterrupted power supplies (UPSs) and switch-
mode power supplies (SMPSs), lighting systems and in process technology such as welding
units, electroplating, etc., and power source for telecommunication systems, LED drivers,
measurement and test equipments, wireless communications, etc. [1]–[3]. To meet the
international standard requirements (EN/IEC 61000-3-2, IEEE 519) the input PFC system is
essential for ac/dc converters. The merits of PFC converters are, enhanced PF, low harmonic
distortion, and tightly regulated dc voltages. Conventional PFC based ac/dc converters
normally contain of two stages, first stage performs the PFC operation and the second stage
(DC-DC regulator) is used to supply dc voltage with low ripple content [4]–[7]. With this
two-stage configuration, the ac/dc converters need two separate control techniques, which
increase the cost and complexity of the converter. The conventional two-stage topology also
suffers to produce high efficiency along with good reliability [8]–[9]. To eliminate all the
above complexities, single-stage integrated ac/dc converters have been developed [9], by
combining a DC-DC regulator with the PFC converter using a common switch.

Various single-stage PFC configurations have been recently proposed using one
active switch with a simple control loop. However, because of the unregulated voltage of the
energy storage capacitor, single-stage converters suffered due to high voltage stress on the
switching element. So, a high voltage rating switch along with bulky capacitor is needed for
the single-stage ac/dc converter which increases the cost [10]. This also effects the efficiency
as well as the reliability. For that reason the single-stage PFC approach is limited to 450V dc.
The general schematic representation of single stage ac/dc converter is shown in Fig. 1. A
number of methods have been initiated in [11]–[20] in order to restrict the dc voltage of the
intermediate energy storage capacitor. The majority of these papers use the boost converter as
a PFC. This configuration is found to be appropriate for low output-voltage applications
(PCs, SMPS loads), since a step-down transformer would be required at the input stage of the
converter for load voltage regulation.

Single Stage
Rectifier DC/DC Load
AC
Unit converter C0

Fig. 1 General representation of single stage ac/dc converter

Alternatively, conventional single-switch converters such as buck–boost, Cuk, and

SEPIC converters [21] are suitable for PFC along with step-down conversion. Nevertheless
they also suffer from high component stresses and low efficiencies than that of the boost
converter. For a wide range of input voltages the buck–boost configurations also are not
suitable to provide low output dc voltages. In addition to that the active switch usage of
conventional buck–boost configurations is very poor with very low duty ratios [22].
 This paper focuses on these issues based on the earlier research on single-stage PFC
configurations using single-switch for universal input voltage ranges for the well-regulated dc
voltage applications [23]. This is done by integrating a buck–boost converter as input PFC
converter with an output buck converter for fast and well regulated dc load voltages, as
shown in Fig. 2. Conversion range of an ac/dc converter can be improved drastically if the
conversion ratio M (D) (= V0 / VIN) as a function of duty cycle (D) could be quadratic
function [24]. This can be achieved by integrating or cascading two dc/dc converters.

Generally boost and buck–boost converters are preferred for PFC due to their
capabilities of generating high power factor at the input supply terminals, when they are
operating in the discontinuous current conduction mode (DCM). However buck–boost
configuration is mostly favored because of its potential for getting buck voltage conversion.
The buck converter is chosen at the output side converter due to its step-down ability. As a
result, a high step-down ratio can be attained. The proposed integrated buck-boost-buck (IB3)
converter is designed so that the buck-boost division is operated in DCM to attain Unity
power factor (UPF) at input ac mains and the buck converter is operated in continuous
current conduction mode (CCM). The advantages of IB3 converter are as follows

1. Fast and well regulated dc output voltage is achieved with extensive voltage conversion
range.
2. Unity input power factor (without input filter), can be achieved.
3. Well suitable for universal range of input voltages (90–265 Vrms) for low-power
applications (<100 W).
4. Higher efficiencies can be attained with less voltage stress on the switching element.

Section-II represents circuit configuration and operation of the proposed configuration

and the important equations. In section-III the theoretical analysis is illustrated with
necessary equations. The modeling and design considerations are presented for the proposed
converter in section-IV. Discussion on simulation and experimental results are presented in
section-V to validate the performance of the proposed model. Conclusions based on the
performance analysis are given in section-VI.
 II. PROPOSED IB3 CONVERTER
A. Proposed converter circuit configuration
Fig. 2 shows the circuit diagram of the IB3 converter topology. As described in the
introduction, the converter is an integration of the buck-boost converter with the buck
converter in cascade. The buck-boost converter placed at input side comprises of D1, Lr, Cr
and a switch (S), and the buck converter which is placed at output comprises L0, D2, DF, C0
and switch. The value of inductor Lr is chosen to operate iLr (current through Lr) in
discontinuous current conduction mode (DCM) so that the average line current is
proportional to input line voltage, which makes the input power factor unity. The
Intermediate capacitor Cr value is chosen sufficiently small to decrease the voltage stress on
the switch S. The output (buck converter) inductance L0 value is selected to operate in
continuous conduction mode (CCM). By operating the output inductance L0 in CCM, the
output capacitance value C0 can be minimized.

iD1 D1 L0

- iL0
Cr vCr -
CENTER TAPPED Lr +
is TRANSFORMER
DFW1 + iLr
iSW
+ DF
v0 RL
AC Input

S C0
Vs Vin vSW
iDF
- i0
G

DFW2 D2 +
-
iD2
Fig. 2 Proposed single stage PFC Buck-Boost-Buck (IB3) converter

B. Steady-state operating modes

The steady-state operation of the IB3 converter have been divided into three modes
over a switching period (Ts = 1/fs) as shown in Figure 3.
 D1 L0

- iL0
Cr vCr -
Lr +
+ iLr
iSW
+ DF
v0 RL
S C0
vSW
Vin
- i0
G

- D2 +

iD2

(a) Mode I
iD1 D1 L0

-
Cr vCr -
+ iL0

+ iLr Lr

+ DF
iDF v0 RL
S C0
VSW
Vin
- i0

- D2 +

(b) Mode II
L0

iL0
-

DF
iDF v0 RL
C0

i0

(c) Mode III

Fig 3 Operating modes of IB3 converter (a) Mode-1 (b) Mode-2 (c) Mode-3
Mode-I [t0, t1]: Earlier to this interval, the current iLr through the inductor Lr is at zero level,
the diode D1 is reverse biased by the voltage across capacitor Cr and the diode DF carries the
load current i0. At the beginning of mode-I the switch S is turned on at t = t0, the current iLr
linearly increases from zero level. Switch S carries load current i0 and iLr. In this operating
mode the diodes D1 and DF continue to be reversed biased and D2 is forward biased. Fig. 3(a)
illustrates the operation of Mode-I along with the current directions.

When switch S is ON
𝑑𝑖𝐿𝑟
𝐿𝑟 = 𝑣𝑠
𝑑𝑡
𝑑𝑖𝐿0
𝐿0 = 𝑣𝐶𝑟 − 𝑣0 (1)
𝑑𝑡

Mode-II [t1, t2]: The switch S is turned off at t1, so the current iLr discharges through the
diode D1 via capacitor Cr transferring the inductive energy stored in Lr to the capacitor. In this
interval the diode D2 becomes reversed biased. The output inductor L0 delivers the energy to
the load through the freewheeling diode DF which is shown in Fig. 3(b). This mode of
operation will end when the current iLr reaches the zero level.

When switch S is OFF

𝑑𝑖𝐿𝑟
𝐿𝑟 = −𝑣𝐶𝑟
𝑑𝑡
𝑑𝑖𝐿0
𝐿0 = −𝑣0 (2)
𝑑𝑡

Mode-III [t2, t3]: During this mode the current iLr stays at zero level whereas current iL0
decreases continuously flowing through the freewheeling diode DF. The switch S will be
turned on before the current iL0 becomes zero, since L0 is operated in continuous conduction
mode (CCM). The converter remains in this mode until the switch is turned on again. This
mode of operation is shown in Fig. 3(c).

Considering d1 is duty cycle of switch ON, using volt-sec balancing principle at

inductors Lr and L0 in steady-state operation, voltage across the capacitor vCr and output
voltage v0 are given by
 𝑑1
𝑣𝐶𝑟 = 𝑣
1 − 𝑑1 𝑠
𝑣0 = 𝑑1 𝑣𝐶𝑟 (3)

Equation (3) is derived by equating the energy stored in the inductor Lr during the on
time (ton= d1Ts) equal to vsd1Ts to the energy delivered to the capacitor during off time (toff =
(1-d1) Ts) equal to vCr(1- d1) Ts. Similarly the input voltage to the buck circuit at the output is
vCr during on time and zero during off time giving rise to average output voltage v 0 equal to
d1 vCr.
Therefore the conversion ratio M (d1) can be derived as
𝑣0 𝑑1 2
𝑀(𝑑1 ) = = (4)
𝑣𝑠 (1 − 𝑑1 )

The steady-state operating waveforms for the proposed IB3 converter are shown in
Fig. 4 during one switching cycle.
 G MODE
ON

I II III I II
OFF
t
TS
iS

iLrp+iL0p
iSW

iLrp = (VS/Lr)d1Ts
iLr

iL0 IL0p CCM Mode

t
iD1 d1Ts d2Ts d3Ts

iD2
((VCr-V0)/L0)d1Ts
t

iDF

vSW VS +VCr
VS

t
t0 t1 t2 t3

Fig 4 Steady-state waveforms of proposed single stage PFC Buck-Boost-Buck converter

 III. THEORETICAL ANALYSIS OF IB3 CONVERTER

Consider that the supply voltage (vs) is sinusoidal, given as 𝑣𝑠 = 𝑉𝑆 𝑠𝑖𝑛𝜔𝐿 𝑡. The input
current is represents the current through the inductance Lr during the time interval d1Ts, where
d1 is the switch duty cycle over a switching period Ts. The rectified line voltage modulates
the input current, as presented in Fig. 5. During one switching period Ts, the input voltage 𝑣𝑠
can be assumed to be constant which is valid since the switching frequency fs (=1/Ts) is very
high. For the same reason the average input current of each pulse can be represented as the
instantaneous input current at the end of each pulse duration.
Therefore, the input current at line frequency is given as [1]:
𝑖𝑠𝑝 𝑑1 2 𝑉𝑠
〈𝑖𝑠 〉 = 𝑑 𝑇 = 𝑠𝑖𝑛𝜔𝐿 𝑡 (5)
2𝑇𝑠 1 𝑠 2𝐿𝑟 𝑓𝑠

where 〈𝑖𝑠 〉 is input current at time t, 𝑖𝑠𝑝 is the peak current of each current pulse, 𝑓𝑠 is
switching frequency, 𝑉𝑠 is the peak voltage of the input supply.

is
Not Scaled

t
Ts d1Ts
Line half period TL/2

Fig. 5 Modulated input current

Both input voltage and current waveforms are sinusoidal in shape and in phase, so input
power Ps is
1 𝑑1 2 𝑉𝑠 2
〈𝑖 〉
𝑃𝑠 = 𝑉𝑠 𝑠𝑝 = (6)
2 2𝐿𝑟 𝑓𝑠
For the given R load, the output power is
𝑣0 2
𝑃0 = (7)
𝑅
where 𝑣0 is output dc voltage
Assuming lossless converter, equating (6) and (7), the average output voltage 𝑉0 can be
obtained as

𝑑1 𝑉𝑠 𝑅
𝑉0 = √ (8)
2 𝐿𝑟 𝑓𝑠

IV. CONVERTER MODELING AND DESIGN

In this part, the design analysis of the converter main reactive components Lr, Cr, and L0 are
discussed. The output shunt capacitor C0 is large and is chosen to ensure proper ripple factor
for the output voltage. The dynamics of the IB3 converter during the three modes of operation
with the given R load can be represented as
|𝑣𝑠 | 𝑓𝑜𝑟 [𝑡0 , 𝑡1 ]
𝑑𝑖𝐿𝑟
𝐿𝑟 −𝑣
= { 𝐶𝑟 𝑓𝑜𝑟 [𝑡1 , 𝑡2 ]
𝑑𝑡
0 𝑓𝑜𝑟 [𝑡2 , 𝑡3 ]
−𝑖𝐿0 𝑓𝑜𝑟 [𝑡0 , 𝑡1 ]
𝑑𝑣𝐶𝑟
𝐶𝑟 = {𝑖𝐿𝑟 𝑓𝑜𝑟 [𝑡1 , 𝑡2 ]
𝑑𝑡
0 𝑓𝑜𝑟 [𝑡2 , 𝑡3 ]
𝑣𝐶𝑟 − 𝑣0 𝑓𝑜𝑟 [𝑡0 , 𝑡1 ]
𝑑𝑖𝐿0
𝐿0 = { −𝑣0 𝑓𝑜𝑟 [𝑡1 , 𝑡2 ] (9)
𝑑𝑡
−𝑣0 𝑓𝑜𝑟 [𝑡2 , 𝑡3 ]

Since C0 is assumed to be large, the average output voltage V0 will be fairly constant and C0
will not participate in the circuit dynamics. If the instantaneous values i Lr, iL0 and vCr given in
(9) are averaged over one switching cycle and are represented by ILr, IL0 and VCr, the above
differential equations can be modified as follows in terms of these average values.
The rate of change of ILr in the duration t0 to t1 (=Ton) is vs/Lr and the corresponding value in
the interval t1 to t2 (=T2) is given by VCr/Lr. Therefore the average rate of change of ILr in one
switching period (Ts) is given by
𝑑 𝑇𝑜𝑛 𝑇2
𝐼𝐿𝑟 = 𝑣𝑠 − 𝑉 (10)
𝑑𝑡 𝑇𝑠 𝐿𝑟 𝑇𝑠 𝐿𝑟 𝐶𝑟

Similarly the average rate of change of IL0 and VCr over one switching cycle are given by
 𝑑 −𝑅 𝑇𝑜𝑛
𝐼𝐿0 = 𝐼𝐿0 + 𝑉
𝑑𝑡 𝐿0 𝑇𝑠 𝐿0 𝐶𝑟
𝑑 𝑇2 𝑇𝑜𝑛
𝑉𝐶𝑟 = 𝐼𝐿𝑟 − 𝐼 (11)
𝑑𝑡 (𝑇𝑜𝑛 + 𝑇2 )𝐶𝑟 𝑇𝑠 𝐶𝑟 𝐿𝑜

The above equations (10) and (11) are expressed in state space matrix form in (12)
The state space model of the converter in terms of average quantities are given by
𝑑〈𝐼𝐿𝑟 〉 𝑑2
0 0 −
𝑑𝑡 𝐿𝑟 𝑑1
〈𝐼𝐿𝑟 〉
𝑑〈𝐼𝐿0 〉 𝑅 𝑑1
= 0 − [ 〈𝐼𝐿0 〉 ] + [𝐿𝑟 ] |𝑣𝑠 | (12)
𝑑𝑡 𝐿0 𝐿0 0
〈𝑉𝐶𝑟 〉
𝑑〈𝑉𝐶𝑟 〉 𝑑2 𝑑1 0
[ 𝑑𝑡 ] [(𝑑1 + 𝑑2 )𝐶𝑟 − 0
𝐶𝑟 ]
where d1=(t1-t0)/Ts and d2=(t2-t1)/Ts

The above equation is linear and time invariant and can be used for the analysis of the
dc-dc converter for small perturbations in the load resistance R and input voltage Vs.
The input voltage to the buck-boost converter considered in this paper is the rectified
ac voltage (refer to fig. 1). Because of this reason the input current pulses have the shape
shown in Fig. 5. The average values of the state variables in (12) for each switching cycle
will be varying. If these variables are averaged over a complete cycle of the input waveform,
their average values will remain constant when the circuit is in steady state. Therefore the
derivatives of these variables in (12) will become zero in steady state. The input voltage Vs
used in (12) is the rectified average value of the input voltage. This condition is utilized to
compute the values of the circuit parameters as discussed below.
As the input inductor Lr is operating in DCM,
𝑖𝑠𝑝
〈𝐼𝐿𝑟 〉 = (𝑑 + 𝑑2 ) (13)
2 1
𝑉𝑠
𝑖𝑠𝑝 = (𝑑1 𝑇𝑠 ) (14)
𝐿𝑟
Using (13) and (14)
2〈𝐼𝐿𝑟 〉𝐿𝑟
𝑑2 = − 𝑑1 (15)
𝑉𝑠 𝑑1 𝑇𝑠
Similarly from (6), input inductance Lr for the lossless converter is given by
𝑑1 2 𝑉𝑠 2
𝐿𝑟 = (16)
2𝑃0 𝑓𝑠
To calculate 𝑑1 , from (16):

√2𝐿𝑟 𝑓𝑠 𝑃0 𝑉0 2𝐿𝑟 𝑓𝑠
𝑑1 = = √ (17)
𝑣𝑠 𝑉𝑠 𝑅

Using (12) and (15), the capacitor Cr voltage (VCr) is calculated in terms of input voltage vs
and output current iL0.
From (13) and (14)
𝑉𝑠
𝐿𝑟 (𝑑1 𝑇𝑠 )
〈𝐼𝐿𝑟 〉 = (𝑑1 + 𝑑2 ) (18)
2
From (12)
𝐼𝐿𝑟 𝑑1
⁄𝐼 = (𝑑1 + 𝑑2 ) 𝑎𝑛𝑑
𝐿𝑜 𝑑2
𝑉𝐶𝑟 𝑑1
⁄𝑉 = (19)
𝑠 𝑑2
Combining (18) and (19)
𝑑1 𝑉𝑠 2
𝑉𝐶𝑟 = (20)
2𝐿𝑟 𝑓𝑠 𝐼𝐿0
For calculation of Cr and L0 the permissible ripple (∆𝑣𝐶𝑟 ) in the voltage across the capacitor
Cr and the permissible ripple ∆𝑖𝐿0 in the current in the inductance L0 are assumed.
The amplitude of the ripple voltage across the capacitor Cr (∆𝑣𝐶𝑟 ) is due to the load
current IL0 flowing through the capacitor during the on time Ton. Using equations (3) the
required value of Cr for the permissible ∆𝑣𝐶𝑟 is given in the following equation
(1 − 𝑑1 )𝑃0 𝑓𝑠
𝐶𝑟 = (21)
𝑣𝑠 ∆𝑣𝐶𝑟 𝑑1
The value of L0 given by (22) also depends on d1, similar to the capacitance voltage (𝑣𝐶𝑟 ):
(𝑉𝐶𝑟 − 𝑉0 )𝑑1
𝐿0 = (22)
𝑓𝑠 ∆𝑖𝐿0

However to design the converter, one of the variables has to be fixed, among VCr, Lr,
d1, and Cr since there are four unknowns governed by three independent equations (12). In
this proposed design, the value of d1 for a given switching frequency fs is assumed. Small
values of capacitor Cr results in large VCr for a given output power and this leads to higher
rating and higher switching losses for the device. Thus there is a tradeoff between small size
capacitor and the efficiency of the converter.
TABLE-I
 INPUT AND OUTPUT RATINGS OF THE PROPOSED CONVERTER
Parameter Value
Converter Input Voltage 60 Vrms
Input Line Frequency (fL) 50 Hz
Maximum Output Voltage (V0max) 154 V
Switching Frequency (fs) 10 kHz
Maximum Load Power 100 W
TABLE-II
DESIGNED VALUES OF CONVERTER COMPONENTS
Component Simulation values Experimental values
Lr 2.25mH 2.5mH
Cr 5uF 5.5uF
L0 50mH 53mH
C0 1000uF 1000uF
Centre tapped T/F 230/60-0-60 V 230/60-0-60 V
R 250Ω 250Ω
Switch - S 25N120NDH (1200V, 25A)
Diodes (D1,D2 & DF) MUR 30120 (1200V, 30A)

V. SIMULATION AND EXPERIMENTAL RESULTS

The proposed IB3 converter as shown in Fig. 1 is simulated with
MATLAB/SIMULINK software. The designed input and output ratings are specified in
Table-I. At the input side centre tapped transformer (230/60-0-60 Vrms) based full-bridge
converter is used as a rectifier unit. Based on the analysis discussed in earlier sections the
circuit components are designed. Input side inductor Lr value is designed to operate iLr in the
discontinuous current conduction mode (DCM). The Intermediate capacitor Cr value is
selected sufficiently low by allowing permissible ripple voltage (∆𝑣𝐶𝑟 ) and limiting the
voltage rating of the switching device. The output inductance L0 value is designed to operate
iL0 in continuous current conduction mode (CCM). A 100W, 230V/60V 50Hz Hardware
prototype of the IB3 converter has built to confirm the simulation results. Fig. 6 shows the
hardware implementation of the proposed converter. The simulation and experimental values
of the prototype are shown in Table II.
 Inductor Lr Output filter
Inductor L0
Diode D1
Intermediate
capacitor Cr
Switch

Resistive Load

Inverted Output
terminals

Diode D2

Output filter
Capacitor C0
Center-tapped
transformer Driver circuit
(230/60-0-60) V
FPGA Controller for
gate pulses

Fig. 6 Hardware implementation of the proposed converter

(a)

(b)
Fig. 7 Simulation waveforms of input line current and supply voltage (D1 = 0.25): (a) without
EMI filter (b) with EMI filter
 Fig. 7 shows simulation waveforms of input current and supply voltage under buck
mode operation (D1 = 0.25). From Fig. 7, it can be noticed that the input fundamental power
factor is unity without using the EMI filter (Fig. 7(a)) even though the input current is in the
form of pulses with sinusoidally varying amplitudes. With EMI filter, the measured input
current waveform is continuous and almost sinusoidal and the fundamental input power
factor is close to unity (0.9887). Fig. 8 shows the FFT analysis of the input current under
buck mode operation (D1 = 0.25). It is observable from Fig. 8 is that the total harmonic
distortion (%THD) in line current is less (2.34%) and this satisfies the international standard
(EN/IEC 61000-3-2, IEEE 519) requirements. This means the proposed converter is very well
suited for the buck mode (low voltage) applications also.

Fig. 8 FFT analysis of input current (buck mode (D1=0.25)).

Fig. 9 demonstrates the output voltage operating under buck mode (D1=0.25). With
25% duty cycle the converter produces 33 V average dc output voltage with a peak-to-peak
ripple of 0.46 V (= 1.4%) approximately. The average output dc voltage obtained using the
time domine analysis is fairly same as that obtained using (8). (Refer to table-III)
 Fig. 9 Simulated waveforms of output voltage: buck mode operation (D1=0.25)

Fig. 10 shows simulation waveforms of input current and supply voltage under boost
mode operation (D1 = 0.60). Operating under boost mode, it can be noticed that the
fundamental input power factor is unity for both with & without EMI filters (Fig. 10).

(a)

(b)
Fig. 10 Simulation waveforms of input line current and supply voltage (D1 = 0.60): (a)
without EMI filter (b) with EMI filter
 The experimental waveforms of input supply voltage and the input current with input
EMI filter are shown in Fig. 11. The measured input current is nearly sinusoidal and the input
fundamental power factor is unity.

Fig. 11 Experimental waveforms of supply voltage and line current with input EMI filter

Fig. 12 shows the FFT analysis of the input line current under boost mode operation
(D1 = 0.60). The THD of the input current is (%THD) 1.72% which satisfies the international
standards (EN/IEC 61000-3-2, IEEE 519).

Fig. 12 FFT analysis of input current (boost mode (D1=0.60)).

 Fig. 13 shows the output voltage with boost mode (D1=0.6) operation. With 60% duty
cycle the output average dc voltage is 82V with a peak-to-peak ripple of 1.3 V (1.6%)
approximately. (Refer to table-III)

Fig. 13 Simulated waveforms of output voltage: boost mode operation (D1=0.60)

Fig. 14 shows the simulation waveforms (over few switching cycles) of currents in all the
components of proposed IB3 converter operating under steady-state conditions. From Fig. 14
it can be observed that the waveforms obtained through time domine analysis are very similar
to the theoretical waveforms shown in Fig. 4. The inductor Lr is operating in discontinuous
conduction mode and L0 is operating in continuous conduction mode (see Fig. 14 (1)).

(1)

(2)
 (3)

(4)
Fig. 14 waveforms of the IB3 converter operating under steady-state conditions:
(Top to Bottom) (1) iL0 and iLr currents, (2) iD2 and iDF currents, (3) iLr and iD1 currents (4)
switch current (isw) and voltage (vsw).

The experimental waveforms of inductor currents iLr (DCM mode) and iL0 (CCM
mode) are shown in Fig. 15 for a few switching cycles.
 Fig. 15 Experimental waveforms of inductor currents iLr and iL0 respectively

Fig. 16 shows the simulated waveforms of the output voltage (v0) and capacitor dc
voltage (vCr). The average capacitor voltage (vCr) is around 135 V with a voltage ripple
(∆𝑣𝐶𝑟 ) of 40 V peak-to-peak approximately. Table-III shows the performance of proposed
converter for different duty ratios (D1) with nominal input voltage (Vs = 230/ 60-0-60 Vrms).

Fig. 16 simulated waveforms of output voltage and intermediate capacitor dc voltage (vCr) .
Fig. 17 Experimental waveforms of intermediate capacitor voltage VCr and output voltage V0

In addition, the measured waveforms of intermediate capacitor voltage VCr and output
voltage are shown in Fig. 17. From the figures it can be observed that the experimental
waveforms confirm the simulated results.

TABLE-III
PERFORMANCE OF IB3 CONVERTER FOR VARIOUS DUTY RATIOS

Input
DUTY OUTPUT % Pin Pout %
Fundam
RATIO (D1%) VOLTAGE (V0) RIPPLE (W) (W) Efficiency
ental P.F
20 1 26 1.0 3.3 2.7 81.4
25 1 33.1 1.4 5.1 4.4 86.3
35 1 47.4 1.6 9.9 9 91.2
50 1 68.3 1.6 19.9 18.7 94.1
60 1 82 1.7 28.3 26.9 95
65 1 94 1.7 37 35.4 95.6
70 1 116.4 1.7 57.3 54.2 94.6
75 1 151.3 1.8 99 91.6 92.5

Fig. 18 shows the efficiency plot of the proposed configuration for different duty
ratios with nominal input voltage and fixed load resistance. The maximum efficiency is
95.6% obtained at 65% of the duty ratio.
 Fig. 18 The efficiency of the converter for different duty ratios

Fig. 19 Efficiency of the converter for different values of output power

Fig. 19 shows the efficiency curve for different values of output power with constant
input voltage. Table-IV shows the performance of IB3 converter with different input voltages
(Vs) considering for universal applications (Vs = 90-265 Vrms). It can be noted that the
proposed converter has good efficiency with less ripple factor throughout the universal input
voltage range. Hence this IB3 converter is well suited for all universal voltage range
applications. Fig. 20 shows the efficiency plot of the proposed configuration for different
values of input voltage.
 TABLE-IV
Performance of IB3 converter with universal input voltage range
Input Fundamental P.F V0 (V) % Ripple % Efficiency
Voltage D1=0.25 D1=0.6 D1=0.25 D1=0.6 D1=0.25 D1=0.6 D1=0.25 D1=0.6
90 1 1 12.4 31.1 1.4 1.7 80.5 91
100 1 1 13.9 34.7 1.4 1.7 81.5 91.5
120 1 1 16.8 42 1.4 1.7 82.9 92.6
150 1 1 21.3 52.9 1.4 1.7 84.3 93.5
180 1 1 25.7 63.8 1.4 1.7 85.3 94.3
200 1 1 28.7 71.1 1.4 1.7 86.2 94.5
220 1 1 31.6 78.4 1.4 1.7 86.2 94.5
230 1 1 33.1 82 1.4 1.7 86.3 95
250 1 1 36.1 89.3 1.4 1.7 86.7 95
265 1 1 38.3 94.7 1.4 1.7 86.8 95

TABLE-V
PERFORMANCE OF IB3 CONVERTER WITH LOAD CHANGES
Load Fundamental P.F V0 (V) % Ripple % Efficiency
(Ω) D1=0.25 D1=0.6 D1=0.25 D1=0.6 D1=0.25 D1=0.6 D1=0.25 D1=0.6
200 1 1 29.8 74.6 1.8 2.1 87.2 95.1
220 1 1 31.2 77.1 1.6 2.0 86.9 95.1
240 1 1 32.5 80.3 1.5 1.8 86.6 95
250 1 1 33.1 82 1.4 1.7 86.3 95
260 1 1 33.7 83.6 1.4 1.7 86.2 95
280 1 1 34.9 86.6 1.3 1.5 85.8 94.9
300 1 1 36.1 89.6 1.1 1.4 85.5 94.8
320 1 1 37.2 92.5 1.0 1.4 85.0 94.8
 Fig. 20 Efficiency curve of the converter for different values of input voltage

Table-V illustrates the performance of IB3 converter with different loads (R = 200-
320 Ω) at constant input voltage. Thus the proposed converter shows good performance over
the different load conditions exhibiting enhanced efficiencies with less ripple factor. Fig. 21
shows the efficiency curve for buck and boost modes with different loads.

Fig. 21 Efficiency curve for buck and boost modes with different loads.
 VI. CONCLUSION
In this paper an integrated buck-boost-buck (IB3) converter is proposed as a variable
DC power supply from an AC source with unity input power factor at fundamental
frequency. The detailed operation and modeling of proposed converter are discussed.
Comprehensive analysis was carried out for the proposed converter to obtain the necessary
design equations for the low power applications. The effectiveness of the IB3 converter is
verified by modeling, a 100W, 230V/60V 50Hz converter using both software and hardware.
Experimental results obtained collaborate with the simulation results. The input current
%THD was measured, and they satisfied the international standards (EN/IEC 61000-3-2,
IEEE 519). Unity input power factor (UPF) at fundamental frequency is achieved for all
operating conditions along with fast and well regulated output voltage for lower duty ratios
also. The proposed converter is tested for universal input voltage ranges (90–265 Vrms) and
different load variations. These results showed that the converter has better efficiencies and
low output voltage ripple throughout the range.

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