PIC16F882/883/884/886/887: 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers

PIC16F882/883/884/886/887
28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers
High-Performance RISC CPU: Peripheral Features:

• Only 35 Instructions to Learn: • 24/35 I/O Pins with Individual Direction Control:
- All single-cycle instructions except branches - High current source/sink for direct LED drive
• Operating Speed: - Interrupt-on-Change pin
- DC – 20 MHz oscillator/clock input - Individually programmable weak pull-ups
- DC – 200 ns instruction cycle - Ultra Low-Power Wake-up (ULPWU)
• Interrupt Capability • Analog Comparator Module with:
• 8-Level Deep Hardware Stack - Two analog comparators
• Direct, Indirect and Relative Addressing modes - Programmable on-chip voltage reference
(CVREF) module (% of VDD)
Special Microcontroller Features: - Fixed voltage reference (0.6V)
• Precision Internal Oscillator: - Comparator inputs and outputs externally
- Factory calibrated to ±1% accessible
- Software selectable frequency range of - SR Latch mode
8 MHz to 31 kHz - External Timer1 Gate (count enable)
- Software tunable • A/D Converter:
- Two-Speed Start-up mode - 10-bit resolution and 11/14 channels
- Crystal fail detect for critical applications • Timer0: 8-bit Timer/Counter with 8-bit
- Clock mode switching during operation for Programmable Prescaler
power savings • Enhanced Timer1:
• Power-Saving Sleep mode - 16-bit timer/counter with prescaler
• Wide Operating Voltage Range (2.0V-5.5V) - External Gate Input mode
• Industrial and Extended Temperature Range - Dedicated low-power 32 kHz oscillator
• Power-on Reset (POR) • Timer2: 8-bit Timer/Counter with 8-bit Period
• Power-up Timer (PWRT) and Oscillator Start-up Register, Prescaler and Postscaler
Timer (OST) • Enhanced Capture, Compare, PWM+ Module:
• Brown-out Reset (BOR) with Software Control - 16-bit Capture, max. resolution 12.5 ns
Option - Compare, max. resolution 200 ns
• Enhanced Low-Current Watchdog Timer (WDT) - 10-bit PWM with 1, 2 or 4 output channels,
with On-Chip Oscillator (software selectable programmable “dead time”, max. frequency
nominal 268 seconds with full prescaler) with 20 kHz
software enable - PWM output steering control
• Multiplexed Master Clear with Pull-up/Input Pin • Capture, Compare, PWM Module:
• Programmable Code Protection - 16-bit Capture, max. resolution 12.5 ns
• High Endurance Flash/EEPROM Cell: - 16-bit Compare, max. resolution 200 ns
- 100,000 write Flash endurance - 10-bit PWM, max. frequency 20 kHz
- 1,000,000 write EEPROM endurance • Enhanced USART Module:
- Flash/Data EEPROM retention: > 40 years - Supports RS-485, RS-232, and LIN 2.0
• Program Memory Read/Write during run time - Auto-Baud Detect
• In-Circuit Debugger (on board) - Auto-Wake-Up on Start bit
• In-Circuit Serial ProgrammingTM (ICSPTM) via Two
Low-Power Features: Pins
• Master Synchronous Serial Port (MSSP) Module
• Standby Current: supporting 3-wire SPI (all 4 modes) and I2C™
- 50 nA @ 2.0V, typical Master and Slave Modes with I2C Address Mask
• Operating Current:
- 11 A @ 32 kHz, 2.0V, typical
- 220 A @ 4 MHz, 2.0V, typical
• Watchdog Timer Current:
- 1 A @ 2.0V, typical
 2006-2012 Microchip Technology Inc. DS41291G-page 1

PIC16F882/883/884/886/887
Pin Diagrams – PIC16F884/887, 40-Pin PDIP
40-Pin PDIP
RE3/MCLR/VPP 1 40 RB7/ICSPDAT
RA0/AN0/ULPWU/C12IN0- 2 39 RB6/ICSPCLK
RA1/AN1/C12IN1- 3 38 RB5/AN13/T1G
RA2/AN2/VREF-/CVREF/C2IN+ 4 37 RB4/AN11
RA3/AN3/VREF+/C1IN+ 5 36 RB3/AN9/PGM/C12IN2-
RA4/T0CKI/C1OUT 6 35 RB2/AN8
RA5/AN4/SS/C2OUT 7 34 RB1/AN10/C12IN3-
RE0/AN5 8 33 RB0/AN12/INT
PIC16F884/887
RE1/AN6 9 32 VDD
RE2/AN7 10 31 VSS
VDD 11 30 RD7/P1D
VSS 12 29 RD6/P1C
RA7/OSC1/CLKIN 13 28 RD5/P1B
RA6/OSC2/CLKOUT 14 27 RD4
RC0/T1OSO/T1CKI 15 26 RC7/RX/DT
RC1/T1OSI/CCP2 16 25 RC6/TX/CK
RC2/P1A/CCP1 17 24 RC5/SDO
RC3/SCK/SCL 18 23 RC4/SDI/SDA
RD0 19 22 RD3
RD1 20 21 RD2

PIC16F882/883/884/886/887
FIGURE 1-2: PIC16F884/PIC16F887 BLOCK DIAGRAM
Configuration PORTA
13 8 RA0
Data Bus
Program Counter RA1
Flash RA2
4K(1)/8K X 14 RA3
RA4
Program RAM RA5
Memory 8-Level Stack 256(1)/368 Bytes RA6
(13-Bit) File RA7
Registers
Program PORTB
14
Bus RAM Addr RB0
9
RB1
Addr MUX RB2
Instruction Reg
RB3
Direct Addr 7 Indirect RB4
8 Addr RB5
RB6
FSR Reg
RB7
STATUS Reg PORTC

8 RC0
RC1
RC2
3 RC3
MUX
Power-up RC4
Timer RC5
Instruction RC6
Oscillator
Decode and Start-up Timer RC7
ALU
Control
Power-on PORTD
OSC1/CLKIN Reset 8 RD0
Timing Watchdog RD1
Generation W Reg RD2
Timer
RD3
OSC2/CLKOUT Brown-out CCP2
RD4
Reset
RD5
Internal RD6
Oscillator RD7
Block CCP2
PORTE
MCLR VDD VSS
RE0
In-Circuit RE1
Debugger RE2
(ICD)
RE3
T1OSI Timer1
32 kHz
CCP1/P1A
SCK/SCL
T1OSO Oscillator
SDI/SDA
RX/DT
TX/CK
SDO
P1C
P1D
P1B
SS
T0CKI T1G T1CKI
Master Synchronous
Timer0 Timer1 Timer2 EUSART ECCP
Serial Port (MSSP)
VREF+
VREF+ Analog-To-Digital Converter 2 Analog Comparators 8
VREF- EEDATA
VREF- (ADC) and Reference
CVREF
256 Bytes
Data
EEPROM
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
C1IN+
C2IN+
C1OUT
C2OUT
C12IN0-
C12IN1-
C12IN2-
C12IN3-
EEADDR
Note 1: PIC16F884 only.

PIC16F882/883/884/886/887
FIGURE 2-6: PIC16F886/PIC16F887 SPECIAL FUNCTION REGISTERS
File File File File
Address Address Address Address
Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h WDTCON 105h SRCON 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h CM1CON0 107h BAUDCTL 187h
PORTD(2) 08h TRISD(2) 88h CM2CON0 108h ANSEL 188h
PORTE 09h TRISE 89h CM2CON1 109h ANSELH 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh
TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved 18Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh
T1CON 10h OSCTUNE 90h 110h 190h
TMR2 11h SSPCON2 91h 111h 191h
T2CON 12h PR2 92h 112h 192h
SSPBUF 13h SSPADD 93h 113h 193h
SSPCON 14h SSPSTAT 94h 114h 194h
CCPR1L 15h WPUB 95h 115h 195h
CCPR1H 16h IOCB 96h General 116h General 196h
CCP1CON 17h VRCON 97h Purpose 117h Purpose 197h
Registers Registers
RCSTA 18h TXSTA 98h 118h 198h
TXREG 19h SPBRG 99h 16 Bytes 119h 16 Bytes 199h
RCREG 1Ah SPBRGH 9Ah 11Ah 19Ah
CCPR2L 1Bh PWM1CON 9Bh 11Bh 19Bh
CCPR2H 1Ch ECCPAS 9Ch 11Ch 19Ch
CCP2CON 1Dh PSTRCON 9Dh 11Dh 19Dh
ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh
ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh
20h A0h 120h 1A0h
General
General General
3Fh Purpose
General Purpose Purpose
Registers
Purpose 40h Registers Registers
Registers 80 Bytes
80 Bytes 80 Bytes
96 Bytes 6Fh EFh 16Fh 1EFh
70h accesses F0h accesses 170h accesses 1F0h
7Fh 70h-7Fh FFh 70h-7Fh 17Fh 70h-7Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2: PIC16F887 only.

PIC16F882/883/884/886/887
2.2.2.1 STATUS Register For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
The STATUS register, shown in Register 2-1, contains:
as ‘000u u1uu’ (where u = unchanged).
• the arithmetic status of the ALU
It is recommended, therefore, that only BCF, BSF,
• the Reset status SWAPF and MOVWF instructions are used to alter the
• the bank select bits for data memory (GPR and STATUS register, because these instructions do not
SFR) affect any Status bits. For other instructions not affect-
The STATUS register can be the destination for any ing any Status bits, see Section 15.0 “Instruction Set
instruction, like any other register. If the STATUS Summary”
register is the destination for an instruction that affects Note 1: The C and DC bits operate as a Borrow
the Z, DC or C bits, then the write to these three bits is and Digit Borrow out bit, respectively, in
disabled. These bits are set or cleared according to the subtraction.
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER DEFINITIONS: STATUS

REGISTER 2-1: STATUS: STATUS REGISTER
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC(1) C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the
source register.

PIC16F882/883/884/886/887
2.2.2.2 OPTION Register
The OPTION register, shown in Register 2-2, is a
readable and writable register, which contains various
control bits to configure:
• Timer0/WDT prescaler
• External INT interrupt
• Timer0
• Weak pull-ups on PORTB
Note: To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT
by setting PSA bit of the OPTION register
to ‘1’. See Section 6.3 “Timer1 Pres-
caler”.
REGISTER DEFINITIONS: OPTION REGISTER

REGISTER 2-2: OPTION_REG: OPTION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual PORT latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate WDT Rate
000 1:2 1:1

001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128
DS41291G-page 32  2006-2012 Microchip Technology Inc.

PIC16F882/883/884/886/887
2.2.2.3 INTCON Register
The INTCON register, shown in Register 2-3, is a
readable and writable register, which contains the various
enable and flag bits for TMR0 register overflow, PORTB
change and external INT pin interrupts.
Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
REGISTER DEFINITIONS: INTERRUPT CONTROL

REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE(1) T0IF(2) INTF RBIF
bit 7 bit 0
Legend:
bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3 RBIE: PORTB Change Interrupt Enable bit(1)
1 = Enables the PORTB change interrupt
0 = Disables the PORTB change interrupt
bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2)
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred (must be cleared in software)
0 = The INT external interrupt did not occur
bit 0 RBIF: PORTB Change Interrupt Flag bit
1 = When at least one of the PORTB general purpose I/O pins changed state (must be cleared in software)
0 = None of the PORTB general purpose I/O pins have changed state
Note 1: IOCB register must also be enabled.

2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing
T0IF bit.

PIC16F882/883/884/886/887
2.2.2.4 PIE1 Register
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-4.
Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.
REGISTER DEFINITIONS: PIE1

REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
Legend:
bit 7 Unimplemented: Read as ‘0’

bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3 SSPIE: Master Synchronous Serial Port (MSSP) Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt

PIC16F882/883/884/886/887
2.2.2.5 PIE2 Register
The PIE2 register contains the interrupt enable bits, as
Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.
REGISTER DEFINITIONS: PIE2

REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE
bit 7 bit 0
Legend:
bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables oscillator fail interrupt
0 = Disables oscillator fail interrupt
bit 6 C2IE: Comparator C2 Interrupt Enable bit
1 = Enables Comparator C2 interrupt
0 = Disables Comparator C2 interrupt
bit 5 C1IE: Comparator C1 Interrupt Enable bit
1 = Enables Comparator C1 interrupt
0 = Disables Comparator C1 interrupt
bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enables EEPROM write operation interrupt
0 = Disables EEPROM write operation interrupt
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enables Bus Collision interrupt
0 = Disables Bus Collision interrupt
bit 2 ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable bit
1 = Enables Ultra Low-Power Wake-up interrupt
0 = Disables Ultra Low-Power Wake-up interrupt
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables CCP2 interrupt
0 = Disables CCP2 interrupt

PIC16F882/883/884/886/887
2.2.2.6 PIR1 Register
The PIR1 register contains the interrupt flag bits, as
Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER DEFINITIONS: PIR1

REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:

bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = A/D conversion complete (must be cleared in software)
0 = A/D conversion has not completed or has not been started
bit 5 RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer is full (cleared by reading RCREG)
0 = The EUSART receive buffer is not full
bit 4 TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer is empty (cleared by writing to TXREG)
0 = The EUSART transmit buffer is full
bit 3 SSPIF: Master Synchronous Serial Port (MSSP) Interrupt Flag bit
1 = The MSSP interrupt condition has occurred, and must be cleared in software before returning from the Interrupt Service Rou-
tine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place
I2 C Slave/Master
A transmission/reception has taken place
I2 C Master
The initiated Start condition was completed by the MSSP module
The initiated Stop condition was completed by the MSSP module
The initiated restart condition was completed by the MSSP module
The initiated Acknowledge condition was completed by the MSSP module
A Start condition occurred while the MSSP module was idle (Multi-master system)
A Stop condition occurred while the MSSP module was idle (Multi-master system)
0 = No MSSP interrupt condition has occurred
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = A Timer2 to PR2 match occurred (must be cleared in software)
0 = No Timer2 to PR2 match occurred
bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = The TMR1 register overflowed (must be cleared in software)
0 = The TMR1 register did not overflow

PIC16F882/883/884/886/887
2.2.2.7 PIR2 Register
The PIR2 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt
shown in Register 2-7. condition occurs, regardless of the state of
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER DEFINITIONS: PIR2

REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF
bit 7 bit 0
Legend:
bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
bit 6 C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator output (C2OUT bit) has changed (must be cleared in software)
0 = Comparator output (C2OUT bit) has not changed
bit 5 C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator output (C1OUT bit) has changed (must be cleared in software)
0 = Comparator output (C1OUT bit) has not changed
bit 4 EEIF: EE Write Operation Interrupt Flag bit
1 = Write operation completed (must be cleared in software)
0 = Write operation has not completed or has not started
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the MSSP when configured for I2C Master mode
0 = No bus collision has occurred
bit 2 ULPWUIF: Ultra Low-Power Wake-up Interrupt Flag bit
1 = Wake-up condition has occurred (must be cleared in software)
0 = No Wake-up condition has occurred
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode

PIC16F882/883/884/886/887
2.2.2.8 PCON Register
The Power Control (PCON) register (see Register 2-8)
contains flag bits to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Watchdog Timer Reset (WDT)
• External MCLR Reset
The PCON register also controls the Ultra Low-Power
Wake-up and software enable of the BOR.
REGISTER DEFINITIONS: PCON

REGISTER 2-8: PCON: POWER CONTROL REGISTER
U-0 U-0 R/W-0 R/W-1 U-0 U-0 R/W-0 R/W-x
— — ULPWUE SBOREN(1) — — POR BOR
bit 7 bit 0
Legend:
bit 7-6 Unimplemented: Read as ‘0’

bit 5 ULPWUE: Ultra Low-Power Wake-up Enable bit
1 = Ultra Low-Power Wake-up enabled
0 = Ultra Low-Power Wake-up disabled
bit 4 SBOREN: Software BOR Enable bit(1)
1 = BOR enabled
0 = BOR disabled
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: BOREN<1:0> = 01 in the Configuration Word Register 1 for this bit to control the BOR.

PIC16F882/883/884/886/887
2.3 PCL and PCLATH 2.3.2 STACK
The Program Counter (PC) is 13 bits wide. The low byte The PIC16F882/883/884/886/887 devices have an
comes from the PCL register, which is a readable and 8-level x 13-bit wide hardware stack (see Figures 2-2
writable register. The high byte (PC<12:8>) is not directly and 2-3). The stack space is not part of either program
readable or writable and comes from PCLATH. On any or data space and the Stack Pointer is not readable or
Reset, the PC is cleared. Figure 2-7 shows the two writable. The PC is PUSHed onto the stack when a
situations for the loading of the PC. The upper example CALL instruction is executed or an interrupt causes a
in Figure 2-7 shows how the PC is loaded on a write to branch. The stack is POPed in the event of a RETURN,
PCL (PCLATH<4:0>  PCH). The lower example in RETLW or a RETFIE instruction execution. PCLATH is
Figure 2-7 shows how the PC is loaded during a CALL or not affected by a PUSH or POP operation.
GOTO instruction (PCLATH<4:3>  PCH). The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
FIGURE 2-7: LOADING OF PC IN push overwrites the value that was stored from the first
DIFFERENT SITUATIONS push. The tenth push overwrites the second push (and
so on).
PCH PCL
Instruction with
12 8 7 0 PCL as
Note 1: There are no Status bits to indicate stack
PC Destination overflow or stack underflow conditions.
PCLATH<4:0> 8 2: There are no instructions/mnemonics

5 ALU Result called PUSH or POP. These are actions
that occur from the execution of the
PCLATH CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
PCH PCL interrupt address.
12 11 10 8 7 0
PC GOTO, CALL
2.4 Indirect Addressing, INDF and
2
PCLATH<4:3> 11
OPCODE<10:0>
FSR Registers
The INDF register is not a physical register. Addressing
PCLATH the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
2.3.1 MODIFYING PCL register. Any instruction using the INDF register actually
Executing any instruction with the PCL register as the accesses data pointed to by the File Select Register
destination simultaneously causes the Program (FSR). Reading INDF itself indirectly will produce 00h.
Counter PC<12:8> bits (PCH) to be replaced by the Writing to the INDF register indirectly results in a no
contents of the PCLATH register. This allows the entire operation (although Status bits may be affected). An
contents of the program counter to be changed by effective 9-bit address is obtained by concatenating the
writing the desired upper 5 bits to the PCLATH register. 8-bit FSR and the IRP bit of the STATUS register, as
When the lower 8 bits are written to the PCL register, all shown in Figure 2-8.
13 bits of the program counter will change to the values A simple program to clear RAM location 20h-2Fh using
contained in the PCLATH register and those being indirect addressing is shown in Example 2-1.
written to the PCL register.
A computed GOTO is accomplished by adding an offset EXAMPLE 2-1: INDIRECT ADDRESSING
to the program counter (ADDWF PCL). Care should be MOVLW 0x20 ;initialize pointer
exercised when jumping into a look-up table or MOVWF FSR ;to RAM
program branch table (computed GOTO) by modifying NEXT CLRF INDF ;clear INDF register
the PCL register. Assuming that PCLATH is set to the INCF FSR ;inc pointer
table start address, if the table length is greater than BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next
255 instructions or if the lower 8 bits of the memory
CONTINUE ;yes continue
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.
For more information refer to Application Note AN556,
“Implementing a Table Read” (DS00556).

PIC16F882/883/884/886/887
FIGURE 2-8: DIRECT/INDIRECT ADDRESSING PIC16F882/883/884/886/887
Direct Addressing Indirect Addressing
RP1 RP0 6 From Opcode 0 IRP 7 File Select Register 0
Bank Select Location Select Bank Select Location Select

00 01 10 11
00h 180h
Data
Memory
7Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
Note: For memory map detail, see Figures 2-2 and 2-3.

PIC16F882/883/884/886/887
3.0 I/O PORTS The TRISA register (Register 3-2) controls the PORTA
pin output drivers, even when they are being used as
There are as many as thirty-five general purpose I/O analog inputs. The user should ensure the bits in the
pins available. Depending on which peripherals are TRISA register are maintained set when using them as
enabled, some or all of the pins may not be available as analog inputs. I/O pins configured as analog input
general purpose I/O. In general, when a peripheral is always read ‘0’.
enabled, the associated pin may not be used as a
Note: The ANSEL register must be initialized to
general purpose I/O pin.
configure an analog channel as a digital
input. Pins configured as analog inputs
3.1 PORTA and the TRISA Registers will read ‘0’.
PORTA is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA EXAMPLE 3-1: INITIALIZING PORTA
(Register 3-2). Setting a TRISA bit (= 1) will make the BANKSEL PORTA ;
corresponding PORTA pin an input (i.e., disable the CLRF PORTA ;Init PORTA
output driver). Clearing a TRISA bit (= 0) will make the BANKSEL ANSEL ;
corresponding PORTA pin an output (i.e., enables CLRF ANSEL ;digital I/O
BANKSEL TRISA ;
output driver and puts the contents of the output latch
MOVLW 0Ch ;Set RA<3:2> as inputs
on the selected pin). Example 3-1 shows how to MOVWF TRISA ;and set RA<5:4,1:0>
initialize PORTA. ;as outputs
Reading the PORTA register (Register 3-1) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch.
REGISTER 3-1: PORTA: PORTA REGISTER

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
Legend:
bit 7-0 RA<7:0>: PORTA I/O Pin bit

1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 3-2: TRISA: PORTA TRI-STATE REGISTER

R/W-1(1) R/W-1(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
bit 7 bit 0
Legend:
bit 7-0 TRISA<7:0>: PORTA Tri-State Control bit

1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Note 1: TRISA<7:6> always reads ‘1’ in XT, HS and LP Oscillator modes.

PIC16F882/883/884/886/887
3.2 Additional Pin Functions
RA0 also has an Ultra Low-Power Wake-up option. The
next three sections describe these functions.
3.2.1 ANSEL REGISTER

The ANSEL register (Register 3-3) is used to configure
the Input mode of an I/O pin to analog. Setting the
appropriate ANSEL bit high will cause all digital reads
on the pin to be read as ‘0’ and allow analog functions
on the pin to operate correctly.
The state of the ANSEL bits has no affect on digital out-
put functions. A pin with TRIS clear and ANSEL set will
still operate as a digital output, but the Input mode will
be analog. This can cause unexpected behavior when
executing read-modify-write instructions on the
affected port.
REGISTER 3-3: ANSEL: ANALOG SELECT REGISTER

ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0
bit 7 bit 0
Legend:
bit 7-0 ANS<7:0>: Analog Select bits

Analog select between analog or digital function on pins AN<7:0>, respectively.
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and
interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
2: Not implemented on PIC16F883/886.

PIC16F882/883/884/886/887
3.3 PORTB and TRISB Registers 3.4.1 ANSELH REGISTER
PORTB is an 8-bit wide, bidirectional port. The The ANSELH register (Register 3-4) is used to
corresponding data direction register is TRISB configure the Input mode of an I/O pin to analog.
(Register 3-6). Setting a TRISB bit (= 1) will make the Setting the appropriate ANSELH bit high will cause all
corresponding PORTB pin an input (i.e., put the digital reads on the pin to be read as ‘0’ and allow
corresponding output driver in a High-Impedance mode). analog functions on the pin to operate correctly.
Clearing a TRISB bit (= 0) will make the corresponding The state of the ANSELH bits has no affect on digital
PORTB pin an output (i.e., enable the output driver and output functions. A pin with TRIS clear and ANSELH
put the contents of the output latch on the selected pin). set will still operate as a digital output, but the Input
Example 3-3 shows how to initialize PORTB. mode will be analog. This can cause unexpected
Reading the PORTB register (Register 3-5) reads the behavior when executing read-modify-write
status of the pins, whereas writing to it will write to the instructions on the affected port.
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the 3.4.2 WEAK PULL-UPS
port pins are read, this value is modified and then written Each of the PORTB pins has an individually configurable
to the PORT data latch. internal weak pull-up. Control bits WPUB<7:0> enable or
The TRISB register (Register 3-6) controls the PORTB disable each pull-up (see Register 3-7). Each weak
pin output drivers, even when they are being used as pull-up is automatically turned off when the port pin is
analog inputs. The user should ensure the bits in the configured as an output. All pull-ups are disabled on a
TRISB register are maintained set when using them as Power-on Reset by the RBPU bit of the OPTION register.
analog inputs. I/O pins configured as analog input always
read ‘0’. Example 3-3 shows how to initialize PORTB. 3.4.3 INTERRUPT-ON-CHANGE
All of the PORTB pins are individually configurable as an
EXAMPLE 3-3: INITIALIZING PORTB interrupt-on-change pin. Control bits IOCB<7:0> enable
or disable the interrupt function for each pin. Refer to
BANKSEL PORTB ; Register 3-8. The interrupt-on-change feature is
CLRF PORTB ;Init PORTB
disabled on a Power-on Reset.
BANKSEL TRISB ;
MOVLW B‘11110000’ ;Set RB<7:4> as inputs For enabled interrupt-on-change pins, the present value
;and RB<3:0> as outputs is compared with the old value latched on the last read
MOVWF TRISB ; of PORTB to determine which bits have changed or
mismatched the old value. The ‘mismatch’ outputs of
the last read are OR’d together to set the PORTB
Change Interrupt flag bit (RBIF) in the INTCON register.
Note: The ANSELH register must be initialized
to configure an analog channel as a digital This interrupt can wake the device from Sleep. The user,
input. Pins configured as analog inputs in the Interrupt Service Routine, clears the interrupt by:
will read ‘0’. a) Any read or write of PORTB. This will end the
mismatch condition.
3.4 Additional PORTB Pin Functions b) Clear the flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
PORTB pins RB<7:0> on the device family device have
Reading or writing PORTB will end the mismatch
an interrupt-on-change option and a weak pull-up
condition and allow flag bit RBIF to be cleared. The latch
option. The following three sections describe these
holding the last read value is not affected by a MCLR nor
PORTB pin functions.
Brown-out Reset. After these Resets, the RBIF flag will
Every PORTB pin on this device family has an continue to be set if a mismatch is present.
interrupt-on-change option and a weak pull-up option.
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set. Furthermore,
since a read or write on a port affects all bits
of that port, care must be taken when using
multiple pins in Interrupt-on-Change mode.
Changes on one pin may not be seen while
servicing changes on another pin.

PIC16F882/883/884/886/887
REGISTER 3-4: ANSELH: ANALOG SELECT HIGH REGISTER

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — ANS13 ANS12 ANS11 ANS10 ANS9 ANS8
bit 7 bit 0
Legend:

bit 5-0 ANS<13:8>: Analog Select bits
Analog select between analog or digital function on pins AN<13:8>, respectively.
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and
interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
REGISTER 3-5: PORTB: PORTB REGISTER

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
bit 7 bit 0
Legend:
bit 7-0 RB<7:0>: PORTB I/O Pin bit

REGISTER 3-6: TRISB: PORTB TRI-STATE REGISTER

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
bit 7 bit 0
Legend:
bit 7-0 TRISB<7:0>: PORTB Tri-State Control bit

1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output

PIC16F882/883/884/886/887
REGISTER 3-7: WPUB: WEAK PULL-UP PORTB REGISTER

WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
bit 7 bit 0
Legend:
bit 7-0 WPUB<7:0>: Weak Pull-up Register bit

1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global RBPU bit of the OPTION register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
REGISTER 3-8: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER

IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0
bit 7 bit 0
Legend:
bit 7-0 IOCB<7:0>: Interrupt-on-Change PORTB Control bit

1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled

PIC16F882/883/884/886/887
3.5 PORTC and TRISC Registers The TRISC register (Register 3-10) controls the PORTC
PORTC is a 8-bit wide, bidirectional port. The analog inputs. The user should ensure the bits in the
corresponding data direction register is TRISC TRISC register are maintained set when using them as
(Register 3-10). Setting a TRISC bit (= 1) will make the analog inputs. I/O pins configured as analog input always
corresponding PORTC pin an input (i.e., put the read ‘0’.
corresponding output driver in a High-Impedance mode).
Clearing a TRISC bit (= 0) will make the corresponding
EXAMPLE 3-4: INITIALIZING PORTC
PORTC pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin). BANKSEL PORTC ;
Example 3-4 shows how to initialize PORTC. CLRF PORTC ;Init PORTC
BANKSEL TRISC ;
Reading the PORTC register (Register 3-9) reads the MOVLW B‘00001100’ ;Set RC<3:2> as inputs
status of the pins, whereas writing to it will write to the MOVWF TRISC ;and set RC<7:4,1:0>
PORT latch. All write operations are read-modify-write ;as outputs
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch.
REGISTER 3-9: PORTC: PORTC REGISTER

RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0
Legend:
bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bit

REGISTER 3-10: TRISC: PORTC TRI-STATE REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1(1) R/W-1(1)
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0
Legend:
bit 7-0 TRISC<7:0>: PORTC Tri-State Control bit

1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
Note 1: TRISC<1:0> always reads ‘1’ in LP Oscillator mode.

PIC16F882/883/884/886/887
3.6 PORTD and TRISD Registers The TRISD register (Register 3-12) controls the PORTD
PORTD(1) is a 8-bit wide, bidirectional port. The analog inputs. The user should ensure the bits in the
corresponding data direction register is TRISD TRISD register are maintained set when using them as
(Register 3-12). Setting a TRISD bit (= 1) will make the analog inputs. I/O pins configured as analog input always
corresponding PORTD pin an input (i.e., put the read ‘0’.
corresponding output driver in a High-Impedance mode).
Clearing a TRISD bit (= 0) will make the corresponding
EXAMPLE 3-5: INITIALIZING PORTD
PORTD pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 3-5 shows how to initialize PORTD.
BANKSEL PORTD ;
Reading the PORTD register (Register 3-11) reads the CLRF PORTD ;Init PORTD
status of the pins, whereas writing to it will write to the BANKSEL TRISD ;
PORT latch. All write operations are read-modify-write MOVLW B‘00001100’ ;Set RD<3:2> as inputs
operations. Therefore, a write to a port implies that the MOVWF TRISD ;and set RD<7:4,1:0>
port pins are read, this value is modified and then written ;as outputs
to the PORT data latch.
Note 1: PORTD is available on PIC16F884/887
only.
REGISTER 3-11: PORTD: PORTD REGISTER

RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
bit 7 bit 0
Legend:
bit 7-0 RD<7:0>: PORTD General Purpose I/O Pin bit

REGISTER 3-12: TRISD: PORTD TRI-STATE REGISTER

TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
bit 7 bit 0
Legend:
bit 7-0 TRISD<7:0>: PORTD Tri-State Control bit

1 = PORTD pin configured as an input (tri-stated)
0 = PORTD pin configured as an output

PIC16F882/883/884/886/887
3.7 PORTE and TRISE Registers The TRISE register (Register 3-14) controls the PORTE
PORTE(1) is a 4-bit wide, bidirectional port. The analog inputs. The user should ensure the bits in the
corresponding data direction register is TRISE. Setting a TRISE register are maintained set when using them as
TRISE bit (= 1) will make the corresponding PORTE pin analog inputs. I/O pins configured as analog input always
an input (i.e., put the corresponding output driver in a read ‘0’.
High-Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e., Note: The ANSEL register must be initialized to
enable the output driver and put the contents of the configure an analog channel as a digital
output latch on the selected pin). The exception is RE3, input. Pins configured as analog inputs
which is input only and its TRIS bit will always read as will read ‘0’.
‘1’. Example 3-6 shows how to initialize PORTE.
Reading the PORTE register (Register 3-13) reads the EXAMPLE 3-6: INITIALIZING PORTE
status of the pins, whereas writing to it will write to the BANKSEL PORTE ;
PORT latch. All write operations are read-modify-write CLRF PORTE ;Init PORTE
operations. Therefore, a write to a port implies that the BANKSEL ANSEL ;
port pins are read, this value is modified and then CLRF ANSEL ;digital I/O
written to the PORT data latch. RE3 reads ‘0’ when BCF STATUS,RP1 ;Bank 1
MCLRE = 1. BANKSEL TRISE ;
MOVLW B‘00001100’ ;Set RE<3:2> as inputs
Note 1: RE<2:0> pins are available on MOVWF TRISE ;and set RE<1:0>
PIC16F884/887 only. ;as outputs
REGISTER 3-13: PORTE: PORTE REGISTER

U-0 U-0 U-0 U-0 R-x R/W-x R/W-x R/W-x
— — — — RE3 RE2 RE1 RE0
bit 7 bit 0
Legend:

bit 3-0 RD<3:0>: PORTE General Purpose I/O Pin bit
REGISTER 3-14: TRISE: PORTE TRI-STATE REGISTER

U-0 U-0 U-0 U-0 R-1(1) R/W-1 R/W-1 R/W-1
— — — — TRISE3 TRISE2 TRISE1 TRISE0
bit 7 bit 0
Legend:

bit 3-0 TRISE<3:0>: PORTE Tri-State Control bit
1 = PORTE pin configured as an input (tri-stated)
0 = PORTE pin configured as an output
Note 1: TRISE<3> always reads ‘1’.

PIC16F882/883/884/886/887
4.0 OSCILLATOR MODULE (WITH The oscillator module can be configured in one of eight
clock modes.
FAIL-SAFE CLOCK MONITOR)
1. EC – External clock with I/O on OSC2/CLKOUT.
4.1 Overview 2. LP – 32 kHz Low-Power Crystal mode.
3. XT – Medium Gain Crystal or Ceramic Resonator
The oscillator module has a wide variety of clock Oscillator mode.
sources and selection features that allow it to be used
4. HS – High Gain Crystal or Ceramic Resonator
in a wide range of applications while maximizing perfor-
mode.
mance and minimizing power consumption. Figure 4-1
illustrates a block diagram of the oscillator module. 5. RC – External Resistor-Capacitor (RC) with
FOSC/4 output on OSC2/CLKOUT.
Clock sources can be configured from external
6. RCIO – External Resistor-Capacitor (RC) with I/
oscillators, quartz crystal resonators, ceramic resonators
O on OSC2/CLKOUT.
and Resistor-Capacitor (RC) circuits. In addition, the
system clock source can be configured from one of two 7. INTOSC – Internal oscillator with FOSC/4 output
internal oscillators, with a choice of speeds selectable via on OSC2 and I/O on OSC1/CLKIN.
software. Additional clock features include: 8. INTOSCIO – Internal oscillator with I/O on
OSC1/CLKIN and OSC2/CLKOUT.
• Selectable system clock source between external
or internal via software. Clock Source modes are configured by the FOSC<2:0>
• Two-Speed Start-up mode, which minimizes bits in the Configuration Word Register 1 (CONFIG1).
latency between external oscillator start-up and The internal clock can be generated from two internal
code execution. oscillators. The HFINTOSC is a calibrated high-
frequency oscillator. The LFINTOSC is an uncalibrated
• Fail-Safe Clock Monitor (FSCM) designed to
low-frequency oscillator.
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.
FIGURE 4-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
FOSC<2:0>
(Configuration Word Register 1)
External Oscillator SCS<0>
(OSCCON Register)
OSC2
Sleep
LP, XT, HS, RC, RCIO, EC
OSC1
MUX
IRCF<2:0>
(OSCCON Register) System Clock
(CPU and Peripherals)
8 MHz
111 INTOSC
Internal Oscillator 4 MHz
110
2 MHz
101
Postscaler
1 MHz
MUX
HFINTOSC 100
500 kHz
8 MHz 011
250 kHz
010
125 kHz
001
LFINTOSC 31 kHz
000
31 kHz
Power-up Timer (PWRT)

Watchdog Timer (WDT)
Fail-Safe Clock Monitor (FSCM)

PIC16F882/883/884/886/887
4.2 Oscillator Control
The Oscillator Control (OSCCON) register (Figure 4-1)
controls the system clock and frequency selection
options. The OSCCON register contains the following
bits:
• Frequency selection bits (IRCF)
• Frequency Status bits (HTS, LTS)
• System clock control bits (OSTS, SCS)
REGISTER DEFINITIONS: OSCILLATOR CONTROL

REGISTER 4-1: OSCCON: OSCILLATOR CONTROL REGISTER
U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0
(1)
— IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS
bit 7 bit 0
Legend:

bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits
111 = 8 MHz
110 = 4 MHz (default)
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (LFINTOSC)
bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Device is running from the clock defined by FOSC<2:0> of the CONFIG1 register
0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC)
bit 2 HTS: HFINTOSC Status bit (High Frequency – 8 MHz to 125 kHz)
1 = HFINTOSC is stable
0 = HFINTOSC is not stable
bit 1 LTS: LFINTOSC Stable bit (Low Frequency – 31 kHz)
1 = LFINTOSC is stable
0 = LFINTOSC is not stable
bit 0 SCS: System Clock Select bit
1 = Internal oscillator is used for system clock
0 = Clock source defined by FOSC<2:0> of the CONFIG1 register
Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.

PIC16F882/883/884/886/887
5.0 TIMER0 MODULE 5.1 Timer0 Operation
The Timer0 module is an 8-bit timer/counter with the When used as a timer, the Timer0 module can be used
following features: as either an 8-bit timer or an 8-bit counter.
• 8-bit timer/counter register (TMR0)
5.1.1 8-BIT TIMER MODE
• 8-bit prescaler (shared with Watchdog Timer)
When used as a timer, the Timer0 module will
• Programmable internal or external clock source
increment every instruction cycle (without prescaler).
• Programmable external clock edge selection Timer mode is selected by clearing the T0CS bit of the
• Interrupt on overflow OPTION register to ‘0’.
Figure 5-1 is a block diagram of the Timer0 module. When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note: The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
5.1.2 8-BIT COUNTER MODE

When used as a counter, the Timer0 module will
increment on every rising or falling edge of the T0CKI
pin. The incrementing edge is determined by the T0SE
bit of the OPTION register. Counter mode is selected by
setting the T0CS bit of the OPTION register to ‘1’.
FIGURE 5-1: TIMER0/WDT PRESCALER BLOCK DIAGRAM
FOSC/4
Data Bus
0
8
1
Sync
1 2 Tcy TMR0
T0CKI 0
pin 0
T0SE T0CS Set Flag bit T0IF
8-bit
on Overflow
Prescaler PSA
1
8
WDTE PSA
SWDTEN
PS<2:0> 1
WDT
16-bit Time-out
Prescaler 0
16
31 kHz Watchdog
INTOSC Timer PSA
WDTPS<3:0>
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register.
3: WDTE bit is in the Configuration Word Register1.

PIC16F882/883/884/886/887
REGISTER DEFINITIONS: OPTION REGISTER
REGISTER 5-1: OPTION_REG: OPTION REGISTER
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual PORT latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
BIT VALUE TMR0 RATE WDT RATE
000 1:2 1:1

001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128
Note 1: A dedicated 16-bit WDT postscaler is available. See Section 14.5 “Watchdog Timer (WDT)” for more
information.
TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
TMR0 Timer0 Module Register 77
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 33
OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 79
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 41
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the
Timer0 module.

PIC16F882/883/884/886/887
6.0 TIMER1 MODULE WITH GATE 6.1 Timer1 Operation
CONTROL The Timer1 module is a 16-bit incrementing counter
The Timer1 module is a 16-bit timer/counter with the which is accessed through the TMR1H:TMR1L register
following features: pair. Writes to TMR1H or TMR1L directly update the
counter.
• 16-bit timer/counter register pair (TMR1H:TMR1L)
When used with an internal clock source, the module is
• Programmable internal or external clock source
a timer. When used with an external clock source, the
• 3-bit prescaler module can be used as either a timer or counter.
• Optional LP oscillator
• Synchronous or asynchronous operation 6.2 Clock Source Selection
• Timer1 gate (count enable) via comparator or
The TMR1CS bit of the T1CON register is used to select
T1G pin
the clock source. When TMR1CS = 0, the clock source
• Interrupt on overflow is FOSC/4. When TMR1CS = 1, the clock source is
• Wake-up on overflow (external clock, supplied externally.
Asynchronous mode only)
• Time base for the Capture/Compare function
• Special Event Trigger (with ECCP) Clock Source TMR1CS
• Comparator output synchronization to Timer1 FOSC/4 0
clock
T1CKI pin 1
Figure 6-1 is a block diagram of the Timer1 module.
FIGURE 6-1: TIMER1 BLOCK DIAGRAM
TMR1GE
T1GINV
TMR1ON
Set flag bit
TMR1IF on To C2 Comparator Module
Overflow TMR1(2) Timer1 Clock
Synchronized
EN 0 clock input
TMR1H TMR1L
1
Oscillator
(1) T1SYNC
T1OSO/T1CKI 1
Prescaler Synchronize(3)
1, 2, 4, 8 det
0
T1OSI 2
T1CKPS<1:0>
TMR1CS
T1G 1
INTOSC
Without CLKOUT SYNCC2OUT(4) 0
T1OSCEN FOSC/4
Internal T1GSS
Clock
Note 1: ST Buffer is low power type when using LP osc, or high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
4: SYNCC2OUT is synchronized when the C2SYNC bit of the CM2CON1 register is set.

PIC16F882/883/884/886/887
6.12 Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 6-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER DEFINITIONS: TIMER1 CONTROL

REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER
(1) (2)
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
Legend:
bit 7 T1GINV: Timer1 Gate Invert bit(1)

1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 6 TMR1GE: Timer1 Gate Enable bit(2)
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 Gate function
0 = Timer1 is always counting
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale Value
bit 3 T1OSCEN: LP Oscillator Enable Control bit
1 = LP oscillator is enabled for Timer1 clock
0 = LP oscillator is off
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from T1CKI pin (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.
2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1
register, as a Timer1 gate source.

PIC16F882/883/884/886/887
7.0 TIMER2 MODULE The TMR2 and PR2 registers are both fully readable
and writable. On any Reset, the TMR2 register is set to
The Timer2 module is an 8-bit timer with the following 00h and the PR2 register is set to FFh.
features:
Timer2 is turned on by setting the TMR2ON bit in the
• 8-bit timer register (TMR2) T2CON register to a ‘1’. Timer2 is turned off by clearing
• 8-bit period register (PR2) the TMR2ON bit to a ‘0’.
• Interrupt on TMR2 match with PR2 The Timer2 prescaler is controlled by the T2CKPS bits
• Software programmable prescaler (1:1, 1:4, 1:16) in the T2CON register. The Timer2 postscaler is
• Software programmable postscaler (1:1 to 1:16) controlled by the TOUTPS bits in the T2CON register.
The prescaler and postscaler counters are cleared
See Figure 7-1 for a block diagram of Timer2.
when:
7.1 Timer2 Operation • A write to TMR2 occurs.

• A write to T2CON occurs.
The clock input to the Timer2 module is the system • Any device Reset occurs (Power-on Reset, MCLR
instruction clock (FOSC/4). The clock is fed into the Reset, Watchdog Timer Reset, or Brown-out
Timer2 prescaler, which has prescale options of 1:1, Reset).
1:4 or 1:16. The output of the prescaler is then used to
increment the TMR2 register. Note: TMR2 is not cleared when T2CON is
written.
The values of TMR2 and PR2 are constantly compared
to determine when they match. TMR2 will increment
from 00h until it matches the value in PR2. When a
match occurs, two things happen:
• TMR2 is reset to 00h on the next increment cycle
• The Timer2 postscaler is incremented
The match output of the Timer2/PR2 comparator is
then fed into the Timer2 postscaler. The postscaler has
postscale options of 1:1 to 1:16 inclusive. The output of
the Timer2 postscaler is used to set the TMR2IF
interrupt flag bit in the PIR1 register.
FIGURE 7-1: TIMER2 BLOCK DIAGRAM
Sets Flag
TMR2
bit TMR2IF
Output
Prescaler Reset
FOSC/4 TMR2
1:1, 1:4, 1:16
2 Postscaler
Comparator
EQ 1:1 to 1:16
T2CKPS<1:0>
PR2 4
TOUTPS<3:0>

PIC16F882/883/884/886/887
REGISTER DEFINITIONS: TIMER2 CONTROL
REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
Legend:

bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits
0000 = 1:1 Postscaler
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
TABLE 7-1: SUMMARY OF ASSOCIATED TIMER2 REGISTERS

Register
on Page
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 34
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 36
PR2 Timer2 Module Period Register 87
TMR2 Holding Register for the 8-bit TMR2 Register 87
T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 88
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for Timer2
module.

PIC16F882/883/884/886/887
8.0 COMPARATOR MODULE 8.1 Comparator Overview
Comparators are used to interface analog circuits to a A single comparator is shown in Figure 8-1 along with
digital circuit by comparing two analog voltages and the relationship between the analog input levels and
providing a digital indication of their relative magnitudes. the digital output. When the analog voltage at VIN+ is
The comparators are very useful mixed signal building less than the analog voltage at VIN-, the output of the
blocks because they provide analog functionality comparator is a digital low level. When the analog
independent of the program execution. The analog voltage at VIN+ is greater than the analog voltage at
comparator module includes the following features: VIN-, the output of the comparator is a digital high level.
• Independent comparator control
FIGURE 8-1: SINGLE COMPARATOR
• Programmable input selection
• Comparator output is available internally/externally
• Programmable output polarity VIN+ +
• Interrupt-on-change Output
VIN- –
• Wake-up from Sleep
• PWM shutdown
• Timer1 gate (count enable)
• Output synchronization to Timer1 clock input VIN-
• SR Latch VIN+
• Programmable and fixed voltage reference
Note: Only Comparator C2 can be linked to
Timer1.
Output
Note: The black areas of the output of the

comparator represents the uncertainty
due to input offsets and response time.

PIC16F882/883/884/886/887
FIGURE 8-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
C1CH<1:0>
2 C1POL To
D Q Data Bus
Q1
C12IN0- 0 EN
RD_CM1CON0
C12IN1- 1
MUX Set C1IF
C12IN2- D Q
2
Q3*RD_CM1CON0
EN
C12IN3- 3 To PWM Logic
CL
Reset
C1ON(1)
C1R
C1VIN- -
C1IN+ 0 C1 C1OUT
MUX C1VIN+
+
FixedRef 1 C1OUT (to SR Latch)
0
MUX C1POL
CVREF 1 C1VREF
C1RSEL
Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (FOSC).
3: Q1 is held high during Sleep mode.
FIGURE 8-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
C2POL To
D Q Data Bus
Q1
EN
RD_CM2CON0
C2CH<1:0> Set C2IF
2 D Q
Q3*RD_CM2CON0
EN
C12IN0- 0 C2ON(1)
CL
C12IN1- 1 Reset
MUX C2VIN-
C12IN2- 2 C2 C2OUT
C2VIN+
C12IN3- 3 C2SYNC
C2POL 0
C2R SYNCC2OUT
MUX
D Q 1 To Timer1 Gate, SR Latch,
C2IN+ 0 PWM Logic, and other
MUX From Timer1
Clock peripherals
FixedRef 1
0
MUX
CVREF 1 C2VREF
C2RSEL
Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (FOSC).
3: Q1 is held high during Sleep mode.

PIC16F882/883/884/886/887
8.5 Operation During Sleep and the PEIE bit of the INTCON register must be set.
The instruction following the Sleep instruction always
The comparator, if enabled before entering Sleep mode, executes following a wake from Sleep. If the GIE bit of
remains active during Sleep. The additional current the INTCON register is also set, the device will then
consumed by the comparator is shown separately in the execute the Interrupt Service Routine.
Section 17.0 “Electrical Specifications”. If the
comparator is not used to wake the device, power
8.6 Effects of a Reset
consumption can be minimized while in Sleep mode by
turning off the comparator. Each comparator is turned off A device Reset forces the CMxCON0 and CM2CON1
by clearing the CxON bit of the CMxCON0 register. registers to their Reset states. This forces both
A change to the comparator output can wake-up the comparators and the voltage references to their Off
device from Sleep. To enable the comparator to wake states.
the device from Sleep, the CxIE bit of the PIE2 register
REGISTER DEFINITIONS: COMPARATOR C1

REGISTER 8-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER 0
R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0
bit 7 bit 0
Legend:
bit 7 C1ON: Comparator C1 Enable bit

1 = Comparator C1 is enabled
0 = Comparator C1 is disabled
bit 6 C1OUT: Comparator C1 Output bit
If C1POL = 1 (inverted polarity):
C1OUT = 0 when C1VIN+ > C1VIN-
C1OUT = 1 when C1VIN+ < C1VIN-
If C1POL = 0 (non-inverted polarity):
bit 5 C1OE: Comparator C1 Output Enable bit
1 = C1OUT is present on the C1OUT pin(1)
0 = C1OUT is internal only
bit 4 C1POL: Comparator C1 Output Polarity Select bit
1 = C1OUT logic is inverted
0 = C1OUT logic is not inverted
bit 2 C1R: Comparator C1 Reference Select bit (non-inverting input)
1 = C1VIN+ connects to C1VREF output
0 = C1VIN+ connects to C1IN+ pin
bit 1-0 C1CH<1:0>: Comparator C1 Channel Select bit
00 = C12IN0- pin of C1 connects to C1VIN-
Note 1: Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding port
TRIS bit = 0.

PIC16F882/883/884/886/887
REGISTER DEFINITIONS: COMPARATOR C2
R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0
bit 7 bit 0
Legend:
bit 7 C2ON: Comparator C2 Enable bit

1 = Comparator C2 is enabled
0 = Comparator C2 is disabled
bit 6 C2OUT: Comparator C2 Output bit
If C2POL = 1 (inverted polarity):
If C2POL = 0 (non-inverted polarity):
bit 5 C2OE: Comparator C2 Output Enable bit
1 = C2OUT is present on C2OUT pin(1)
0 = C2OUT is internal only
bit 4 C2POL: Comparator C2 Output Polarity Select bit
1 = C2OUT logic is inverted
0 = C2OUT logic is not inverted
bit 2 C2R: Comparator C2 Reference Select bits (non-inverting input)
1 = C2VIN+ connects to C2VREF
0 = C2VIN+ connects to C2IN+ pin
bit 1-0 C2CH<1:0>: Comparator C2 Channel Select bits
Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port
TRIS bit = 0.

PIC16F882/883/884/886/887
8.8 Additional Comparator Features 8.8.2 SYNCHRONIZING COMPARATOR
C2 OUTPUT TO TIMER1
There are three additional comparator features:
The Comparator C2 output can be synchronized with
• Timer1 count enable (gate)
Timer1 by setting the C2SYNC bit of the CM2CON1
• Synchronizing output with Timer1 register. When enabled, the C2 output is latched on the
• Simultaneous read of comparator outputs falling edge of the Timer1 clock source. If a prescaler is
used with Timer1, the comparator output is latched after
8.8.1 COMPARATOR C2 GATING TIMER1 the prescaling function. To prevent a race condition, the
This feature can be used to time the duration or interval comparator output is latched on the falling edge of the
of analog events. Clearing the T1GSS bit of the Timer1 clock source and Timer1 increments on the
CM2CON1 register will enable Timer1 to increment rising edge of its clock source. See the Comparator
based on the output of Comparator C2. This requires Block Diagram (Figures 8-2 and 8-3) and the Timer1
that Timer1 is on and gating is enabled. See Block Diagram (Figure 6-1) for more information.
Section 6.0 “Timer1 Module with Gate Control” for
details. 8.8.3 SIMULTANEOUS COMPARATOR
OUTPUT READ
It is recommended to synchronize the comparator with
Timer1 by setting the C2SYNC bit when the comparator The MC1OUT and MC2OUT bits of the CM2CON1
is used as the Timer1 gate source. This ensures Timer1 register are mirror copies of both comparator outputs.
does not miss an increment if the comparator changes The ability to read both outputs simultaneously from a
during an increment. single register eliminates the timing skew of reading
separate registers.
Note 1: Obtaining the status of C1OUT or
C2OUT by reading CM2CON1 does not
affect the comparator interrupt mismatch
registers.

R-0 R-0 R/W-0 R/W-0 U-0 U-0 R/W-1 R/W-0
MC1OUT MC2OUT C1RSEL C2RSEL — — T1GSS C2SYNC
bit 7 bit 0
Legend:
bit 7 MC1OUT: Mirror Copy of C1OUT bit

bit 6 MC2OUT: Mirror Copy of C2OUT bit
bit 5 C1RSEL: Comparator C1 Reference Select bit
1 = CVREF routed to C1VREF input of Comparator C1
0 = Absolute voltage reference (0.6) routed to C1VREF input of Comparator C1 (or 1.2V precision
reference on parts so equipped)
bit 4 C2RSEL: Comparator C2 Reference Select bit
1 = CVREF routed to C2VREF input of Comparator C2
0 = Absolute voltage reference (0.6) routed to C2VREF input of Comparator C2 (or 1.2V precision
reference on parts so equipped)
bit 1 T1GSS: Timer1 Gate Source Select bit
1 = Timer1 gate source is T1G
0 = Timer1 gate source is SYNCC2OUT.
bit 0 C2SYNC: Comparator C2 Output Synchronization bit
1 = Output is synchronous to falling edge of Timer1 clock
0 = Output is asynchronous

PIC16F882/883/884/886/887
REGISTER DEFINITIONS: SR LATCH
REGISTER 8-4: SRCON: SR LATCH CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/S-0 R/S-0 U-0 R/W-0
SR1(2) SR0(2) C1SEN C2REN PULSS PULSR — FVREN
bit 7 bit 0
Legend: S = Bit is set only -

bit 7 SR1: SR Latch Configuration bit(2)

1 = C2OUT pin is the latch Q output
0 = C2OUT pin is the C2 comparator output
bit 6 SR0: SR Latch Configuration bits(2)
1 = C1OUT pin is the latch Q output
0 = C1OUT pin is the C1 Comparator output
bit 5 C1SEN: C1 Set Enable bit
1 = C1 comparator output sets SR latch
0 = C1 comparator output has no effect on SR latch
bit 4 C2REN: C2 Reset Enable bit
1 = C2 comparator output resets SR latch
0 = C2 comparator output has no effect on SR latch
bit 3 PULSS: Pulse the SET Input of the SR Latch bit
1 = Triggers pulse generator to set SR latch. Bit is immediately reset by hardware.
0 = Does not trigger pulse generator
bit 2 PULSR: Pulse the Reset Input of the SR Latch bit
1 = Triggers pulse generator to reset SR latch. Bit is immediately reset by hardware.
0 = Does not trigger pulse generator
bit 0 FVREN: Fixed Voltage Reference Enable bit
1 = 0.6V Reference FROM INTOSC LDO is enabled
0 = 0.6V Reference FROM INTOSC LDO is disabled
Note 1: The CxOUT bit in the CMxCON0 register will always reflect the actual comparator output (not the level on
the pin), regardless of the SR latch operation.
2: To enable an SR Latch output to the pin, the appropriate CxOE and TRIS bits must be properly
configured.

PIC16F882/883/884/886/887
FIGURE 8-8: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
VREF+
VRSS = 1 8R R R R R
VRSS = 0
VDD 8R VRR
Analog
MUX
VREF-
VRSS = 1
15
CVREF
VRSS = 0
To Comparators
and ADC Module 0
VR<3:0>
VROE
4
VREN
CVREF C1RSEL
C2RSEL FVREN
Sleep
HFINTOSC enable
EN
FixedRef 0.6V Fixed Voltage
To Comparators Reference
and ADC Module
FIGURE 8-9: COMPARATOR AND ADC VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+
AVDD 1 AVDD 1
0 0
VRSS VCFG0
CVREF
Comparator ADC
Voltage Voltage
VROE
Reference Reference
VCFG1
VRSS
0
0 AVSS 1
AVSS 1 VCFG1
VREF-

PIC16F882/883/884/886/887
REGISTER DEFINITIONS: VOLTAGE REFERENCE CONTROL
REGISTER 8-5: VRCON: VOLTAGE REFERENCE CONTROL REGISTER
VREN VROE VRR VRSS VR3 VR2 VR1 VR0
bit 7 bit 0
Legend:
bit 7 VREN: Comparator C1 Voltage Reference Enable bit

1 = CVREF circuit powered on
0 = CVREF circuit powered down
bit 6 VROE: Comparator C2 Voltage Reference Enable bit
1 = CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF/C2IN+ pin
0 = CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF/C2IN+ pin
bit 5 VRR: CVREF Range Selection bit
1 = Low range
0 = High range
bit 4 VRSS: Comparator VREF Range Selection bit
1 = Comparator Reference Source, CVRSRC = (VREF+) - (VREF-)
0 = Comparator Reference Source, CVRSRC = VDD - VSS
bit 3-0 VR<3:0>: CVREF Value Selection 0  VR<3:0>  15
When VRR = 1: CVREF = (VR<3:0>/24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD
TABLE 8-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE
REFERENCE MODULES
Register on
Page
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 42
ANSELH — — ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 50
CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 93
CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 94
CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL — — T1GSS C2SYNC 96
PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE 35
PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF 37
PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 41
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 50
SRCON SR1 SR0 C1SEN C2SEN PULSS PULSR — FVREN 98
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 50
VRCON VREN VROE VRR VRSS VR3 VR2 VR1 VR0 102
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator.

PIC16F882/883/884/886/887
9.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESL and ADRESH).
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
Figure 9-1 shows the block diagram of the ADC.
FIGURE 9-1: ADC BLOCK DIAGRAM
VCFG1 = 0
AVSS
VREF- VCFG1 = 1
AVDD
VCFG0 = 0
VREF+ VCFG0 = 1
AN0 0000
AN1 0001
AN2 0010
AN3 0011
AN4 0100
AN5 0101
AN6 0110
AN7 0111
ADC
AN8 1000
GO/DONE 10
AN9 1001
AN10 1010
0 = Left Justify
ADFM
AN11 1011 1 = Right Justify
AN12 1100 ADON 10
AN13 1101
VSS ADRESH ADRESL
CVREF 1110
FixedRef 1111
CHS<3:0>

PIC16F882/883/884/886/887
9.2.7 ADC REGISTER DEFINITIONS
The following registers are used to control the opera-
tion of the ADC.
Note: For ANSEL and ANSELH registers, see
Register 3-3 and Register 3-4,
respectively.
REGISTER DEFINITIONS: ADC CONTROL

REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0
ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
bit 7-6 ADCS<1:0>: A/D Conversion Clock Select bits

00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max)
bit 5-2 CHS<3:0>: Analog Channel Select bits
0000 = AN0
0001 = AN1
0010 = AN2
0011 = AN3
0100 = AN4
0101 = AN5
0110 = AN6
0111 = AN7
1000 = AN8
1001 = AN9
1010 = AN10
1011 = AN11
1100 = AN12
1101 = AN13
1110 = CVREF
1111 = Fixed Ref (0.6V fixed voltage reference)
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current

PIC16F882/883/884/886/887
REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1

R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
ADFM — VCFG1 VCFG0 — — — —
bit 7 bit 0
Legend:
bit 7 ADFM: A/D Conversion Result Format Select bit

1 = Right justified
0 = Left justified
bit 5 VCFG1: Voltage Reference bit
1 = VREF- pin
0 = VSS
bit 4 VCFG0: Voltage Reference bit
1 = VREF+ pin
0 = VDD

PIC16F882/883/884/886/887
9.3 A/D Acquisition Requirements an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
For the ADC to meet its specified accuracy, the charge time, Equation 9-1 may be used. This equation
holding capacitor (CHOLD) must be allowed to fully assumes that 1/2 LSb error is used (1024 steps for the
charge to the input channel voltage level. The Analog ADC). The 1/2 LSb error is the maximum error allowed
Input model is shown in Figure 9-4. The source for the ADC to meet its specified resolution.
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 9-4.
The maximum recommended impedance for analog
sources is 10 k. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
EQUATION 9-1: ACQUISITION TIME EXAMPLE
Assumptions: Temperature = 50°C and external impedance of 10k  5.0V V DD
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C +   Temperature - 25°C   0.05µs/°C  
The value for TC can be approximated with the following equations:
1
V AP PLIE D  1 – -------------------------- = V CHOLD ;[1] VCHOLD charged to within 1/2 lsb
 n + 1 
2 –1
–TC
 ----------
RC ;[2] VCHOLD charge response to VAPPLIED
V AP P LI ED  1 – e  = V CHOLD
 
– Tc
 ---------
1
V AP P LIED  1 – e  = V A P PLIE D  1 – --------------------------
RC
;combining [1] and [2]
   n+1 
2 –1
Solving for TC:
T C = – C HOLD  R IC + R SS + R S  ln(1/2047)
= – 10pF  1k  + 7k  + 10k   ln(0.0004885)
= 1.37 µs
Therefore:
T ACQ = 2ΜS + 1.37 ΜS +   50°C- 25°C   0.05ΜS /°C  
= 4.67 ΜS
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.

PIC16F882/883/884/886/887
FIGURE 9-4: ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
Rs ANx RIC  1k SS Rss
VA CPIN I LEAKAGE(1)
VT = 0.6V CHOLD = 10 pF
5 pF ± 500 nA
VSS/VREF-
6V
5V RSS
Legend: CPIN = Input Capacitance VDD 4V
VT = Threshold Voltage 3V
I LEAKAGE = Leakage current at the pin due to 2V
various junctions
RIC = Interconnect Resistance 5 6 7 8 9 10 11
SS = Sampling Switch Sampling Switch
CHOLD = Sample/Hold Capacitance (k)
Note 1: See Section 17.0 “Electrical Specifications”.
FIGURE 9-5: ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
ADC Output Code
1 LSB ideal
3FBh
Full-Scale
004h Transition
003h
002h
001h
000h Analog Input Voltage
1 LSB ideal
VSS/VREF- Zero-Scale VDD/VREF+

Transition

PIC16F882/883/884/886/887
REGISTER DEFINITIONS: CCP CONTROL
REGISTER 11-1: CCP1CON: ENHANCED CCP1 CONTROL REGISTER
P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0
Legend:
bit 7-6 P1M<1:0>: PWM Output Configuration bits

If CCP1M<3:2> = 00, 01, 10:
xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins
If CCP1M<3:2> = 11:
00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins
01 = Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive
10 = Half-Bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins
11 = Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive
bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0 CCP1M<3:0>: ECCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Unused (reserved)
0010 = Compare mode, toggle output on match (CCP1IF bit is set)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 or TMR2
1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low

PIC16F882/883/884/886/887
11.2 Capture/Compare/PWM (CCP2) TABLE 11-2: CCP MODE – TIMER
RESOURCES REQUIRED
The Capture/Compare/PWM module is a peripheral
which allows the user to time and control different CCP Mode Timer Resource
events. In Capture mode, the peripheral allows the Capture Timer1
timing of the duration of an event. The Compare mode
allows the user to trigger an external event when a Compare Timer1
predetermined amount of time has expired. The PWM PWM Timer2
mode can generate a Pulse-Width Modulated signal of
varying frequency and duty cycle.
The timer resources used by the module are shown in
Table 11-2.
Additional information on CCP modules is available in
the Application Note AN594, “Using the CCP Modules”
(DS00594).
REGISTER 11-2: CCP2CON: CCP2 CONTROL REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
bit 7 bit 0
Legend:

bit 5-4 DC2B<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR2L.
bit 3-0 CCP2M<3:0>: CCP2 Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP2 module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
1000 = Compare mode, set output on match (CCP2IF bit is set)
1001 = Compare mode, clear output on match (CCP2IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP2IF bit is set, CCP2 pin
is unaffected)
1011 = Compare mode, trigger special event (CCP2IF bit is set, TMR1 is reset and A/D
conversion is started if the ADC module is enabled. CCP2 pin is unaffected.)
11xx = PWM mode.

PIC16F882/883/884/886/887
11.5 PWM Mode The PWM output (Figure 11-4) has a time base
(period) and a time that the output stays high (duty
The PWM mode generates a Pulse-Width Modulated cycle).
signal on the CCPx pin. The duty cycle, period and
resolution are determined by the following registers:
FIGURE 11-4: CCP PWM OUTPUT
• PR2
Period
• T2CON
• CCPRxL
Pulse Width
• CCPxCON TMR2 = PR2
In Pulse-Width Modulation (PWM) mode, the CCP TMR2 = CCPRxL:CCPxCON<5:4>

module produces up to a 10-bit resolution PWM output TMR2 = 0
on the CCPx pin. Since the CCPx pin is multiplexed
with the PORT data latch, the TRIS for that pin must be
cleared to enable the CCPx pin output driver. 11.5.1 PWM PERIOD
Note: Clearing the CCPxCON register will The PWM period is specified by the PR2 register of
relinquish CCPx control of the CCPx pin. Timer2. The PWM period can be calculated using the
formula of Equation 11-1.
Figure 11-3 shows a simplified block diagram of PWM
operation.
EQUATION 11-1: PWM PERIOD
Figure 11-4 shows a typical waveform of the PWM
signal. PWM Period =   PR2  + 1   4  T OSC 
For a step-by-step procedure on how to set up the CCP (TMR2 Prescale Value)
module for PWM operation, see Section 11.5.7
“Setup for PWM Operation”. Note: TOSC = 1/FOSC
FIGURE 11-3: SIMPLIFIED PWM BLOCK When TMR2 is equal to PR2, the following three events
DIAGRAM occur on the next increment cycle:
CCPxCON<5:4>
• TMR2 is cleared
Duty Cycle Registers • The CCPx pin is set. (Exception: If the PWM duty
CCPRxL
cycle = 0%, the pin will not be set.)
• The PWM duty cycle is latched from CCPRxL into
CCPRxH.
CCPRxH(2) (Slave) Note: The Timer2 postscaler (see Section 7.1

CCPx “Timer2 Operation”) is not used in the
Comparator R Q determination of the PWM frequency.
(1) S
TMR2
TRIS
EQUATION 11-2: PULSE WIDTH
Comparator Pulse Width = CCPRxL:CCPxCON<5:4> 

Clear Timer2,
toggle CCPx pin and T OSC  (TMR2 Prescale Value)
latch duty cycle
PR2
Note 1: The 8-bit timer TMR2 register is concatenated EQUATION 11-3: DUTY CYCLE RATIO
with the 2-bit internal system clock (FOSC), or
2 bits of the prescaler, to create the 10-bit time
base. CCPRxL:CCPxCON<5:4>
Duty Cycle Ratio = -----------------------------------------------------------------------
2: In PWM mode, CCPRxH is a read-only register. 4  PR2 + 1 )
EQUATION 11-4: PWM RESOLUTION
log 4  PR2 + 1  
Resolution = ------------------------------------------ bits
log 2 

PIC16F882/883/884/886/887
REGISTER DEFINITIONS: PWM CONTROL
REGISTER 11-4: PWM1CON: ENHANCED PWM CONTROL REGISTER
PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0
bit 7 bit 0
Legend:
bit 7 PRSEN: PWM Restart Enable bit

1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes
away; the PWM restarts automatically
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
bit 6-0 PDC<6:0>: PWM Delay Count bits
PDCn = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal
should transition active and the actual time it transitions active.

PIC16F882/883/884/886/887
11.6.7 PULSE STEERING MODE
In Single Output mode, pulse steering allows any of the Note: The associated TRIS bits must be set to
PWM pins to be the modulated signal. Additionally, the output (‘0’) to enable the pin output driver
same PWM signal can be simultaneously available on in order to see the PWM signal on the pin.
multiple pins.
While the PWM Steering mode is active, CCP1M<1:0>
Once the Single Output mode is selected bits of the CCP1CON register select the PWM output
(CCP1M<3:2> = 11 and P1M<1:0> = 00 of the polarity for the P1<D:A> pins.
CCP1CON register), the user firmware can bring out
the same PWM signal to one, two, three or four output The PWM auto-shutdown operation also applies to
pins by setting the appropriate STR<D:A> bits of the PWM Steering mode as described in Section 11.6.4
PSTRCON register, as shown in Table 11-5. “Enhanced PWM Auto-Shutdown Mode”. An auto-
shutdown event will only affect pins that have PWM
outputs enabled.
REGISTER DEFINITIONS: PULSE STEERING CONTROL

REGISTER 11-5: PSTRCON: PULSE STEERING CONTROL REGISTER(1)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
— — — STRSYNC STRD STRC STRB STRA
bit 7 bit 0
Legend:

bit 4 STRSYNC: Steering Sync bit
1 = Output steering update occurs on next PWM period
0 = Output steering update occurs at the beginning of the instruction cycle boundary
bit 3 STRD: Steering Enable bit D
1 = P1D pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = P1D pin is assigned to port pin
bit 2 STRC: Steering Enable bit C
1 = P1C pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = P1C pin is assigned to port pin
bit 1 STRB: Steering Enable bit B
1 = P1B pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = P1B pin is assigned to port pin
bit 0 STRA: Steering Enable bit A
1 = P1A pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = P1A pin is assigned to port pin
Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> = 11 and
P1M<1:0> = 00.

PIC16F882/883/884/886/887
12.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities:
SYNCHRONOUS • Full-duplex asynchronous transmit and receive
ASYNCHRONOUS RECEIVER • Two-character input buffer
TRANSMITTER (EUSART) • One-character output buffer
• Programmable 8-bit or 9-bit character length
The Enhanced Universal Synchronous Asynchronous
• Address detection in 9-bit mode
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock • Input buffer overrun error detection
generators, shift registers and data buffers necessary • Received character framing error detection
to perform an input or output serial data transfer • Half-duplex synchronous master
independent of device program execution. The • Half-duplex synchronous slave
EUSART, also known as a Serial Communications • Programmable clock polarity in synchronous
Interface (SCI), can be configured as a full-duplex modes
asynchronous system or half-duplex synchronous
• Sleep operation
system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT The EUSART module implements the following
terminals and personal computers. Half-Duplex additional features, making it ideally suited for use in
Synchronous mode is intended for communications Local Interconnect Network (LIN) bus systems:
with peripheral devices, such as A/D or D/A integrated • Automatic detection and calibration of the baud rate
circuits, serial EEPROMs or other microcontrollers.
• Wake-up on Break reception
These devices typically do not have internal clocks for
baud rate generation and require the external clock • 13-bit Break character transmit
signal provided by a master synchronous device. Block diagrams of the EUSART transmitter and
receiver are shown in Figure 12-1 and Figure 12-2.
FIGURE 12-1: EUSART TRANSMIT BLOCK DIAGRAM

Data Bus
TXIE
Interrupt
TXREG Register TXIF
8
MSb LSb TX/CK pin
(8) Pin Buffer
• • • 0
and Control
Transmit Shift Register (TSR)
TXEN
TRMT SPEN
Baud Rate Generator FOSC
÷n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D
SYNC 1 X 0 0 0
SPBRGH SPBRG BRGH X 1 1 0 0
BRG16 X 1 0 1 0

PIC16F882/883/884/886/887
FIGURE 12-2: EUSART RECEIVE BLOCK DIAGRAM
SPEN CREN OERR RCIDL
RX/DT pin MSb RSR Register LSb

Pin Buffer Data
and Control Recovery
Stop (8) 7 ••• 1 0 START
Baud Rate Generator FOSC RX9

÷n
BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPBRGH SPBRG BRGH X 1 1 0 0 FIFO
FERR RX9D RCREG Register
BRG16 X 1 0 1 0
8
Data Bus
RCIF Interrupt
RCIE
The operation of the EUSART module is controlled

through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCTL)
These registers are detailed in Register 12-1,
Register 12-2 and Register 12-3, respectively.

PIC16F882/883/884/886/887
12.2 Clock Accuracy with The first (preferred) method uses the OSCTUNE
Asynchronous Operation register to adjust the INTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
The factory calibrates the Internal Oscillator block out- changes to the system clock source. See Section 4.5
put (INTOSC). However, the INTOSC frequency may “Internal Clock Modes” for more information.
drift as VDD or temperature changes, and this directly
The other method adjusts the value in the Baud Rate
affects the asynchronous baud rate. Two methods may
Generator. This can be done automatically with the
be used to adjust the baud rate clock, but both require
Auto-Baud Detect feature (see Section 12.3.1 “Auto-
a reference clock source of some kind.
Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
REGISTER DEFINITIONS: EUSART CONTROL

REGISTER 12-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
Legend:
bit 7 CSRC: Clock Source Select bit

Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.

PIC16F882/883/884/886/887
REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.

PIC16F882/883/884/886/887
REGISTER 12-3: BAUDCTL: BAUD RATE CONTROL REGISTER

R-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
bit 7 ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care
bit 6 RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 4 SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1 = Transmit inverted data to the RB7/TX/CK pin
0 = Transmit non-inverted data to the RB7/TX/CK pin
Synchronous mode:
1 = Data is clocked on rising edge of the clock
0 = Data is clocked on falling edge of the clock
bit 3 BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = Receiver is waiting for a falling edge. No character will be received byte RCIF will be set. WUE will
automatically clear after RCIF is set.
0 = Receiver is operating normally
Synchronous mode:
Don’t care
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care

PIC16F882/883/884/886/887
12.3 EUSART Baud Rate Generator If the system clock is changed during an active receive
(BRG) operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
The Baud Rate Generator (BRG) is an 8-bit or 16-bit make sure that the receive operation is Idle before
timer that is dedicated to the support of both the changing the system clock.
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the EXAMPLE 12-1: CALCULATING BAUD
BRG16 bit of the BAUDCTL register selects 16-bit RATE ERROR
mode.
For a device with FOSC of 16 MHz, desired baud rate
The SPBRGH, SPBRG register pair determines the of 9600, Asynchronous mode, 8-bit BRG:
period of the free running baud rate timer. In
F OS C
Asynchronous mode the multiplier of the baud rate Desired Baud Rate = ---------------------------------------------------------------------
64  [SPBRGH:SPBRG] + 1 
period is determined by both the BRGH bit of the TXSTA
register and the BRG16 bit of the BAUDCTL register. In Solving for SPBRGH:SPBRG:
Synchronous mode, the BRGH bit is ignored.
FOSC
---------------------------------------------
Table 12-3 contains the formulas for determining the Desired Baud Rate
X = --------------------------------------------- – 1
baud rate. Example 12-1 provides a sample calculation 64
for determining the baud rate and baud rate error. 16000000
------------------------
Typical baud rates and error values for various 9600
= ------------------------ – 1
asynchronous modes have been computed for your 64
convenience and are shown in Table 12-3. It may be =  25.042  = 25
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate 16000000
Calculated Baud Rate = ---------------------------
64  25 + 1 
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies. = 9615
Writing a new value to the SPBRGH, SPBRG register
Calc. Baud Rate – Desired Baud Rate
pair causes the BRG timer to be reset (or cleared). This Error = --------------------------------------------------------------------------------------------
Desired Baud Rate
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.  9615 – 9600 
= ---------------------------------- = 0.16%
9600
TABLE 12-3: BAUD RATE FORMULAS

Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)]

0 0 1 8-bit/Asynchronous
FOSC/[16 (n+1)]
1 0 x 8-bit/Synchronous FOSC/[4 (n+1)]
1 1 x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGH, SPBRG register pair
TABLE 12-4: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR

Register
on Page
BAUDCTL ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 166
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 165
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 167
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 167
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 164
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.

PIC16F882/883/884/886/887
13.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
13.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated CircuitTM (I2CTM)
- Full Master mode
- Slave mode (with general address call).
The I2C interface supports the following modes in
hardware:
• Master mode
• Multi-Master mode
• Slave mode.
13.2 Control Registers

The MSSP module has three associated registers.
These include a STATUS register and two control
registers.
Register 13-1 shows the MSSP STATUS register
(SSPSTAT), Register 13-2 shows the MSSP Control
Register 1 (SSPCON), and Register 13-3 shows the
MSSP Control Register 2 (SSPCON2).

PIC16F882/883/884/886/887
REGISTER 13-1: SSPSTAT: SSP STATUS REGISTER

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P S R/W UA BF
bit 7 bit 0
Legend:
bit 7 SMP: Sample bit

SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2 C Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high speed mode (400 kHz)
bit 6 CKE: SPI Clock Edge Select bit
CKP = 0:
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
CKP = 1:
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
bit 3 S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2 R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to
the next Start bit, Stop bit, or not ACK bit.
In I2 C Slave mode:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in Idle mode.
bit 1 UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2 C mode only):
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty

PIC16F882/883/884/886/887
REGISTER 13-2: SSPCON: SSP CONTROL REGISTER 1

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
Legend:
bit 7 WCOL: Write Collision Detect bit

Master mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started
0 = No collision
Slave mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR
is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting
data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is
initiated by writing to the SSPBUF register (must be cleared in software).
0 = No overflow
In I2 C mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit
mode (must be cleared in software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode:
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2 C Slave mode:
SCK release control
1 = Release clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2 C Master mode:
Unused in this mode
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0110 = I2C Slave mode, 7-bit address
0111 = I2C Slave mode, 10-bit address
1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))
1001 = Load Mask function
1010 = Reserved
1011 = I2C firmware controlled Master mode (Slave idle)
1100 = Reserved
1101 = Reserved
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

PIC16F882/883/884/886/887
REGISTER 13-3: SSPCON2: SSP CONTROL REGISTER 2

R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend:
bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (in I2C Master mode only)
In Master Transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (in I2C Master mode only)
In Master Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)
SCK Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enabled bit (in I2C Master mode only)
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).

PIC16F882/883/884/886/887
13.3 SPI Mode FIGURE 13-1: MSSP BLOCK DIAGRAM
(SPI MODE)
The SPI mode allows 8 bits of data to be synchronously
transmitted and received, simultaneously. All four modes Internal
Data Bus
of SPI are supported. To accomplish communication,
typically three pins are used: Read Write
• Serial Data Out (SDO) – RC5/SDO

SSPBUF Reg
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in any
Slave mode of operation: SSPSR Reg
• Slave Select (SS) – RA5/SS/AN4 SDI bit 0 Shift
Clock
13.3.1 OPERATION SDO

When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits SSPCON<5:0> and SSPSTAT<7:6>. SS Control
Enable
These control bits allow the following to be specified:
SS Edge
• Master mode (SCK is the clock output)
Select
• Slave mode (SCK is the clock input)
• Clock polarity (Idle state of SCK) 2
• Data input sample phase (middle or end of data Clock Select
output time)
SSPM<3:0>
• Clock edge (output data on rising/falling edge of SMP:CKE 4
SCK) 2 (
TMR2 Output
2 )
• Clock rate (Master mode only) Edge
Select Prescaler TOSC
• Slave Select mode (Slave mode only)
SCK 4, 16, 64
Figure 13-1 shows the block diagram of the MSSP
module, when in SPI mode. Data to TX/RX in SSPSR
TRIS bit
Note: I/O pins have diode protection to VDD and VSS.
The MSSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the buffer full-detect bit BF of the SSP-
STAT register and the interrupt flag bit SSPIF of the
PIR1 register are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit WCOL of the SSPCON register
will be set. User software must clear the WCOL bit so
that it can be determined if the following write(s) to the
SSPBUF register completed successfully.

PIC16F882/883/884/886/887
13.3.3 MASTER MODE The clock polarity is selected by appropriately program-
ming the CKP bit of the SSPCON register. This, then,
The master can initiate the data transfer at any time would give waveforms for SPI communication as
because it controls the SCK. The master determines shown in Figure 13-2, Figure 13-4 and Figure 13-5,
when the slave is to broadcast data by the software where the MSb is transmitted first. In Master mode, the
protocol. SPI clock rate (bit rate) is user programmable to be one
In Master mode, the data is transmitted/received as of the following:
soon as the SSPBUF register is written to. If the SPI is • FOSC/4 (or TCY)
only going to receive, the SDO output could be dis-
• FOSC/16 (or 4 • TCY)
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin • FOSC/64 (or 16 • TCY)
at the programmed clock rate. As each byte is • Timer2 output/2
received, it will be loaded into the SSPBUF register as This allows a maximum data rate (at 40 MHz) of
a normal received byte (interrupts and Status bits 10.00 Mbps.
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode. Figure 13-2 shows the waveforms for Master mode.
When the CKE bit of the SSPSTAT register is set, the
SDO data is valid before there is a clock edge on SCK.
The change of the input sample is shown based on the
state of the SMP bit of the SSPSTAT register. The time
when the SSPBUF is loaded with the received data is
shown.
FIGURE 13-2: SPI MODE WAVEFORM (MASTER MODE)

Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

(CKE = 1)
SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SDI
(SMP = 1) bit 0
bit7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 Cycle
SSPSR to after Q2
SSPBUF

PIC16F882/883/884/886/887
13.3.4 SLAVE MODE the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte, and becomes a floating
In Slave mode, the data is transmitted and received as output. External pull-up/pull-down resistors may be
the external clock pulses appear on SCK. When the desirable, depending on the application.
last bit is latched, the SSPIF interrupt flag bit of the
PIR1 register is set. Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
While in Slave mode, the external clock is supplied by
0100), the SPI module will reset if the SS
the external clock source on the SCK pin. This external
pin is set to VDD.
clock must meet the minimum high and low times, as
specified in the electrical specifications. 2: If the SPI is used in Slave mode with CKE
set (SSPSTAT register), then the SS pin
While in Sleep mode, the slave can transmit/receive
control must be enabled.
data. When a byte is received, the device will wake-up
from Sleep. When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
13.3.5 SLAVE SELECT a high level, or clearing the SSPEN bit.
SYNCHRONIZATION
To emulate two-wire communication, the SDO pin can
The SS pin allows a Synchronous Slave mode. The be connected to the SDI pin. When the SPI needs to
SPI must be in Slave mode with SS pin control operate as a receiver, the SDO pin can be configured
enabled (SSPCON<3:0> = 04h). The pin must not as an input. This disables transmissions from the SDO.
be driven low for the SS pin to function as an input. The SDI can always be left as an input (SDI function),
The Data Latch must be high. When the SS pin is since it cannot create a bus conflict.
low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
FIGURE 13-3: SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO bit 7 bit 6 bit 7 bit 0
SDI bit 0
Input
Sample
(SMP = 0)
SSPIF
Next Q4 Cycle
SSPBUF

PIC16F882/883/884/886/887
FIGURE 13-4: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI
Input
Sample
(SMP = 0)
SSPIF
Next Q4 Cycle
SSPBUF
FIGURE 13-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Required
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDI
(SMP = 0)
bit 7 bit 0
Input
Sample
(SMP = 0)
SSPIF
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF

PIC16F882/883/884/886/887
13.3.6 SLEEP OPERATION 13.3.8 BUS MODE COMPATIBILITY
In Master mode, all module clocks are halted, and the Table 13-1 shows the compatibility between the
transmission/reception will remain in that state until the standard SPI modes and the states of the CKP and
device wakes from Sleep. After the device returns to CKE control bits.
normal mode, the module will continue to transmit/
receive data. TABLE 13-1: SPI BUS MODES
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the Standard SPI Mode Control Bits State
device to be placed in Sleep mode and data to be Terminology CKP CKE
shifted into the SPI transmit/receive shift register.
0, 0 0 1
When all eight bits have been received, the MSSP
interrupt flag bit will be set and, if enabled, will wake the 0, 1 0 0
device from Sleep. 1, 0 1 1
1, 1 1 0
13.3.7 EFFECTS OF A RESET
There is also a SMP bit that controls when the data will
A Reset disables the MSSP module and terminates the be sampled.
current transfer.
TABLE 13-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Register on
Page
INTCON GIE/GIEH PEIE/GIEL T0IE INTE RBIE T0IF INTF RBIF 33

SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register 187
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 185
SSPSTAT SMP CKE D/A P S R/W UA BF 184
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 55
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in
SPI mode.
Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.

PIC16F882/883/884/886/887
13.4 MSSP I2C Operation The SSPCON register allows control of the I 2C
operation. The SSPM<3:0> mode selection bits
The MSSP module in I 2C mode, fully implements all (SSPCON register) allow one of the following I 2C modes
master and slave functions (including general call to be selected:
support) and provides interrupts on Start and Stop bits in
hardware, to determine a free bus (Multi-Master mode). • I2C Master mode, clock = OSC/4 (SSPADD +1)
The MSSP module implements the standard mode • I 2C Slave mode (7-bit address)
specifications, as well as 7-bit and 10-bit addressing. • I 2C Slave mode (10-bit address)
Two pins are used for data transfer. These are the • I 2C Slave mode (7-bit address), with Start and
RC3/SCK/SCL pin, which is the clock (SCL), and the Stop bit interrupts enabled
RC4/SDI/SDA pin, which is the data (SDA). The user • I 2C Slave mode (10-bit address), with Start and
must configure these pins as inputs or outputs through Stop bit interrupts enabled
the TRISC<4:3> bits. • I 2C firmware controlled master operation, slave is
The MSSP module functions are enabled by setting idle
MSSP Enable bit SSPEN of the SSPCON register. Selection of any I 2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open drain,
FIGURE 13-6: MSSP BLOCK DIAGRAM provided these pins are programmed to be inputs by
(I2C MODE) setting the appropriate TRISC bits.
Internal
13.4.1 SLAVE MODE
Data Bus
In Slave mode, the SCL and SDA pins must be
Read Write configured as inputs (TRISC<4:3> set). The MSSP
module will override the input state with the output data
RC3/SCK/SCL
SSPBUF Reg when required (slave-transmitter).
When an address is matched, or the data transfer after
Shift
Clock an address match is received, the hardware
automatically will generate the Acknowledge (ACK)
SSPSR Reg
pulse and load the SSPBUF register with the received
RC4/ MSb LSb value currently in the SSPSR register.
SDI/
SDA If either or both of the following conditions are true, the
Match Detect Addr Match MSSP module will not give this ACK pulse:
a) The buffer full bit BF (SSPCON register) was set
SSPMSK Reg
before the transfer was received.
b) The overflow bit SSPOV (SSPCON register)
was set before the transfer was received.
SSPADD Reg
In this event, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF of the PIR1 register is
Start and Set, Reset
S, P bits set. The BF bit is cleared by reading the SSPBUF
Stop bit Detect
(SSPSTAT Reg) register, while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
The MSSP module has these six registers for I2C
and parameter #101.
operation:
• MSSP Control Register 1 (SSPCON)
• MSSP Control Register 2 (SSPCON2)
• MSSP STATUS register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address register (SSPADD)
• MSSP Mask register (SSPMSK)

PIC16F882/883/884/886/887
13.4.3 MASTER MODE 13.4.4 I2C™ MASTER MODE SUPPORT
Master mode of operation is supported by interrupt Master mode is enabled by setting and clearing the
generation on the detection of the Start and Stop appropriate SSPM bits in SSPCON and by setting the
conditions. The Stop (P) and Start (S) bits are cleared SSPEN bit. Once Master mode is enabled, the user
from a Reset, or when the MSSP module is disabled. has the following six options:
Control of the I 2C bus may be taken when the P bit is 1. Assert a Start condition on SDA and SCL.
set, or the bus is idle, with both the S and P bits clear.
2. Assert a Repeated Start condition on SDA and
In Master mode, the SCL and SDA lines are manipu- SCL.
lated by the MSSP hardware. 3. Write to the SSPBUF register initiating
The following events will cause SSP Interrupt Flag bit, transmission of data/address.
SSPIF, to be set (SSP Interrupt if enabled): 4. Generate a Stop condition on SDA and SCL.
• Start condition 5. Configure the I2C port to receive data.
• Stop condition 6. Generate an Acknowledge condition at the end
• Data transfer byte transmitted/received of a received byte of data.
• Acknowledge transmit
• Repeated Start condition Note: The MSSP module, when configured in I2C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
imitate transmission, before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
FIGURE 13-10: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)
Internal SSPM<3:0>
Data Bus SSPADD<6:0>
Read Write
SSPBUF Baud
Rate
Generator
SDA Shift
Clock Arbitrate/WCOL Detect
SDA In Clock
SSPSR
(hold off clock source)
MSb LSb
Receive Enable
Start bit, Stop bit,

Clock Cntl
Acknowledge
Generate
SCL
Start bit Detect

Stop bit Detect
SCL In Write Collision Detect Set/Reset, S, P, WCOL (SSPSTAT)
Clock Arbitration Set SSPIF, BCLIF
Bus Collision State Counter for Reset ACKSTAT, PEN (SSPCON2)
End of XMIT/RCV

PIC16F882/883/884/886/887
13.4.4.1 I2C™ Master Mode Operation A typical transmit sequence would go as follows:
The master device generates all of the serial clock a) The user generates a Start condition by setting
pulses and the Start and Stop conditions. A transfer is the Start Enable (SEN) bit (SSPCON2 register).
ended with a Stop condition or with a Repeated Start b) SSPIF is set. The MSSP module will wait the
condition. Since the Repeated Start condition is also required start time before any other operation
the beginning of the next serial transfer, the I2C bus will takes place.
not be released. c) The user loads the SSPBUF with the address to
In Master Transmitter mode, serial data is output transmit.
through SDA, while SCL outputs the serial clock. The d) Address is shifted out the SDA pin until all eight
first byte transmitted contains the slave address of the bits are transmitted.
receiving device (7 bits) and the Read/Write (R/W) bit. e) The MSSP module shifts in the ACK bit from the
In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the
transmitted eight bits at a time. After each byte is trans- ACKSTAT bit (SSPCON2 register).
mitted, an Acknowledge bit is received. Start and Stop
f) The MSSP module generates an interrupt at the
conditions are output to indicate the beginning and the
end of the ninth clock cycle by setting the SSPIF
end of a serial transfer.
bit.
In Master Receive mode, the first byte transmitted con- g) The user loads the SSPBUF with eight bits of
tains the slave address of the transmitting device data.
(7 bits) and the R/W bit. In this case, the R/W bit will be
h) Data is shifted out the SDA pin until all eight bits
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
are transmitted.
address followed by a ‘1’ to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial i) The MSSP module shifts in the ACK bit from the
clock. Serial data is received eight bits at a time. After slave device and writes its value into the
each byte is received, an Acknowledge bit is transmit- ACKSTAT bit (SSPCON2 register).
ted. Start and Stop conditions indicate the beginning j) The MSSP module generates an interrupt at the
and end of transmission. end of the ninth clock cycle by setting the SSPIF
bit.
The Baud Rate Generator used for the SPI mode oper-
ation is now used to set the SCL clock frequency for k) The user generates a Stop condition by setting
either 100 kHz, 400 kHz, or 1 MHz I2C operation. The the Stop Enable bit PEN (SSPCON2 register).
Baud Rate Generator reload value is contained in the l) Interrupt is generated once the Stop condition is
lower 7 bits of the SSPADD register. The Baud Rate complete.
Generator will automatically begin counting on a write
to the SSPBUF. Once the given operation is complete
(i.e., transmission of the last data bit is followed by
ACK), the internal clock will automatically stop counting
and the SCL pin will remain in its last state.

FIGURE 13-15:
Write SSPCON2<0> SEN = 1 ACKSTAT in

Start condition begins SSPCON2 = 1
From slave, clear ACKSTAT bit SSPCON2<6>
SEN = 0
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0 of 10-bit Address ACK
 2006-2012 Microchip Technology Inc.

SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
SSPBUF written with 7-bit address and R/W

start transmit
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SCL held low
while CPU
responds to SSPIF
SSPIF
Cleared in software service routine
Cleared in software From SSP interrupt
Cleared in software
BF
SSPBUF written SSPBUF is written in software

SEN
After Start condition, SEN cleared by hardware.
PEN
R/W
I 2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
DS41291G-page 203
PIC16F882/883/884/886/887
FIGURE 13-16:
DS41291G-page 204
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
Write to SSPCON2<0> (SEN = 1)
Begin Start Condition ACK from Master Set ACKEN start Acknowledge sequence
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSPCON2<3>, (RCEN = 1)
PEN bit = 1
Write to SSPBUF occurs here RCEN cleared RCEN = 1 start RCEN cleared
automatically next receive automatically written here
Start XMIT ACK from Slave
Transmit Address to Slave R/W = 1 Receiving Data from Slave Receiving Data from Slave
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Bus Master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSPIF at end
of receive Set SSPIF interrupt
Set SSPIF interrupt at end of Acknow-
at end of receive Set SSPIF interrupt ledge sequence
at end of Acknowledge
SSPIF sequence
Set P bit
SDA = 0, SCL = 1 Cleared in software Cleared in software Cleared in software Cleared in software Cleared in (SSPSTAT<4>)
while CPU software and SSPIF
responds to SSPIF
PIC16F882/883/884/886/887
BF
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPOV
SSPOV is set because

SSPBUF is still full
ACKEN
I 2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
 2006-2012 Microchip Technology Inc.

PIC16F882/883/884/886/887
14.1 Configuration Bits
Note: Address 2007h and 2008h are beyond the
The Configuration bits can be programmed (read as user program memory space. It belongs to
‘0’), or left unprogrammed (read as ‘1’) to select various the special configuration memory space
device configurations as shown in Register 14-1. (2000h-3FFFh), which can be accessed
These bits are mapped in program memory location only during programming. See “PIC16F88X
2007h and 2008h, respectively. Memory Programming Specification”
(DS41287) for more information.
REGISTER DEFINITIONS: CONFIGURATION WORDS

REGISTER 14-1: CONFIG1: CONFIGURATION WORD REGISTER 1
DEBUG LVP FCMEN IESO BOREN<1:0>

bit 13 bit 8
CPD CP MCLRE PWRTE WDTE FOSC<2:0>

bit 7 bit 0
bit 13 DEBUG: In-Circuit Debugger Mode bit

1 = In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger
bit 12 LVP: Low Voltage Programming Enable bit
1 = RB3/PGM pin has PGM function, low voltage programming enabled
0 = RB3 pin is digital I/O, HV on MCLR must be used for programming
bit 11 FCMEN: Fail-Safe Clock Monitor Enabled bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 10 IESO: Internal External Switchover bit
1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled
bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1)
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the PCON register
00 = BOR disabled
bit 7 CPD: Data Code Protection bit(2)
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
bit 6 CP: Code Protection bit(3)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 5 MCLRE: RE3/MCLR pin function select bit(4)
1 = RE3/MCLR pin function is MCLR
0 = RE3/MCLR pin function is digital input, MCLR internally tied to VDD
bit 4 PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled and can be enabled by SWDTEN bit of the WDTCON register
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
110 = RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
100 = INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off.
3: The entire program memory will be erased when the code protection is turned off.
4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

PIC16F882/883/884/886/887
REGISTER 14-2: CONFIG2: CONFIGURATION WORD REGISTER 2
— — — WRT<1:0> BOR4V
bit 13 bit 8
— — — — — — — —
bit 7 bit 0

bit 10-9 WRT<1:0>: Flash Program Memory Self Write Enable bits
PIC16F883/PIC16F884
00 = 0000h to 07FFh write protected, 0800h to 0FFFh may be modified by EECON control
11 = Write protection off
PIC16F886/PIC16F887
00 = 0000h to 0FFFh write protected, 1000h to 1FFFh may be modified by EECON control
PIC16F882
00 = 0000h to 03FFh write protected, 0400h to 07FFh may be modified by EECON control
01 = 0000h to 00FFh write protected, 0100h to 07FFh may be modified by EECON control
bit 8 BOR4V: Brown-out Reset Selection bit

0 = Brown-out Reset set to 2.1V
1 = Brown-out Reset set to 4.0V

PIC16F882/883/884/886/887
14.2 Reset They are not affected by a WDT Wake-up since this is
viewed as the resumption of normal operation. TO and
The PIC16F882/883/884/886/887 devices differentiate PD bits are set or cleared differently in different Reset
between various kinds of Reset: situations, as indicated in Table 14-2. These bits are
a) Power-on Reset (POR) used in software to determine the nature of the Reset.
b) WDT Reset during normal operation See Table 14-5 for a full description of Reset states of
all registers.
c) WDT Reset during Sleep
d) MCLR Reset during normal operation A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 14-1.
e) MCLR Reset during Sleep
f) Brown-out Reset (BOR) The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 17.0 “Electrical
Some registers are not affected in any Reset condition; Specifications” for pulse-width specifications.
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
• Power-on Reset
• MCLR Reset
• MCLR Reset during Sleep
• WDT Reset
• Brown-out Reset (BOR)
FIGURE 14-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/VPP pin
Sleep
WDT WDT
Module Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out(1)
Reset BOREN
SBOREN S
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter R Q
OSC1/
CLKI pin
PWRT
LFINTOSC 11-bit Ripple Counter
Enable PWRT
Enable OST
Note 1: Refer to the Configuration Word Register 1 (Register 14-1).

PIC16F882/883/884/886/887
14.3 Interrupts The following interrupt flags are contained in the PIR2
register:
The PIC16F882/883/884/886/887 devices have multi-
ple interrupt sources: • Fail-Safe Clock Monitor Interrupt
• 2 Comparator Interrupts
• External Interrupt RB0/INT
• EEPROM Data Write Interrupt
• Timer0 Overflow Interrupt
• Ultra Low-Power Wake-up Interrupt
• PORTB Change Interrupts
• CCP2 Interrupt
• 2 Comparator Interrupts
• A/D Interrupt When an interrupt is serviced:
• Timer1 Overflow Interrupt • The GIE is cleared to disable any further interrupt.
• Timer2 Match Interrupt • The return address is pushed onto the stack.
• EEPROM Data Write Interrupt • The PC is loaded with 0004h.
• Fail-Safe Clock Monitor Interrupt For external interrupt events, such as the INT pin,
• Enhanced CCP Interrupt PORTB change interrupts, the interrupt latency will be
• EUSART Receive and Transmit Interrupts three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
• Ultra Low-Power Wake-up Interrupt
Figure 14-8). The latency is the same for one or
• MSSP Interrupt two-cycle instructions. Once in the Interrupt Service
The Interrupt Control register (INTCON) and Peripheral Routine, the source(s) of the interrupt can be
Interrupt Request Register 1 (PIR1) record individual determined by polling the interrupt flag bits. The
interrupt requests in flag bits. The INTCON register interrupt flag bit(s) must be cleared in software before
also has individual and global interrupt enable bits. re-enabling interrupts to avoid multiple interrupt
requests.
A Global Interrupt Enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts, or disables (if Note 1: Individual interrupt flag bits are set,
cleared) all interrupts. Individual interrupts can be regardless of the status of their
disabled through their corresponding enable bits in the corresponding mask bit or the GIE bit.
INTCON, PIE1 and PIE2 registers, respectively. GIE is
2: When an instruction that clears the GIE
cleared on Reset.
bit is executed, any interrupts that were
The Return from Interrupt instruction, RETFIE, exits pending for execution in the next cycle
the interrupt routine, as well as sets the GIE bit, which are ignored. The interrupts, which were
re-enables unmasked interrupts. ignored, are still pending to be serviced
The following interrupt flags are contained in the when the GIE bit is set again.
INTCON register: For additional information on Timer1, Timer2,
• INT Pin Interrupt comparators, A/D, data EEPROM, EUSART, MSSP or
• PORTB Change Interrupts Enhanced CCP modules, refer to the respective
peripheral section.
• Timer0 Overflow Interrupt
The peripheral interrupt flags are contained in the PIR1 14.3.1 RB0/INT INTERRUPT
and PIR2 registers. The corresponding interrupt enable
External interrupt on RB0/INT pin is edge-triggered;
bits are contained in PIE1 and PIE2 registers.
either rising if the INTEDG bit (OPTION_REG<6>) is
The following interrupt flags are contained in the PIR1 set, or falling, if the INTEDG bit is clear. When a valid
register: edge appears on the RB0/INT pin, the INTF bit
• A/D Interrupt (INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
• EUSART Receive and Transmit Interrupts
bit must be cleared in software in the Interrupt Service
• Timer1 Overflow Interrupt Routine before re-enabling this interrupt. The RB0/INT
• Synchronous Serial Port (SSP) Interrupt interrupt can wake-up the processor from Sleep, if the
• Enhanced CCP1 Interrupt INTE bit was set prior to going into Sleep. The status of
• Timer1 Overflow Interrupt the GIE bit decides whether or not the processor
• Timer2 Match Interrupt branches to the interrupt vector following wake-up
(0004h). See Section 14.6 “Power-Down Mode
(Sleep)” for details on Sleep and Figure 14-10 for
timing of wake-up from Sleep through RB0/INT
interrupt.

PIC16F882/883/884/886/887
14.3.2 TIMER0 INTERRUPT 14.3.3 PORTB INTERRUPT
An overflow (FFh  00h) in the TMR0 register will set An input change on PORTB change sets the RBIF
the T0IF (INTCON<2>) bit. The interrupt can be (INTCON<0>) bit. The interrupt can be
enabled/disabled by setting/clearing T0IE (INTCON<5>) enabled/disabled by setting/clearing the RBIE
bit. See Section 5.0 “Timer0 Module” for operation of (INTCON<3>) bit. Plus, individual pins can be
the Timer0 module. configured through the IOCB register.
Note: If a change on the I/O pin should occur
when the read operation is being
executed (start of the Q2 cycle), then the
RBIF interrupt flag may not get set. See
Section 3.4.3 “Interrupt-on-Change” for
more information.
FIGURE 14-7: INTERRUPT LOGIC
IOC-RB0
IOCB0
IOC-RB1
IOCB1
IOC-RB2 BCLIF
IOCB2 BCLIE
IOC-RB3 SSPIF
IOCB3 SSPIE
IOC-RB4 TXIF
IOCB4 TXIE
IOC-RB5 RCIF
IOCB5 RCIE Wake-up (If in Sleep mode)(1)
T0IF
IOC-RB6 TMR2IF T0IE
Interrupt to CPU
IOCB6 TMR2IE INTF
INTE
IOC-RB7 TMR1IF RBIF
IOCB7 TMR1IE
RBIE
C1IF
C1IE PEIE
C2IF GIE
C2IE
ADIF
ADIE
EEIF
EEIE
Note 1: Some peripherals depend upon the
OSFIF system clock for operation. Since the
OSFIE system clock is suspended during
Sleep, these peripherals will not wake
CCP1IF the part from Sleep. See Section 14.6.1
CCP1IE
“Wake-up from Sleep”.
CCP2IF
CCP2IE
ULPWUIF
ULPWUIE

PIC16F882/883/884/886/887
FIGURE 14-8: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF flag (5) Interrupt Latency (2)
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC PC PC + 1 PC + 1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h)
Instruction Dummy Cycle Dummy Cycle Inst (0004h)

Inst (PC – 1) Inst (PC)
Executed
Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 17.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 14-6: SUMMARY OF INTERRUPT REGISTERS

Register on
Page
PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE 35
PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF 37
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the interrupt module.

PIC16F882/883/884/886/887
14.4 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W and STATUS
registers). This must be implemented in software.
Since the upper 16 bytes of all GPR banks are
common in the PIC16F882/883/884/886/887 (see
Figures 2-2 and 2-3), temporary holding registers,
W_TEMP and STATUS_TEMP, should be placed in
here. These 16 locations do not require banking and
therefore, make it easier to context save and restore.
The same code shown in Example 14-1 can be used
to:
• Store the W register
• Store the STATUS register
• Execute the ISR code
• Restore the Status (and Bank Select Bit register)
• Restore the W register
Note: The PIC16F882/883/884/886/887 devices
normally do not require saving the
PCLATH. However, if computed GOTOs
are used in the ISR and the main code,
the PCLATH must be saved and restored
in the ISR.
EXAMPLE 14-1: SAVING STATUS AND W REGISTERS IN RAM

MOVWF W_TEMP ;Copy W to TEMP register
SWAPF STATUS,W ;Swap status to be saved into W
;Swaps are used because they do not affect the status bits
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
:
:(ISR) ;Insert user code here
:
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W

PIC16F882/883/884/886/887
14.5 Watchdog Timer (WDT) 14.5.2 WDT CONTROL
The WDT has the following features: The WDTE bit is located in the Configuration Word
Register 1. When set, the WDT runs continuously.
• Operates from the LFINTOSC (31 kHz)
When the WDTE bit in the Configuration Word
• Contains a 16-bit prescaler
Register 1 is set, the SWDTEN bit of the WDTCON
• Shares an 8-bit prescaler with Timer0 register has no effect. If WDTE is clear, then the
• Time-out period is from 1 ms to 268 seconds SWDTEN bit can be used to enable and disable the
• Configuration bit and software controlled WDT. Setting the bit will enable it and clearing the bit
WDT is cleared under certain conditions described in will disable it.
Table 14-7. The PSA and PS<2:0> bits of the OPTION register
have the same function as in previous versions of the
14.5.1 WDT OSCILLATOR PIC16F882/883/884/886/887 family of microcon-
The WDT derives its time base from the 31 kHz trollers. See Section 5.0 “Timer0 Module” for more
LFINTOSC. The LTS bit of the OSCCON register does information.
not reflect that the LFINTOSC is enabled.
The value of WDTCON is ‘---0 1000’ on all Resets.
This gives a nominal time base of 17 ms.
Note: When the Oscillator Start-up Timer (OST)
is invoked, the WDT is held in Reset,
because the WDT Ripple Counter is used
by the OST to perform the oscillator delay
count. When the OST count has expired,
the WDT will begin counting (if enabled).
FIGURE 14-9: WATCHDOG TIMER BLOCK DIAGRAM

From TMR0 Clock Source 0
Prescaler(1)
1
16-bit WDT Prescaler
PSA
PS<2:0>
31 kHz
WDTPS<3:0>
LFINTOSC Clock
0 1
PSA
WDTE from the Configuration Word Register 1

SWDTEN from WDTCON
WDT Time-out
Note 1: This is the shared Timer0/WDT prescaler. See Section 5.1.3 “Software Programmable Prescaler” for more information.
TABLE 14-7: WDT STATUS

Conditions WDT
WDTE = 0 Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST

PIC16F882/883/884/886/887
REGISTER 14-3: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN(1)
bit 7 bit 0
Legend:

bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits
Bit Value = Prescale Rate
0000 = 1:32
0001 = 1:64
0010 = 1:128
0011 = 1:256
0100 = 1:512 (Reset value)
0101 = 1:1024
0110 = 1:2048
0111 = 1:4096
1000 = 1:8192
1001 = 1:16384
1010 = 1:32768
1011 = 1:65536
1100 = reserved
1101 = reserved
1110 = reserved
1111 = reserved
bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer(1)
1 = WDT is turned on
0 = WDT is turned off (Reset value)
Note 1: If WDTE Configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE
Configuration bit = 0, then it is possible to turn WDT on/off with this control bit.
TABLE 14-8: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Register
on Page
OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 32
WDTCON — — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN 229
Legend: Shaded cells are not used by the Watchdog Timer.
TABLE 14-9: SUMMARY OF CONFIGURATION WORD ASSOCIATED WITH WATCHDOG TIMER

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page
CONFIG1(1) 13:8 — — DEBUG LVP FCMEN IESO BOREN 1 BOREN0 214

7:0 CPD CP MCLRE PWRTE WDTE FOSC 2 FOSC 1 FOSC 0
Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used by the Watchdog Timer.
Note 1: See Configuration Word Register 1 (Register 14-1) for operation of all register bits.

PIC16F882/883/884/886/887
TABLE 15-2: PIC16F882/883/884/886/887 INSTRUCTION SET
Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected
BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 1, 2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1, 2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW – Clear W 1 00 0001 0xxx xxxx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 1, 2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 1, 2
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2, 3
INCF f, d Increment f 1 00 1010 dfff ffff Z 1, 2
INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2, 3
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1, 2
MOVF f, d Move f 1 00 1000 dfff ffff Z 1, 2
MOVWF f Move W to f 1 00 0000 lfff ffff
NOP – No Operation 1 00 0000 0xx0 0000
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1, 2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1, 2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 1, 2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1, 2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 1, 2
BSF f, b Bit Set f 1 01 01bb bfff ffff 1, 2
BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3
LITERAL AND CONTROL OPERATIONS
ADDLW k Add literal and W 1 11 111x kkkk kkkk C, DC, Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
GOTO k Go to address 2 10 1kkk kkkk kkkk
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLW k Move literal to W 1 11 00xx kkkk kkkk
RETFIE – Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 01xx kkkk kkkk
RETURN – Return from Subroutine 2 00 0000 0000 1000
SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD
SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C, DC, Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.

PIC16F882/883/884/886/887: 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers

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PIC16F882/883/884/886/887

28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers

High-Performance RISC CPU: Peripheral Features:

 2006-2012 Microchip Technology Inc. DS41291G-page 1

 2006-2012 Microchip Technology Inc. DS41291G-page 7

STATUS Reg PORTC

Note 1: PIC16F884 only.

 2006-2012 Microchip Technology Inc. DS41291G-page 17

 2006-2012 Microchip Technology Inc. DS41291G-page 27

REGISTER DEFINITIONS: STATUS

 2006-2012 Microchip Technology Inc. DS41291G-page 31

Note: To achieve a 1:1 prescaler assignment for

REGISTER DEFINITIONS: OPTION REGISTER

bit 7 RBPU: PORTB Pull-up Enable bit

000 1:2 1:1

DS41291G-page 32  2006-2012 Microchip Technology Inc.

Note: Interrupt flag bits are set when an interrupt

REGISTER DEFINITIONS: INTERRUPT CONTROL

bit 7 GIE: Global Interrupt Enable bit

Note 1: IOCB register must also be enabled.

 2006-2012 Microchip Technology Inc. DS41291G-page 33

Note: Bit PEIE of the INTCON register must be

REGISTER DEFINITIONS: PIE1

bit 7 Unimplemented: Read as ‘0’

DS41291G-page 34  2006-2012 Microchip Technology Inc.

Note: Bit PEIE of the INTCON register must be

REGISTER DEFINITIONS: PIE2

bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

 2006-2012 Microchip Technology Inc. DS41291G-page 35

Note: Interrupt flag bits are set when an interrupt

REGISTER DEFINITIONS: PIR1

bit 7 Unimplemented: Read as ‘0’

DS41291G-page 36  2006-2012 Microchip Technology Inc.

REGISTER DEFINITIONS: PIR2

bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

 2006-2012 Microchip Technology Inc. DS41291G-page 37

REGISTER DEFINITIONS: PCON

bit 7-6 Unimplemented: Read as ‘0’

DS41291G-page 38  2006-2012 Microchip Technology Inc.

PCLATH<4:0> 8 2: There are no instructions/mnemonics

 2006-2012 Microchip Technology Inc. DS41291G-page 39

Direct Addressing Indirect Addressing

RP1 RP0 6 From Opcode 0 IRP 7 File Select Register 0

Bank Select Location Select Bank Select Location Select

DS41291G-page 40  2006-2012 Microchip Technology Inc.

REGISTER 3-1: PORTA: PORTA REGISTER

bit 7-0 RA<7:0>: PORTA I/O Pin bit

REGISTER 3-2: TRISA: PORTA TRI-STATE REGISTER

bit 7-0 TRISA<7:0>: PORTA Tri-State Control bit

Note 1: TRISA<7:6> always reads ‘1’ in XT, HS and LP Oscillator modes.

 2006-2012 Microchip Technology Inc. DS41291G-page 41

3.2.1 ANSEL REGISTER

REGISTER 3-3: ANSEL: ANALOG SELECT REGISTER

bit 7-0 ANS<7:0>: Analog Select bits

DS41291G-page 42  2006-2012 Microchip Technology Inc.

 2006-2012 Microchip Technology Inc. DS41291G-page 49

REGISTER 3-4: ANSELH: ANALOG SELECT HIGH REGISTER

bit 7-6 Unimplemented: Read as ‘0’

REGISTER 3-5: PORTB: PORTB REGISTER

bit 7-0 RB<7:0>: PORTB I/O Pin bit

REGISTER 3-6: TRISB: PORTB TRI-STATE REGISTER

bit 7-0 TRISB<7:0>: PORTB Tri-State Control bit

DS41291G-page 50  2006-2012 Microchip Technology Inc.