LCD TV: Service Manual

Internal Use Only
North/Latin America http://aic.lgservice.com

Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com
LCD TV
SERVICE MANUAL
CHASSIS : LJ91T
MODEL : 32SL80YD 42SL80YD-SA
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL61862414 (0911-REV01) Printed in Korea

CONTENTS
CONTENTS .............................................................................................. 2
PRODUCT SAFETY ..................................................................................3
SPECIFICATION ........................................................................................6
ADJUSTMENT INSTRUCTION ...............................................................14
TROUBLE SHOOTING ............................................................................17
BLOCK DIAGRAM...................................................................................58
EXPLODED VIEW .................................................................................. 59
SVC. SHEET ...............................................................................................
Copyright LG Electronics. Inc. All right reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5K/10watt resistor in parallel with a 0.15uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1W), keep the resistor 10mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.
AC Volt-meter
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed

metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical Good Earth Ground
such as WATER PIPE,
shock. CONDUIT etc.
To Instrument’s
0.15uF
exposed
Leakage Current Cold Check(Antenna Cold Check) METALLIC PARTS
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC 1.5 Kohm/10W
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc. When 25A is impressed between Earth and 2nd Ground
If the exposed metallic part has a return path to the chassis, the for 1 second, Resistance must be less than 0.1 Ω
measured resistance should be between 1MΩ and 5.2MΩ. *Base on Adjustment standard
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service unit under test.
manual and its supplements and addenda, read and follow the 2. After removing an electrical assembly equipped with ES
SAFETY PRECAUTIONS on page 3 of this publication. devices, place the assembly on a conductive surface such as
NOTE: If unforeseen circumstances create conflict between the aluminum foil, to prevent electrostatic charge buildup or
following servicing precautions and any of the safety precautions on exposure of the assembly.
page 3 of this publication, always follow the safety precautions. 3. Use only a grounded-tip soldering iron to solder or unsolder ES
Remember: Safety First. devices.
4. Use only an anti-static type solder removal device. Some solder
General Servicing Precautions removal devices not classified as "anti-static" can generate
1. Always unplug the receiver AC power cord from the AC power electrical charges sufficient to damage ES devices.
source before; 5. Do not use freon-propelled chemicals. These can generate
a. Removing or reinstalling any component, circuit board electrical charges sufficient to damage ES devices.
module or any other receiver assembly. 6. Do not remove a replacement ES device from its protective
b. Disconnecting or reconnecting any receiver electrical plug or package until immediately before you are ready to install it.
other electrical connection. (Most replacement ES devices are packaged with leads
c. Connecting a test substitute in parallel with an electrolytic electrically shorted together by conductive foam, aluminum foil
capacitor in the receiver. or comparable conductive material).
CAUTION: A wrong part substitution or incorrect polarity 7. Immediately before removing the protective material from the
installation of electrolytic capacitors may result in an leads of a replacement ES device, touch the protective material
explosion hazard. to the chassis or circuit assembly into which the device will be
installed.
2. Test high voltage only by measuring it with an appropriate high CAUTION: Be sure no power is applied to the chassis or circuit,
voltage meter or other voltage measuring device (DVM, and observe all other safety precautions.
FETVOM, etc) equipped with a suitable high voltage probe. 8. Minimize bodily motions when handling unpackaged
Do not test high voltage by "drawing an arc". replacement ES devices. (Otherwise harmless motion such as
3. Do not spray chemicals on or near this receiver or any of its the brushing together of your clothes fabric or the lifting of your
assemblies. foot from a carpeted floor can generate static electricity
4. Unless specified otherwise in this service manual, clean sufficient to damage an ES device.)
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable General Soldering Guidelines
non-abrasive applicator; 10% (by volume) Acetone and 90% (by 1. Use a grounded-tip, low-wattage soldering iron and appropriate
volume) isopropyl alcohol (90%-99% strength) tip size and shape that will maintain tip temperature within the
CAUTION: This is a flammable mixture. range or 500°F to 600°F.
Unless specified otherwise in this service manual, lubrication of 2. Use an appropriate gauge of RMA resin-core solder composed
contacts in not required. of 60 parts tin/40 parts lead.
5. Do not defeat any plug/socket B+ voltage interlocks with which 3. Keep the soldering iron tip clean and well tinned.
receivers covered by this service manual might be equipped. 4. Thoroughly clean the surfaces to be soldered. Use a mall wire-
6. Do not apply AC power to this instrument and/or any of its bristle (0.5 inch, or 1.25cm) brush with a metal handle.
electrical assemblies unless all solid-state device heat sinks are Do not use freon-propelled spray-on cleaners.
correctly installed. 5. Use the following unsoldering technique
7. Always connect the test receiver ground lead to the receiver a. Allow the soldering iron tip to reach normal temperature.
chassis ground before connecting the test receiver positive (500°F to 600°F)
lead. b. Heat the component lead until the solder melts.
Always remove the test receiver ground lead last. c. Quickly draw the melted solder with an anti-static, suction-
8. Use with this receiver only the test fixtures specified in this type solder removal device or with solder braid.
service manual. CAUTION: Work quickly to avoid overheating the circuit
CAUTION: Do not connect the test fixture ground strap to any board printed foil.
heat sink in this receiver. 6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
Electrostatically Sensitive (ES) Devices (500°F to 600°F)
Some semiconductor (solid-state) devices can be damaged easily b. First, hold the soldering iron tip and solder the strand against
by static electricity. Such components commonly are called the component lead until the solder melts.
Electrostatically Sensitive (ES) Devices. Examples of typical ES c. Quickly move the soldering iron tip to the junction of the
devices are integrated circuits and some field-effect transistors and component lead and the printed circuit foil, and hold it there
semiconductor "chip" components. The following techniques only until the solder flows onto and around both the
should be used to help reduce the incidence of component component lead and the foil.
damage caused by static by static electricity. CAUTION: Work quickly to avoid overheating the circuit
1. Immediately before handling any semiconductor component or board printed foil.
semiconductor-equipped assembly, drain off any electrostatic d. Closely inspect the solder area and remove any excess or
charge on your body by touching a known earth ground. splashed solder with a small wire-bristle brush.
Alternatively, obtain and wear a commercially available
discharging wrist strap device, which should be removed to
prevent potential shock reasons prior to applying power to the
IC Remove/Replacement
Some chassis circuit boards have slotted holes (oblong) through Circuit Board Foil Repair
which the IC leads are inserted and then bent flat against the Excessive heat applied to the copper foil of any printed circuit
circuit foil. When holes are the slotted type, the following technique board will weaken the adhesive that bonds the foil to the circuit
should be used to remove and replace the IC. When working with board causing the foil to separate from or "lift-off" the board. The
boards using the familiar round hole, use the standard technique following guidelines and procedures should be followed whenever
as outlined in paragraphs 5 and 6 above. this condition is encountered.
Removal At IC Connections
1. Desolder and straighten each IC lead in one operation by gently To repair a defective copper pattern at IC connections use the
prying up on the lead with the soldering iron tip as the solder following procedure to install a jumper wire on the copper pattern
melts. side of the circuit board. (Use this technique only on IC
2. Draw away the melted solder with an anti-static suction-type connections).
solder removal device (or with solder braid) before removing the
IC. 1. Carefully remove the damaged copper pattern with a sharp
Replacement knife. (Remove only as much copper as absolutely necessary).
1. Carefully insert the replacement IC in the circuit board. 2. carefully scratch away the solder resist and acrylic coating (if
2. Carefully bend each IC lead against the circuit foil pad and used) from the end of the remaining copper pattern.
solder it. 3. Bend a small "U" in one end of a small gauge jumper wire and
3. Clean the soldered areas with a small wire-bristle brush. carefully crimp it around the IC pin. Solder the IC connection.
(It is not necessary to reapply acrylic coating to the areas). 4. Route the jumper wire along the path of the out-away copper
pattern and let it overlap the previously scraped end of the good
"Small-Signal" Discrete Transistor copper pattern. Solder the overlapped area and clip off any
Removal/Replacement excess jumper wire.
1. Remove the defective transistor by clipping its leads as close as
possible to the component body. At Other Connections
2. Bend into a "U" shape the end of each of three leads remaining Use the following technique to repair the defective copper pattern
on the circuit board. at connections other than IC Pins. This technique involves the
3. Bend into a "U" shape the replacement transistor leads. installation of a jumper wire on the component side of the circuit
4. Connect the replacement transistor leads to the corresponding board.
leads extending from the circuit board and crimp the "U" with
long nose pliers to insure metal to metal contact then solder 1. Remove the defective copper pattern with a sharp knife.
each connection. Remove at least 1/4 inch of copper, to ensure that a hazardous
condition will not exist if the jumper wire opens.
Power Output, Transistor Device 2. Trace along the copper pattern from both sides of the pattern
Removal/Replacement break and locate the nearest component that is directly
1. Heat and remove all solder from around the transistor leads. connected to the affected copper pattern.
2. Remove the heat sink mounting screw (if so equipped). 3. Connect insulated 20-gauge jumper wire from the lead of the
3. Carefully remove the transistor from the heat sink of the circuit nearest component on one side of the pattern break to the lead
board. of the nearest component on the other side.
4. Insert new transistor in the circuit board. Carefully crimp and solder the connections.
5. Solder each transistor lead, and clip off excess lead. CAUTION: Be sure the insulated jumper wire is dressed so the
6. Replace heat sink. it does not touch components or sharp edges.
Diode Removal/Replacement
1. Remove defective diode by clipping its leads as close as
possible to diode body.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and if
necessary, apply additional solder.
Fuse and Conventional Resistor
Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.
3. Solder the connections.
CAUTION: Maintain original spacing between the replaced
component and adjacent components and the circuit board to
prevent excessive component temperatures.
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application range 3. Test method

This specification is applied to the LCD TV used LJ91T 1) Performance: LGE TV test method followed
chassis. 2) Demanded other specification
- Safety: CE, IEC specification
2. Requirement for Test - EMC: CE, IEC specification
Each part is tested as below without special appointment.
1) Temperature : 25±5ºC (77±9ºF), CST : 40±5ºC

2) Relative Humidity : 65±10%
3) Power Voltage : Standard input voltage(100~240V@50/60Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 5 minutes prior to
the adjustment.
4. Electrical specification
4.1 General Specification
No Item Specification Remark
1. Receiving System 1) SBTVD / NTSC / PAL-M / PAL-N
2. Available Channel 1) VHF : 02~13
2) UHF : 14~69
3) DTV : 02-69
4) CATV : 01~135
3. Input Voltage 1) AC 100 ~ 240V 50/60Hz Mark : 110V, 60Hz
4. Market Central and South AMERICA
5. Screen Size 32 inch Wide(1920x1080) 32SL80YD-SA
42 inch Wide(1920x1080) 42SL80YD-SA
6. Aspect Ratio 16:9
7. Tuning System FS
8. Module LC320WUD-SBA1(Vitaz 4) 32LH70YD-SH
LC420WUD-SBT1(Vitaz 4) 42LH70YD-SE
LC470WUD-SAT1(Vitaz 4) 47LH70YD-SE
9. Operating Environment 1) Temp : 0 ~ 40 deg
2) Humidity : ~ 80 %
10. Storage Environment 1) Temp : -20 ~ 60 deg
2) Humidity : ~ 85 %
5. Chromiance & Luminance spec.
No Item Min Typ Max Unit Remark
1. Max Luminance Module 480(TBD) 540(TBD) cd/m2 32SL80YD-SA
(Center 1-point / Full White 480 600 cd/m2 42SL80YD-SA
Pattern)
480 600 cd/m2 47SL80YD-SA
470(TBD) 590(TBD) cd/m2 55SL80YD-SA
Set 400 500 cd/m2 32SL80YD-SA
400 450 cd/m2 42SL80YD-SA
400 500 cd/m2 47SL80YD-SA
400 500 cd/m2 55SL80YD-SA
2. Luminance uniformity 77 % Full white
3. Color RED X Typ. 0.638 Typ. 32SL80YD-SA
4. coordinate Y -0.03 0.334 +0.03
5. GREEN X 0.291
6. Y 0.607
7. BLUE X 0.145
8. Y 0.062
9. WHITE X 0.279
10. Y 0.292
RED X Typ. 0.638 Typ. 42SL80YD-SA
Y -0.03 0.334 +0.03
GREEN X 0.290
Y 0.606
BLUE X 0.144
Y 0.064
WHITE X 0.279
Y 0.292
Y -0.03 0.334 +0.03
GREEN X 0.290
Y 0.608
BLUE X 0.145
Y 0.064
WHITE X 0.279
Y 0.292
Y -0.03 0.333 +0.03
GREEN X 0.287
Y 0.605
BLUE X 0.145
Y 0.064
WHITE X 0.279
Y 0.292
11. Color coordinate uniformity N/A
12. Contrast ratio 800:1 1200:1 32SL80YD-SA
40000:1 50000:1
(DCR) (DCR)
1000:1 1200:1 42SL80YD-SA
40000:1 50000:1
(DCR) (DCR)
800:1 1200:1 47SL80YD-SA
40000:1 50000:1
(DCR) (DCR)
900:1 1300:1 55SL80YD-SA
40000:1 50000:1
(DCR) (DCR)
13. Color Cool Typ. 0.269 Typ. <Test Condition>
Temperature -0.015 0.273 +0.015 85% Full white pattern
Standard Typ. 0.285 Typ. ** The W/B Tolerance is
-0.015 0.293 +0.015 –0.015 for Adjustment
Warm Typ. 0.313 Typ. Dynamic contrast : off
-0.015 0.329 +0.015 Dynamic color : off
OPC : off
14. Color Distortion, DG 10.0 %
15. Color Distortion, DP 10.0 deg
16. Color S/N, AM/FM 43.0 dB
17. Color Killer Sensitivity -80 dBm
6. Component Input (Y, CB/PB, CR/PR)

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed
1. 720*480 15.73 60 13.5135 SDTV ,DVD 480I
2. 720*480 15.73 59.94 13.5 SDTV ,DVD 480I
3. 720*480 31.47 60 27.027 SDTV 480P
4. 720*480 31.47 59.94 27.0 SDTV 480P
5. 1280*720 45.00 60.00 74.25 HDTV 720P
6. 1280*720 44.96 59.94 74.176 HDTV 720P
7. 1920*1080 33.75 60.00 74.25 HDTV 1080I
8. 1920*1080 33.72 59.94 74.176 HDTV 1080I
9. 1920*1080 67.500 60 148.50 HDTV 1080P
10. 1920*1080 67.432 59.939 148.352 HDTV 1080P
11. 1920*1080 27.000 24.000 74.25 HDTV 1080P
12. 1920*1080 26.97 23.94 74.176 HDTV 1080P
13. 1920*1080 33.75 30.000 74.25 HDTV 1080P
14. 1920*1080 33.71 29.97 74.176 HDTV 1080P
15. 1920*1080 56.25 50.000 148.5 HDTV 1080P
16. 1920*1080 28.125 25.000 74.25 HDTV 1080P
7. RGB Input (PC)
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed
PC DDC
1. 640*350 31.468 70.09 25.17 EGA X
2. 720*400 31.469 70.08 28.32 DOS O
3. 640*480 31.469 59.94 25.17 VESA(VGA) O
4. 800*600 35.156 56.25 36.00 VESA(SVGA) O
5. 800*600 37.879 60.31 40.00 VESA(SVGA) O
6. 1024*768 48.363 60.00 65.00 VESA(XGA) O
7. 1280*768 47.776 59.870 79.5 CVT(WXGA) O
8. 1360*768 47.712 60.015 85.50 VESA (WXGA) O
9. 1280*1024 63.981 60.020 108.00 VESA O
10. 1600*1200 75.00 60.00 162 VESA (UXGA) O
11 1920*1080 67.5 60 148.5 HDTV 1080P O
** RGB PC Monitor Range Limits

- Min Vertical Freq - 56 Hz
- Max Vertical Freq - 62 Hz
- Min Horiz. Freq - 30 kHz
- Max Horiz. Freq - 80 kHz
- Pixel Clock - 170 MHz
8. HDMI Input (PC/DTV)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed
PC DDC
1 640*350 31.468 70.09 25.17 EGA X
2 720*400 31.469 70.08 28.32 DOS O
3 640*480 31.469 59.94 25.17 VESA(VGA) O
4 800*600 35.156 56.25 36.00 VESA(SVGA) O
5 800*600 37.879 60.31 40.00 VESA(SVGA) O
6 1024*768 48.363 60.00 65.00 VESA(XGA) O
7 1280*768 47.776 59.870 79.5 CVT(WXGA) O
8 1360*768 47.712 60.015 85.50 VESA (WXGA) O
9 1280*1024 63.981 60.020 108.00 VESA (SXGA) O
10 1600*1200 75.00 60.00 162 VESA (UXGA) O
11 1920*1080 66.587 59.934 138.5 HDTV 1080P O
DTV
1 720*480 31.47 60 27.027 SDTV 480P
2 720*480 31.47 59.94 27.00 SDTV 480P
3 1280*720 45.00 60.00 74.25 HDTV 720P
4 1280*720 44.96 59.94 74.176 HDTV 720P
5 1920*1080 33.75 60.00 74.25 HDTV 1080I
6 1920*1080 33.72 59.94 74.176 HDTV 1080I
7 1920*1080 67.500 60 148.50 HDTV 1080P
8 1920*1080 67.432 59.939 148.352 HDTV 1080P
9 1920*1080 27.000 24.000 74.25 HDTV 1080P
10 1920*1080 26.97 23.94 74.176 HDTV 1080P
11 1920*1080 33.75 30.000 74.25 HDTV 1080P
12 1920*1080 33.71 29.97 74.176 HDTV 1080P
17. 1920*1080 56.25 50.000 148.5 HDTV 1080P
18. 1920*1080 28.125 25.000 74.25 HDTV 1080P
** HDMI Monitor Range Limits

- Min Vertical Freq - 56 Hz
- Max Vertical Freq - 62 Hz
- Min Horiz. Freq - 30 kHz
- Max Horiz. Freq - 80 kHz
- Pixel Clock - 170 MHz
9. Consignment Setting (OUTGOING CONDITION)
No Item Condition
1. Input Mode TV02CH
2. Volume Level 10
3. Mute Off
4. Aspect Ratio 16:9
5. System Color PAL-M
6 Booster On
7. Picture Picture Mode Vivid
Backlight 100
Contrast 100
Brightness 50
Sharpness 70
Color 70
Tint 0
Color Temperature Cool
Picture Reset
8. Audio Sound Mode Standard
Auto Volume Off
Clear Voice Off
SRS TruSurround XT Off
Balance 0
TV Speaker On
9. Time Clock Auto
Off Timer / On Timer Off
Sleep Timer / Auto Sleep
10. Option Language (Menu/Audio) Portugues
SimpLink On
Key Lock Off
Caption Off
Set ID 1
11. Channel Memory RF : 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
14, 30, 51, 63
CATV : 15, 16, 17
Copyright LG Electronics. Inc. All right reserved. - 10 - LGE Internal Use Only
10. Mechanical Specification
32SL80YD-SA
No. Item Con tent Unit Remark

1. Product Width (W) Length (D) Height (H) mm
Dim ension W/O Packing 764.8 224.8 550.2 mm With Stand
764.8 49.8 490.4 mm W/O Stand
With Packing 910 137 488 mm With Stand
mm W/O Stand
2. Product W/O Packing 12.9 Kg With Stand
Weight 11.2 Kg W/O Stand
With Packing 15 Kg With Stand
Kg W/O Stand
42SL80YD-SA

Dim ension W/O Packing 1001.2 261 689.7 mm With Stand
1001.2 45 623.2 mm W/O Stand
mm W/O Stand
2. Product W/O Packing 21 Kg With Stand
With Packing 22.5 Kg With Stand
Kg W/O Stand
47SL80YD-SA

Dim ension W/O Packing 1109.6 320.2 751.7 mm With Stand
1109.6 45.5 685.3 mm W/O Stand
With Packing 1195.0 253.0 860.0 mm With Stand
mm W/O Stand
2. Product W/O Packing TBD Kg With Stand
With Packing TBD Kg With Stand
Kg W/O Stand
55SL80YD-SA

Dim ension W/O Packing 1279 320.2 854.3 mm With Stand
1279 45.5 780.5 mm W/O Stand
mm W/O Stand
2. Product W/O Packing 35.2 Kg With Stand
With Packing 39 Kg With Stand
Kg W/O Stand
ADJUSTMENT INSTRUCTION
1. Application Range 4. PCB Assembly Adjustment
This specification sheet is applied all of the LJ91T LCD TV 4.1. CPLD DOWNLOAD : JTAG MODE
models, which produced in manufacture department or similar
LG TV factory.
2. Notice
1) Because this is not a hot chassis, it is not necessary to use

an isolation transformer. However, the use of isolation
transformer will help protect test instrument.
2) Adjustment must be done in the correct order. But it is
flexible when its factory local problem occurs. .
3) The adjustment must be performed in the circumstance of
25 ±5°C of temperature and 65±10% of relative humidity if
there is no specific designation.
4) The input voltage of the receiver must keep 100~220V, 4.2. << PRINT PORT >> PIN MAP
50/60Hz.
5) Before adjustment, execute Heat-Run for 5 minutes. Pin JTAG Mode Signal Name
2 TCK
• After Receive 100% Full white pattern (06CH) then process
Heat-run 3 TMS
(or “8. Test pattern” condition of Ez-Adjust status) 8 TDI
• How to make set white pattern
1) Press Power ON button of Service Remocon 11 TDO
2) Press ADJ button of Service remocon. Select “8. Test 13 -
pattern” and, after select “White” using navigation button,
15 VCC
and then you can see 100% Full White pattern.
18 TO 25 GND
* In this status you can maintain Heat-Run useless any
pattern generator
* Notice: if you maintain one picture over 20 minutes

(Especially sharp distinction black with white pattern –
13Ch, or Cross hatch pattern – 09Ch) then it can appear
image stick near black level.
3. Adjustment Items
3.1 PCB Assembly adjustment

• CPLD DOWNLOAD
• Adjust 480i Comp1
• Adjust 1080p Comp1/RGB
- If it is necessary, it can adjustment at Manufacture Line
- You can see set adjustment status at “1. ADJUST
CHECK” of the “In-start menu”
3.2 Set Assembly Adjustment

• EDID (The Extended Display Identification Data ) / DDC
(Display Data Channel) download
• Color Temperature (White Balance) Adjustment
• Make sure RS-232C control
• Selection Factory output option
4.3. << 10P WAFER >> PIN MAP
4.4. Using RS-232C
Adjust 3 items at 3.1 PCB assembly adjustments “4.1.3
sequence” one after the order.
O Adjustment protocol
Order Command Set response

1. Inter the ad 00 00 d 00 OK00x
Adjustment mode
2. Change the kb 00 40 b 00 OK40x (Adjust 480i Comp1/1080p Comp1)
Source kb 00 60 b 00 OK60x (Adjust 1080p RGB)
3.Start Adjustment ad 00 10
4.Return the OKx ( Success condition )
Response NGx ( Failed condition )
5.Read (main) (main : component1 480i, RGB 1080p)
Adjustment data ad 00 20 000000000000000000000000007c007b006dx
(main) (main : component1 1080p)
ad 00 30 000000070000000000000000007c00830077x
6.Confirm ad 00 99 NG 03 00x (Failed condition)
Adjustment NG 03 01x (Failed condition)
NG 03 02x (Failed condition)
OK 03 03x (Success condition)
7. End of Adjustment ad 00 90 d 00 OK90x
See ADC Adjustment RS232C Protocol_Ver1.0
O Adjustment protocol
- Pattern Generator : (MSPG-925FA)
- Adjust 480i Comp1 (MSPG-925FA : model :209 , pattern
: 65)
- Adjust 1080p Comp1/RGB(MSPG-925FA:model : 225 ,
pattern : 65)
- Adjust RGB (MSPG-925FA:model :225 , Pattern :65) –
RGB-PC Mode
* If you want more information then see the below Adjustment

method (Factory Adjustment)
O Adjustment sequence
- ad 00 00 : Enter the ADC Adjustment mode.
- xb 00 40: Change the mode to Component1 (No actions)
- ad 00 10: Adjust 480i Comp
- ad 00 10: Adjust 1080p Comp
- xb 00 60: Change to RGB-PC mode(No action)
- ad 00 10: Adjust 1080p RGB
- ad 00 90: End of the adjustment
5. Factory Adjustment
5.1 Manual Adjust Component 480i/1080p

RGB 1080p
O Summary : Adjustment component 480i/1080i and RGB

1080p is Gain and Black levelsetting at Analog
to Digital converter, and compensate the RGB
deviation
O Using instrument
- Adjustment remocon, 801GF(802B, 802F, 802R) or
MSPG925FA pattern generator (It can output 480i/1080i
horizontal 100% color bar pattern signal, and its output
level must setting 0.7V±0.1V p-p correctly)
5.2 EDID (The Extended Display

Identification Data) / DDC (Display Data
Channel) Download.
<Pic.4 Adjustment pattern : 480i / 1080p 60Hz Pattern > O Summary

• It is established in VESA, for communication between
* You must make it sure its resolution and pattern cause every PC and Monitor without order from user for building user
instrument can have different setting condition. It helps to make easily use realize “Plug and
Play” function.
O Adjustment method 480i Comp1, Adjust 1080p • For EDID data write, we use DDC2B protocol.
Comp1/RGB (Factory adjustment)
• ADC 480i Component1 adjustment O Auto Download
- Check connection of Component1 • After enter Service Mode by pushing “ADJ” key,
- MSPG-925FA Ë Model: 209, Pattern 65 • Enter EDID D/L mode.
• Set Component 480i mode and 100% Horizontal Color • Enter “START” by pushing “OK” key.
Bar Pattern(HozTV31Bar), then set TV set to
Component1 mode and its screen to “NORMAL” Caution: - Never connect HDMI & D-sub Cable when the user
• ADC 1080p Component1 / RGB adjustment downloading .
- Check connection both of Component1 and RGB - Use the proper cables below for EDID Writing.
- MSPG-925FA Model: 225, Pattern 65
• Set Component 1080p mode and 100% Horizontal Color
Bar Pattern(HozTV31Bar), then set TV set to
Component1 mode and its screen to “NORMAL”
• After get each the signal, wait more a second and enter
the “IN-START” with press IN-START key of Service
remocon. After then select “7. External ADC” with
navigator button and press “Enter”.
• After Then Press key of Service remocon “Right
Arrow(VOL+)”
• You can see “ADC Component1 Success”
• Component1 1080p, RGB 1080p Adjust is same
method.
• Component 1080p Adjustment in Component1 input
mode
• RGB 1080p adjustment in RGB input mode
• If you success RGB 1080p Adjust. You can see “ADC
RGB-DTV Success”
Edid data and Model option download (RS232) - HDM2 EDID table (0x3D, 0x1C)
NO Item CMD 1 CMD 2 Data 0
Enter Download When transfer the ’Mode In’ ,
download MODE ModeIn A E 0 0 Carry the command.
Edid data and
Automaticall y download
Model option Download A E *Note1 *Note2
download (The use of a internal Data)
Adjust Mode Out A E 9 0
Adjustment To check Download
Confirmation A E 9 9 on Assembly line.
O Manual Download
• Write HDMI EDID data
- Using instruments
=> Jig. (PC Serial to D-Sub connection) for PC, DDC
adjustment.
=> S/W for DDC recording (EDID data write and
read)
=> D-sub jack
=> Additional HDMI cable connection Jig.
- HDMI-3 EDID table (0x3D, 0x0C)
- Preparing and setting.
=> Set instruments and Jig. Like pic.5), then turn on
PC and Jig.
=> Operate DDC write S/W (EDID write & read)
=> It will operate in the DOS mode.
VSC
PC
B/D
Pic.3) For write EDID data, setting Jig and another instruments.
• EDID data for LJ91D Chassis (Model name = LG TV)

- HDMI-1 EDID table (0x3D, 0x2C) - Analog (RGB) EDID table (0x9B, 0x25)
See Workig Guide of you want more information about EDID

communication.
5.3 Adjustment Color Temperature O White Balance Adjustment
If you can’t adjust with inner pattern, then you can adjust
(White balance) it using HDMI pattern. You can select option at "Ez-Adjust
Menu – 7. White Balance" there items "NONE, INNER,
O Using Instruments HDMI". It is normally setting at inner basically. If you can’t
• Color Analyzer: CA-210 (CH 9) adjust using inner pattern you can select HDMI item, and
- Using LCD color temperature, Color Analyzer (CA-210) you can adjust.
must use CH 9, which Matrix compensated (White, Red,
Green, Blue compensation) with CS-2100. See the In manual Adjust case, if you press ADJ button of service
Coordination bellowed one. remocon, and enter "Ez-Adjust Menu – 7. White
• Auto-adjustment Equipment (It needs when Auto- Balance", then automatically inner pattern operates. (In
adjustment – It is availed communicate with RS-232C : case of "Inner" originally "Inner" will be selected.
Baud rate: 115200)
• Video Signal Generator MSPG-925F 720p, 216Gray • Connect all cables and equipments like Pic.5)
(Model: 217, Pattern 78) • Set Baud Rate of RS-232C to 115200. It may set
115200 orignally.
• Connect RS-232C cable to set
O Connection Diagram (Auto Adjustment)
• Connect HDMI cable to set
• Using Inner Pattern
F u l l W h i t e P at t er n C A -100+
COL OR
A NA L Y ZER
T Y PE ; C A -100+
R S-232C
• Using HDMI input

¢ RS-232C Command (Commonly apply)
wb 00 00 White Balance adjustment start.

wb 00 10 Start of adjust gain (Inner white
pattern)
wb 00 1f End of gain adjust
wb 00 20 Start of offset adjust(Inner white
pattern)
wb 00 2f End of offset adjust
wb 00 ff End of White Balance adjust(Inner
pattern disappeared)
• "wb 00 00": Start Auto-adjustment of white balance.

• "wb 00 10": Start Gain Adjustment (Inner pattern)
• "jb 00 c0" :
<Pic.5 Connection Diagram for Adjustment White balance> .
•…
• "wb 00 1f": End of Adjustment
* If it needs, offset adjustment (wb 00 20-start, wb 00
2f-end)
• "wb 00 ff": End of white balance adjustment (inner
pattern disappear)
O White Balance Adjustment (Manual adjustment)
• Test Equipment: CA-210
- Using LCD color temperature, Color Analyzer (CA-
210) must use CH 9, which Matrix compensated
(White, Red, Green, Blue compensation) with CS-
2100. See the Coordination bellowed one.
• Manual adjustment sequence is like bellowed one.
- Turn to "Ez-Adjust" mode with press ADJ button of
service remocon.
- Select "10.Test Pattern" with CH+/- button and press
enter. Then set will go on Heat-run mode. Over 30
minutes set let on Heat-run mode.
- Let CA-210 to zero calibration and must has gap more
10cm from center of LCD module when adjustment.
- Press "ADJ" button of service remocon and select
"7.White-Balance" in "Ez-Adjust" then press "▶" 5.5 Test of RS-232C control
button of navigation key. Press IN-Start button of service remocon then set the “4.Baud
(When press "▶" button then set will go to full white rate” to 15200, Then check RS-232C control and
mode)
- Adjust at three mode (Cool, Medium, Warm) 5.6 Selection of Country option.
- If "cool" mode Selection of country option is allowed only North American model
Let B-Gain to 192 and R, G, B-Cut to 64 and then (Not allowed Korean model). It is selection of Country about
control R, G gain adjustment High Light adjustment. Rating and Time Zone.
- If "Medium" and "Warm" mode • Models: All models which use LA75A Chassis (See the first
Let R-Gain to 192 and R, G, B-Cut to 64 and then page.)
control G, B gain adjustment High Light adjustment. • Press “In-Start” button of Service Remocon, then enter the
- All of the three mode “Option” Menu with “PIP CH-“ Button
Let R-Gain to 192 and R, G, B-Cut to 64 and then • Select one of these three (USA, CANADA, MEXICO)
control G, B gain adjustment High Light adjustment. defends on its market using “Vol. +/-“button.
- With volume button (+/-) you can adjust.
- After all adjustment finished, with Enter (■ key) turn * Caution : Don’t push The Instop Key ater completing the
to Ez-Adjust mode. Then with ADJ button, exit from function inspection.
adjustment mode
5.7 Check the Ginga(Data Broadcasting)
Attachment: White Balance adjustment coordination and color
temperature.
1) Turn on TV
2) Press the OK Button on the ADJ R/C
O Using CS-1000 Equipment.
- COOL : T=11000K, △uv=0.000, x=0.276 y=0.283
- MEDIUM : T=9300K, △uv=0.000, x=0.285 y=0.293
- WARM : T=6500K, △uv=0.000, x=0.313 y=0.329
5.4 EYE-Q Function check.

1) Turn on TV
2) Press EYE Key of Adj R/C 3) Check the Ginga icon
3) Cover the Eye Q II sensor on the front of the using your
hand and wait for 6 seconds
4) Confirm that R/G/B va;ie os ;pwer tjam 10 of the ‘Raw
Data (Sensor data, Back light)”. If after 6 seconds, R/G/B
value is not lower than 10, re[;ace EYE Q II sensor.
5) Remove your hand from the EYE Q II sensor and wait for
6 sencond
6) Confirm that “OK” pop up.
If change is not seen, replace EYE Q II sensor
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
400
810
521
A7
520
540
910
530
805
900
806
550
804
801
807
802
LV2
610
803
LV1
600
A10
580
121
200
A2
120
200T
200N
300
310
500
510
Copyright LG Electronics. Inc. All right reserved. -17 - LGE Internal Use Only
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP
29 D3.3V
R1101
COMPONENT1 SIDE AV R,G,B PC&DDC
10K
R1118
1K +5V_ST
COMP1_DET
ZD1101
5.1V
28 C1101
3:T21
ZD1102
D1103
5.1V
100pF ENKMC2838-T112
50V A1
FIX-TER D3.3V
C
A2
11
L1101 R1134
27 10 CM2012FR27KT R1123
15 3:T21
2.7K
R1137
SIDE_CVBS_DET
COMP1_Y_IN
ZD1133
ZD1103
9 C1130 1K 3:T19
5.1V
5.1V
50V 50V
27pF 27pF 0.1uF
ZD1134
ZD1104
C1103 16V IC1103
5.1V
5.1V
8 C1116 C1151
P1101 C1153
26 +5V M24C02-RMN6T
R1156
12507WS-08L C1142 0.1uF 4700pF
4.7K
R1153
4.7K
7 0.1uF R1159 50V
50V
L1102 10K
CM2012FR27KT R1124 R1129 E0 VCC
6 1 8 OPT
15 0
COMP1_Pb_IN 1 R1142
ZD1105
22 R1166
5.1V
25 5
50V
50V 3:T21 R1130 RGB_VSYNC E1
2 7
WC 0
ZD1106
27pF 15 3:T14 EDID_WP
5.1V
27pF 2 SIDE_CVBS_IN 3:T16
C1117
4 R1151 C1104
3:T19 E2 SCL
ZD1135
0 C1137
3 6
5.1V
DDC_SCL
D2A
D2B
D3A
D3B
VCC
47pF
Q2
Q3
JK1101 3 R1172 3:T17
ZD1136
13 [RD]MONO 50V
5.1V
L1103 75
24 CM2012FR27KT R1125 VSS
4 5
SDA
10
11
12
13
14
15 DDC_SDA
COMP1_Pr_IN 4 3:T17
ZD1107
R1157
5.1V
22 R1163
50V 50V 3:T20
74F08D
IC1102
22
ZD1108
27pF 27pF
5.1V
5
C1105 C1118
23 6
R1131
0 R1173
1
0
D1104 D1105
C1112 C1131 ADMC5M03200L OPT ADMC5M03200L
GND
Q1
D1B
D1A
Q0
D0B
D0A
R1135 5.6V
COMP1_L_IN 7 SIDE_L_IN 5.6V
R1103
470K
ZD1109
22 3:T20
ZD1137
0 3:T22 0
5.1V
1uF C1122 1uF
5.1V
R1114 R1150
25V 100pF 0 25V C1135
ZD1110
D1102
ZD1138
8 100pF
5.1V
50V
5.1V
R1127 R1143 ADUC30S03010L
22 30V
470K
9 RGB_HSYNC
3:T14 D1101
21 C1113
COMP1_R_IN BCM Reference
ADUC30S03010L
30V
R1104
0
470K
C1123 3:T21
ZD1111
1uF R1115
5.1V
25V 100pF
50V
ZD1112
L1108
5.1V
20 0
ZD1146
3:T15 DSUB_B
5.1V
ZD1147
C1143 L1108-*1
5.1V
C1132 47pF
R1136 50V BG1608B121F RGB_BEAD
SIDE_R_IN
ZD1139
19 1uF 0 3:T20 +5V
5.1V
D3.3V
25V
R1102
ZD1140
R1128
5.1V
L1109
COMPONENT2
10K
470K C1136 R1169

R1119 100pF 0 10K
ZD1148
1K 3:T15 DSUB_G
5.1V
COMP2_DET
ZD1121
C1144 L1109-*1 1K
5.1V
ZD1149
18 3:T23 47pF R1170
5.1V
C1102
BG1608B121F RGB_BEAD
ZD1122
100pF 50V DSUB_DET

5.1V
50V 3:T16
FIX-TER BCM RECOMMAND
C1152 D1106
11 L1110 100pF ADMC5M03200L
L1106
17 10 R1120
0 50V 5.6V
OPT
R1162 0
R1164 0
CM2012FR27KT
ZD1150
3:T16 DSUB_R
5.1V
15
COMP2_Y_IN
ZD1123
C1145 L1110-*1
ZD1151
5.1V
5.1V
50V 3:T23 47pF
50V
ZD1124
27pF 50V BG1608B121F RGB-BEAD

27pF
5.1V
GREEN_GND
DDC_CLOCK
8 C1107 C1119
DDC_DATA
BLUE_GND
SYNC_GND
16
RED_GND
DDC_GND
H_SYNC
V_SYNC
GND_2
GREEN
GND_1
7
BLUE
RED
NC
L1104
CM2012FR27KT R1121
6 15
COMP2_Pb_IN
ZD1125
5.1V
15 5 50V 3:T22
SHILED
50V
11
12
13
14
15
ZD1126
27pF 27pF
5.1V
C1108
4 R1152
C1120
JK1106
0
PC AUDIO
16
10
6
9
JK1102
13 [RD]MONO L1105
SPG09-DB-010
14 CM2012FR27KT R1122
15
5
COMP2_Pr_IN JK1104
ZD1127
5.1V
50V 3:T22 PEJ027-01

50V
ZD1128
27pF 27pF
5.1V
C1109 3 E_SPRING
C1121
13 6A T_TERMINAL1
C1133
C1114 7A B_TERMINAL1 R1138
ZD1141
PC_R_IN
5.1V
COMP2_L_IN
R1108
R1132
C1127 1uF
470K
3:T13
ZD1129
12 0 R_SPRING
470K
3:T23
ZD1142
4
5.1V
1uF R1116 100pF 25V

25V 50V 5.1V
ZD1130
5.1V
T_SPRING
5
RS-232C
C1134
7B B_TERMINAL2 R1139
+5V_ST
ZD1143
PC_L_IN
11
5.1V
0
R1133
C1115 1uF 3:T13
T_TERMINAL2
470K
L1107
ZD1144
6B 25V
5.1V
COMP2_R_IN BLM18PG121SN1D
ZD1131
R1109
0
5.1V
C1128 3:T23
470K
1uF R1117 SHIELD_PLATE

25V 100pF 8
ZD1132
5.1V
50V C1146
10 R1144 R1145
0.1uF
50V JK1107
IC1101 4.7K 4.7K R1146
0
MAX3232CDR RS232C_RxD 3:T12 SPG09-DB-009
C1140 R1147
D3.3V 0.47uF 0
9 25V
C1+ 1 16 VCC
RS232C_TxD 3:T12 1
AV1 R1105
10K R1111
C1138 R1167 6
0.1uF 220
1K 50V 2
V+ 2 15 GND
AV1_CVBS_DET
ZD1113
R1148
8
5.1V
C1106 3:T18 100 R1168 7

OPT 220
ZD1114
0.1uF C1- 3 14 DOUT1

5.1V
16V 3
ZD1152
C1141
ZD1154
5.1V
0.47uF
5.1V
25V 50V 50V 8
SPDIF OPTIC JACK C2+ 4 13 RIN1
R1149 50V
47pF 47pF
4
ZD1153
ZD1155
50V C1149 C1150
5.1V
5.1V
7 6 R1110
15
AV1_CVBS_IN
C2- 5 12 ROUT1
100
OPT
C1147
220pF
C1148
220pF 9
8 C1139
JK1105 0.47uF 5
3:T18
ZD1115
C1124
5.1V
47pF +5V JST1223-001 25V V- DIN1

D3.3V 6 11 10
R1171
ZD1116
7 50V
+5V_ST
5.1V
75
6 GND
1
Fiber Optic
5 DOUT2 7 10 DIN2
+5V_ST
C1110 R1126 US_Commercial
25V 1uF R1112 1K VCC
R1165
2
4 0 RIN2 ROUT2
8 9 3.3K
AV1_L_IN OPT
JK1103 R1158
5 C1125 3:T18 VINPUT
ZD1117
3.3K US_Commercial
3
SPDIF_OUT
5.1V
R1106 100pF C
4
470K G4;3:T12 R1154 R1160

ZD1118
ZD1145 C1129 0 100K

5.1V
Q1102 B
OPT 0.1uF FIX_POLE
50V 2SC3052
5.6B
R1140 C US_Commercial
100 R1155 R1161 E
C1111
4 25V 1uF
R1113
0
AV1_R_IN R1141
IR
3:T11
10K
OPT
B Q1101
2SC3052
100K
US_Commercial
3:T18 100
C1126 OPT E
ZD1119
100pF
5.1V
R1107
470K
ZD1120
5.1V
2 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM (BRAZIL VENUS) 2009. 03. 23
1 ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR LEE GI YOUNG
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. IN - OUT
1 15
* HDMI CEC
29 +3.3V_ST +1.8V_AMP +1.8V_HDMI D3.3V +3.3V_HDMI
L601 L602
Q16;AH18 68K BLM18PG121SN1D BLM18PG121SN1D
MMBD301LT1G
JACK_GND 5V_HDMI_4
28 20
R666
C623 C629
D601
R641 Q601 0.1uF 0.1uF
0 AH19
9.1K
R667
SSM6N15FU
19 HPD4
HPD
27 18
17
+5V_POWER
R642 0 R14;AG19
CEC_REMOTE
R658
0 DRAIN1
6 1
SOURCE1 12:F6
HDMI_CEC
DDC/CEC_GND
16 DDC_SDA_4 H8;H17;R26;AL11 GATE2 GATE1
SDA R13;AG19 5 2
AVRL161A1R1NT
15 DDC_SCL_4
R639 0
VR607
26 14
SCL
NC R643 0
H8;H17;W27;AL11
SOURCE2
4 3
DRAIN2
CEC_REMOTE
13 C612
CEC AG19 0.1uF
12 CK-_HDMI4
CLK-
25 11
CLK_SHIELD AG19
CK+_HDMI4
GND R664 OPT
GND
10 AF19
CLK+ 0
9 D0-_HDMI4
DATA0-
24 8
7
DATA0_SHIELD AF19
D0+_HDMI4
AF19
DATA0+
6 D1-_HDMI4
DATA1-
5
AF19
23 4
DATA1_SHIELD
DATA1+
D1+_HDMI4
AE19
D2-_HDMI4 +3.3V_HDMI
3
DATA2-
2 AE19
DATA2_SHIELD
22 1
DATA2+
D2+_HDMI4 R665
0
KJA-ET-0-0032
JK503
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
21
C609
C610
C611
C613
C614
C615
GND SIDE_HDMI_PORT4
C624
20
D2-_HDMI4
D1-_HDMI4
D2+_HDMI4
D1+_HDMI4
CK+_HDMI4
D0-_HDMI4
CK-_HDMI4
DDC_SCL_4
DDC_SDA_4
D0+_HDMI4
HDMI0_RXC-_BCM 11:W17
HDMI0_RXC+_BCM 11:W17
HDMI0_RX0-_BCM 11:W17
HDMI0_RX0+_BCM 11:W17
+5.0V
HDMI_SCL
HDMI_SDA
5V_HDMI_1 5V_HDMI_2 0.1uF
HPD4
C625
P19;AJ15
20 5V_HDMI_2
0.1uF
C626
19 20
R628
0 AL11 0.1uF
19 HPD2 C627
R662
1.8K
18 R635 0.1uF
R634 R653 R656
5V_HDMI_4
47K 47K
18 17
16
R616 0 R18;AL12
DDC_SDA_2
47K 47K
R661
1.8K
R17;AL12 DDC_SDA_1 DDC_SDA_2
15 0 DDC_SCL_2 C616
R617 DDC_SCL_1 DDC_SCL_2 0.1uF
14 H8;R26;W27;AL11
17 13
R618 0
CEC_REMOTE
AL12
+1.8V_HDMI
CK-_HDMI2
12
C622 C628
C620
11 AL12 0.1uF 0.1uF
0.1uF
16 CK+_HDMI2
VDDC[1V8]_3
VDDH[3V3]_8
VDDH[3V3]_7
RXD_DDC_CLK
RXD_DDC_DAT
10
AL13 5V_HDMI_4
VDDO[1V8]
D0-_HDMI2
9
OUT_D0-
OUT_D0+
OUT_D1-
OUT_D1+
OUT_D2-
OUT_D2+
RXD_D2+
RXD_D2-
RXD_D1+
RXD_D1-
RXD_D0+
RXD_D0-
RXD_DC+
RXD_DC-
RXD_HPD
VSS_12
VSS_11
VSS_10
RXD_5V
8 AL13 5V_HDMI_2
D0+_HDMI2
15 7
AL13
D1-_HDMI2
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
6
VSS_1 1 75 VDDH[1V8]_2
5V_HDMI_1 R676 C621
5 OUT_C+ 2 74 R12K
AL13 0.1uF
D1+_HDMI2 OUT_C- 3 73 VSS_9 12K
4
14 3
AL14
D2-_HDMI2
R655
47K
R657
47K
C607
OUT_DDC_CLK
VDDO[3V3] 4
5
72
71
RXC_D2+
RXC_D2-
D2+_HDMI2
D2-_HDMI2
OUT_DDC_DAT 6 70 VDDH[3V3]_6
2 DDC_SDA_4 0.1uF
AL14 VSS_2 7 69 RXC_D1+
D2+_HDMI2 D1+_HDMI2
1 DDC_SCL_4 VDDC[1V8]_1 RXC_D1-
8
IC601 68 D1-_HDMI2
13 HPD1
RXA_HPD
RXA_5V
9
10
67
66
VSS_8
RXC_D0+
RXA_DDC_DAT 11 TDA9996HL 65 RXC_D0-
D0+_HDMI2
D0-_HDMI2
DDC_SDA_1 RXA_DDC_CLK VDDH[3V3]_5
12 64
DDC_SCL_1 RXA_C- RXC_C+
13 63 CK+_HDMI2
12 YKF45-7058V UI_HW_PORT2 EDID Pull-up CK-_HDMI1
CK+_HDMI1
RXA_C+ 14 62 RXC_C-
CK-_HDMI2
VDDH[3V3]_1 15 61 RXC_DDC_CLK
JK501 GND DDC_SCL_2
RXA_D0- 16 60 RXC_DDCC_DAT
D0-_HDMI1 DDC_SDA_2
RXA_D0+ 17 59 RXC_5V
D0+_HDMI1 VSS_3 RXC_HPD
18 58
HPD2
11 D1-_HDMI1
RXA_D1-
RXA_D1+
19
20
57
56
CEC
VSS_7 0
R677
CEC_REMOTE
D1+_HDMI1 VDDH[3V3]_2 VDDS[3V3]
21 55
RXA_D2- 22 54 CDEC_STBY Net Labels changed for HDMI2
20 L19;Z14 D2-_HDMI1 RXA_D2+ INT/HP_CTRL R678 0
5V_HDMI_1 23 53
D2+_HDMI1
10 20
VDDH[1V8]_1 24 52 XTAL_OUT OPT
0.1uF
R627
C619
NC 25 51 XTAL_IN
0 Y13 +5.0V
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
19 HPD1
R663
18 0
VSS_4
TEST
RXB_HPD
RXB_5V
RXB_DDC_DAT
RXB_DDC_CLK
RXB_C-
RXB_C+
VDDH[3V3]_3
RXB_D0-
RXB_D0+
VSS_5
RXB_D1-
RXB_D1+
VDDH[3V3]_4
RXB_D2-
RXB_D2+
VSS_6
CDEC_DDC
VDDC[1V8]_2
VDDC[3V3]
0 MODE
PD
SDA/SEL1
SCL/SEL0
C605
9 17
R605 0 M18;X13
0.1uF
16 DDC_SDA_1
M17;X12
R668
15 0 DDC_SCL_1 0
R606
+1.8V_HDMI R675
8 14
13
R607 0
H17;R26;W27;AL11
CEC_REMOTE OPT
0
Y12 C617 C618
CK-_HDMI1
12 C606 0.1uF 5.6nF
C604 C608
R670
0.1uF 0.1uF 0.1uF
11
0
Y12
7 10
CK+_HDMI1
Y12
R671
D0-_HDMI1 +3.3V_HDMI
9
8 R672
Y11
6 7
D0+_HDMI1
Y11
D1-_HDMI1
R669
0
4.7K OPT
R673
4.7K
6
OPT
5 4.7K
R674
Y11
D1+_HDMI1
5 4
3
Y10
D2-_HDMI1
OPT
5:G5;16:G14
5:G5;16:G14
2
SCL1_3.3V
SDA1_3.3V
Y10
D2+_HDMI1
1
4
3 YKF45-7058V
JK500 GND
UI_HW_PORT1 VARISTORS(VR500/501/502/503/504/505/506/507) on lines-HPD1/2/3/4 are all options
in case HDMI Switch doesn’t support ’ESD protection’
HDMI S/W For MSTAR Platform
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BCM (BRAZIL VENUS) 2009.03.23
1 ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR LEE GI YOUNG
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI
2 15
A B C D E F G H I J
IC503
D3.3V AZ1117H-1.8TRE1(EH13A) +1.8V_AMP
7
INPUT 3 1 ADJ/GND
2
C548
10uF
C549
0.1uF
OUTPUT
10V 16V GND
C551 C552
0.1uF 10uF
16V 10V
6 +24V +24V_AMP
L511
MLB-201209-0120P-N2
SPK_L+ H3
+24V_AMP
D501 R518 C544
1N4148W L504 0.01uF
100V 5.6 DA-8580 50V
T_330uF_Capacitor R511 R523
3.3 OPT EAP38319001 C540 R527
C531 0.1uF
1000pF 2S 2F 50V 4.7K
50V 3.3
C515 C520 C522

C538
0.47uF SPEAKER_L
C553 50V
0.01uF 0.1uF 0.1uF 330uF C532 1S 1F R528
50V C526 D502 1000pF
50V 50V 35V 1N4148W 50V C541 3.3
0.01uF 100V 0.1uF R524
22uH 50V C545
50V OPT R519
4.7K 0.01uF
C514 5.6 50V
5
MLB-201209-0120P-N2
D3.3V 22000pF SPK_L- H3
50V C519
22000pF
50V
L503
PGND1A_2
PGND1A_1
PVDD1A_2
PVDD1A_1
PVDD1B_2
PVDD1B_1
PGND1B_2
PGND1B_1
C521
OUT1A_2
OUT1A_1
OUT1B_2
OUT1B_1
1uF
R502 16V
Change 22uH(L504,L505) TO 15uH/6.3mm After DV1
BST1B
VDR1B
100
9:G7;9:I3;12:I4 AMP_RST
C506
56
55
54
53
52
51
50
49
48
47
46
45
44
43
1000pF
50V
BST1A 1 42 NC C523
C511 16V1uF
R504 VDR1A 2 41 VDR2A C525 SPK_R+ H3
9:G6 0 1uF 10V 22000pF
RESET 3 40 BST2A
+1.8V_AMP AUDIO_M_CLK 50V D503
R520
AD 4 39 PGND2A_2 L505 C546
1N4148W 5.6
IC501
MLB-201209-0120P-N2
+1.8V_AMP DVSS_1 PGND2A_1 DA-8580

5 38 100V 0.01uF
C508 EAP38319001 C539 C542 R525
0.1uF VSS_IO 37 OUT2A_2 OPT C533 0.47uF 50V
MLB-201209-0120P-N2
6 1000pF 2S 2F 50V 0.1uF 4.7K R529

L502
CLK_I 7 36 OUT2A_1 50V 50V 3.3 SPEAKER_R
C507 VDD_IO 8 NTP-3100L 35 PVDD2A_2
R501
C504 1000pF C534 1S 1F

L501 50V DGND_PLL 9 34 PVDD2A_1 1000pF R530
100pF D504
0
R503 AGND_PLL PVDD2B_2 50V 3.3

50V 10 33 1N4148W 22uH
100V C543 R526
3.3K LFM PVDD2B_1 R521
4 AVDD_PLL
11
12
32
31 OUT2B_2
OPT
5.6
0.1uF
50V
4.7K C547
0.01uF
50V
H3
DVDD_PLL 13 EAN60664001 30 OUT2B_1 SPK_R-
TEST0 14 29 PGND2B_2
C501 C502
10uF 0.1uF C503 C505 +24V_AMP
15
16
17
18
19
20
21
22
23
24
25
26
27
28
10V 16V 10uF 0.1uF
6.3V 16V R522
3.3
DVSS_2
DVDD
SDATA
WCK
BCK
SDA
SCL
MONITOR_0
MONITOR_1
MONITOR_2
FAULT
VDR2B
BST2B
PGND2B_1
+1.8V_AMP
C530
C527 C528 C529 C535 WAFER-ANGLE
0.1uF
0.01uF 0.1uF 330uF 0.01uF
50V
50V L507 5
50V 50V
120-ohm
C510 C518
1uF H5 SPK_L+
10uF C513 10V C524 4
10V 0.1uF L508
16V 120-ohm
22000pF T_330uF_Capacitor
50V H5 SPK_L-
3
L510
120-ohm
H4 SPK_R+
R513 2
AMP_MUTE 12:F3 L509
R505 100 100 120-ohm
11:F7 BCM_I2S_DATA_OUT C517
H4 SPK_R-
R506 100 33pF 1
3 11:F6
11:F7
BCM_I2S_WORD_CLK
BCM_I2S_BIT_CLK
R507 100
50V
OPT P501
R508 100
SDA1_3.3V
9:I4;2:AH5
R509 100
2A => 5A
9:I4;2:AH5 SCL1_3.3V
C512 C509
33pF 33pF
50V 50V
MCLK SDATA WCK BCK TP is necessory

2 Monitor0_1_2 TP is necessory
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR KIM JONG HYUN
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. AUDIO 3 15
A B C D E F G H I J
* FROM LIPS & POWER B/D -->Apply changed Pin Map
+3.3V_ST
+12V
+5V_ST
L806
MLB-201209-0120P-N2
E
L822 D3.3V
R873 R859
Q805 MLB-201209-0120P-N2 +3.3V_MEMC
R823 3.3K 330K C873
OPT
1uF +12V L829
B
1K
OPT
C820 R817 R820 1/10W MLB-201209-0120P-N2
15pF R829 25V
33K 33K 0
50V
P801 RT1P141C-T112
C IC809
SC2621ASTRT D803 A3.3V
R875
FM20020-24 R828
7 Q807
2SC3875S(ALY)
B
RL_ON
1N4148W
100V
0
10K 12:I5;14:E5
OPT
BST
1 14
DH We’ll change SI4804 to KEC’s Product
E OPT
L830
N.C POWER_ON OCS PN L828 MLB-201209-0120P-N2
1 2 2 13
GND GND +5V_ST
R876
3 4 2.2uH
16V C883
A2[GN]1K
C1814
10uF C882
C886
CB4532UK121E
C885
COMP GND_2
10uF C881
0.01uF C884
GND GND
C887
5 6 3 12
A1[RD]
220uF ==> 100uF*2 + 22uF for Depth Q812
L807 R862 R864
5.2V 7 8 5.2V SI4804BDY
FB DL C1816
5.6K 620
100uF
C819 C842 4 11 10uF
5.2V 5.2V
6.3V
6.3V
C899 S1 D1_2
9 10 C827
LD1
22uF 1 8 6.3V
0.1uF
10uF
33uF
100uF 22uF
6.3V
C878
0.1uF
100uF 16V
+12V GND 11 12 GND 16V 16V LDOG DRV G1 D1_1 R861 470pF
5 10
C
L808 2 7
C1809
MLB-201209-0120P-N2 12V 13 14 12V C880
S2
3 6
D2_2 3.3
C824 LDFB NC
C896 C828 C826 GND 15 16 GND L805 +24V 6 9 SAM2333
0.1uF
47uF 0.1uF
22uF 0.1uF 50V CB4532UK121E G2 D2_1
50V 25V 24V 24V 4 5
16V OPT 17 18 GND_1 VCC
7 8 C872 10uF
N.C 19 20 Inverter_On C812 C804 25V
0.1uF
C807
1uF C802 C856 OPT 1uF C879
470pF
A.Dim Error_Out 68uF C1806
21 22 50V 35V 50V 68uF 6800pF C1819 470pF 1K
C862
35V 1uF 25V
6 N.C 23 24 PWM_Dim +5.0V 25V
0.1uF
50V R863
R854
JP810
10K must be placed with pin#8,#10 as close as possible.

4.7K L804
25 R818
GND
R801 BG2012B080TF 3.3K +3.3V_ST
A_DIM
R815
9:G6;9:I3 100 OPT
C805 C808 R826
C
R816
6.8K
1uF 16V 10K
R824 R830
OPT
25V 0.1uF
B 10K 0
OPT
C895
* D1.8V
C
0.1uF R870
50V Q806 E 10K D1.8V 415 mA @85% efficiency
Q813 B
2SC3052 INV_ON/OFF +5.0V
2SC3875S(ALY) OPT 750 mA +1.8V_MEMC
12:I5 D3.3V
TruMotion_240Hz OPT
E R827
10K
OPT IC802
OPT L826
AZ1085S-ADJTR/E1 400 mA + 600 mA
IC805
R843
R869 BG2012B080TF
10K
0 INPUT OUTPUT
AOZ1073AIL
PWM_DIM ERROR_OUT 3 2
9:G7;9:I3;7:I5 C829 R807 C806 R802 12:F6
1
L815
1uF 0.1uF 0 C822 3.6uH
R822 0 16V C811 PGND LX_2
25V C876 ADJ/GND 330uF
5 OPC_OUT1
7:I5 OPT
0 OPT OPT
OPT 100uF
16V 0.1uF 1%
1%
C818
4V
0.1uF
L812
MLB-201209-0120P-N2
1 8
C859
R825 VIN LX_1 C1817 C855
R857 2 7 10uF 0.1uF
56 66.5 10uF
+12V 6.3V
MLB-201209-0120P-N2
12:A3;A6;C4;F7;G7;I2;14:B2 R819 AGND EN

3 6
R1
* +12V to +5.0V 56
1%
R2
L813
Vout = (1+R2/R1)*1.25 FB COMP

C840 C841 4 5
R832 R834 0.1uF 1000pF 10uF
+12V 1.8V_BCM3556 C836
R844
3.3K 150K C838 50V
11K
1/10W 1uF 12:A3;A6;B5;F7;G7;I2;14:B2 R871
25V 20K
0
+5.0V
R877
IC806
SC2621ASTRT D802 12:A3;2:Y20;2:Z10;B3;C6;H5;7:A3;14:I7;14:J1 R845
C846
1N4148W 330pF 15K
100V 50V
BST DH
1 14
L819
* +1.8V_MEMC for FRC DDR
OCS PN
2 13
4 COMP
3 12
GND_2
2.2uH R853
300
Q810 C853 C860 C863 C1808
SI4804BDY R849 C1801
FB DL 10K D3.3V
4 11
VOUT : 2.533V * +1.26V Core for FRC 600 mA
100uF
S1 D1_2
10uF 10uF 0.01uF
MLB-201209-0120P-N2
1 8 10uF
16V
C845
LDOG DRV G1 D1_1 R837 470pF 16V 16V 16V +1.8V_MEMC +1.26V_MEMC
5 10 2 7 IC807
C1802
S2 D2_2 3.3 C851 D2.5V A2.5V SC4215ISTRT
L824
LDFB NC 3 6
6 9
0.1uF
12.4K
50V
G2 D2_1 NC_2
4 5 NC_3 NC_1 GND
R855
1%
GND_1 VCC 1 8
7 8 10uF 4 5 L827
25V MLB-201209-0120P-N2
C821 C848 VIN R852
2200pF
C837 VO
1.1K
OPT EN ADJ
R874
C832 10K
0.068uF C1818 1uF 470pF 3 6 2 7
C830
1uF
39K
10V
33uF 10V
0.1uF 0
25V EN ADJ
6.3V
25V 50V
6.3V
VIN VO
R846
1K
3 6
R821 R835 2 7
6.3V
16V
6.3V
33uF
1.8K
R840
must be placed with pin#8,#10 as close as possible. NC_1 GND
C1810
10uF
10uF
NC_2 NC_3 R856
C877
C875
A2[GN]
4 5
A1[RD]
1 8 C868 C870 22K
0.1uF
10uF
10uF
C1815 10uF 0.1uF
3 C858
18K
10V 16V
C888
10uF 33uF
6.3V 10V
SC4215ISTRT
C1803
C1812
C1813
MLB-201209-0120P-N2
+5.0V
C
IC803
R841
D805
SAM2333
L811
R831 R833
6.8K 390K C835
1uF * +5.0V to 1.2V
1/8W
25V
+12V
IC804
CB3216PA501E
SC2621ASTRT D801 +5V_ST D1.2V
1N4148W A1.2V * +5v_ST to +3.3V_ST
L801
100V
BST DH
0
1 14 Q804
R878
SI4925BDY
L821
OCS PN L817 MLB-201209-0120P-N2
2 13 S1 1 8 D1_2
1.2K
2 * +12v -> PANEL_POWER

6.3V
R872
2.2uH
10uF 6.3V
COMP GND_2 G1 2 7 D1_1

R842
4V
3 12
0.01uF
2K
Q809 7:I5;7:I7
C852
SI4804BDY 0.1uF S2 3 6 D2_2

C854
FB DL +5V_ST +3.3V_ST 12V_TCON

C1807
C861
4 11
10uF
C865
S1 D1_2 OPT
330uF
1 8
470pF
G2 4 5 D2_1
C1804
C844
IC801 C817
3.3
R812
R836
LDOG DRV 1uF

4.7uF
200
5 10 G1 D1_1 AZ1117D-3.3TRE1 47K 25V 1uF

R847
2 7 C833
C898
R810 25V
22uF
C839
25V
S2 D2_2 INPUT OUTPUT 22K 25V
LDFB NC 3 6 3 2 C1811
6 9
C814 0.1uF
47K
0.1uF
16V
16V
G2 D2_1 1
25V
4 5 R813
C1800 1uF
C801 C803 ADJ/GND
C810
GND_1 VCC
7 8 22uF 10uF 0.1uF OPT C
22uF
470pF
16V 16V R806

C815 16V
1.5K
10K B Q803
C847
R848
220pF
2200pF C1805 2SC3052

C825
1uF
22K
C E
25V R805
12:I5 10K B
Q802
R814 PANEL_CTL
R811
15K
2SC3052 E
1%
1
FLASH, A1.2, +1.8_DDR_BCM3556, VTT

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR AN SO YOUNG
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. POWER 4 15
A B C D E F G H I J
D1.8V
D1.8V
0.047uF
0.047uF
0.047uF
0.047uF
C323
C324
C325
C326
0.01uF
C327
C328
2700pF
C329
C330
C331
C332
0.01uF
C333
C334
2700pF
C335
C352
C353
C354
C305
C306
C307
C308
0.01uF
C309
C310
2700pF
C311
C312
C313
C314
0.01uF
C315
C316
2700pF
C317
C349
C350
C351
470pF
470pF
470pF
470pF
100uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
100uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10uF
10uF
7
10uF
10uF
A1.2V
IC100
BCM3556
A6 0.1uF C345 DDR0_VREF0 DDR1_VREF0

DDR_BVDD0
A24 0.1uF C346
DDR_BVDD1
DDR_BVSS0
B7
B24
Qimonda Qimonda
DDR_BVSS1
F20
IC300 IC301
DDR_PLL_TEST DDR1_DQ[0-15]
DDR_PLL_LDO
B23 R312 0 R301 HYB18TC1G160C2F-1.9 HYB18TC1G160C2F-1.9
22 C300 C301 DDR0_DQ[0-15] C321 C322
B17 OPT DDR01_CKE B4 B4
DDR01_CKE E5;H5;I2
C22 R313 470pF 0.1uF 470pF 0.1uF
DDR_COMP
E16 240 DDR01_ODT E5;H5;I1 B6;H6;H2;B5 DDR01_A[0-3,7-13] VREF J2 G8 DQ0 DDR0_DQ[0] VREF DQ0 DDR1_DQ[0]
DDR01_ODT B6;E6;H2;B5 DDR01_A[0-3,7-13] J2 G8
C23 DQ1 DDR0_DQ[1] DQ1
6 DDR_EXT_CLK
DDR0_CLK
B12
C12
DDR0_CLK E5
B6;H2 DDR0_A[4-6] DDR01_A[0] A0 M8
G2
H7 DQ2
DQ3
DDR0_DQ[2]
B5;H1 DDR1_A[4-6] DDR01_A[0] A0 M8
G2
H7 DQ2
DDR1_DQ[1]
DDR1_DQ[2]
DDR0_CLKb E5 H3 DDR0_DQ[3] H3 DQ3 DDR1_DQ[3]
DDR0_CLKB DDR01_A[1] A1 M3 DDR01_A[1] A1
A13 DQ4 DDR0_DQ[4] M3 DQ4
DDR1_CLK H5 A2 H1 H1 DDR1_DQ[4]
DDR1_CLK DDR01_A[2] M7 DDR01_A[2] A2 M7
A12 DDR1_CLKb H5 H9 DQ5 DDR0_DQ[5] DQ5 DDR1_DQ[5]
DDR1_CLKB DDR01_A[3] A3 A3 H9
B15 DDR01_A[0] N2 DQ6 DDR01_A[3] N2
F1 DDR0_DQ[6] F1 DQ6 DDR1_DQ[6]
DDR01_A00 DDR0_A[4] A4 N8 DDR1_A[4] A4
E14 DDR01_A[1] DQ7 DDR0_DQ[7] N8 DQ7
DDR01_A[0-3] E6;H6;H2 DDR0_A[5] A5 F9 F9 DDR1_DQ[7]
DDR01_A01 N3 DDR1_A[5] A5 N3
A15 DDR01_A[2] C8 DQ8 DDR0_DQ[8] DQ8 DDR1_DQ[8]
DDR01_A02 DDR0_A[6] A6 DDR1_A[6] A6 C8
D15 DDR01_A[3] N7 DQ9 N7
C2 DDR0_DQ[9] C2 DQ9 DDR1_DQ[9]
DDR01_A03 DDR01_A[7] A7 P2 DDR01_A[7] A7
E13 DDR0_A[4] D6;H2 DQ10 DDR0_DQ[10] P2 DQ10
DDR0_A[4-6] A8 D7 D7 DDR1_DQ[10]
DDR0_A04 DDR01_A[8] P8 DDR01_A[8] A8 P8
E12 DDR0_A[5] D3 DQ11 DDR0_DQ[11] DQ11 DDR1_DQ[11]
DDR0_A05 DDR01_A[9] A9 A9 D3
F13 DDR0_A[6] P3 DQ12 DDR01_A[9] P3
D1 DDR0_DQ[12] D1 DQ12 DDR1_DQ[12]
DDR0_A06 DDR01_A[10] A10/AP M2 DDR01_A[10] A10/AP
C14 DDR01_A[7] DQ13 DDR0_DQ[13] M2 DQ13
A11 D9 D9 DDR1_DQ[13]
DDR01_A07 DDR01_A[11] P7 DDR01_A[11] A11 P7
F14 DDR01_A[8] B1 DQ14 DDR0_DQ[14] DQ14 DDR1_DQ[14]
DDR01_A08 DDR01_A[12] A12 A12 B1
B14 DDR01_A[9] R2 DQ15 DDR01_A[12] R2
DDR01_A[7-13] E6;H6;H2 B9 DDR0_DQ[15] B9 DQ15 DDR1_DQ[15]
DDR01_A09
D14 DDR01_A[10]
DDR01_A10
C13 DDR01_A[11] B5;H5;I1 DDR01_BA0 BA0 L2 D1.8V BA0 D1.8V
DDR01_A11 B5;E5;I1 DDR01_BA0 L2
D13 DDR01_A[12] B5;H5;I1 DDR01_BA1 BA1 L3 B5;E5;I1 BA1
DDR01_A12 VDD5 DDR01_BA1 L3 VDD5
B13 DDR01_A[13] BA2 A1 A1
B5;H5;I1 DDR01_BA2 L1 B5;E5;I1 DDR01_BA2 BA2 L1
DDR01_A13 E1 VDD4 VDD4
F15 DDR1_A[4] H6;H1 E1
DDR1_A[4-6] B6 DDR0_CLK VDD3 B6 DDR1_CLK
DDR1_A04 J9 J9 VDD3
C15 DDR1_A[5]
5 DDR1_A05
DDR1_A06
D16
F16
DDR1_A[6]
B6 DDR0_CLKb
R300
100
CK
CK
J8
K8
M9
R1
VDD2
VDD1 B6 DDR1_CLKb
R303
100
CK
CK
J8
K8
M9
R1
VDD2
VDD1
DDR01_BA0 CKE
DDR01_BA0 B6;H5;I2 DDR01_CKE K2 B6;E5;I2 DDR01_CKE CKE K2
B16 DDR01_BA1
DDR01_BA1
E15 DDR01_BA2
DDR01_BA2
A17 DDR01_CASb B6;H5;I1 DDR01_ODT ODT K9 A9 VDDQ10 B6;E5;I1 ODT VDDQ10
DDR01_CASB DDR01_ODT K9 A9
A8 DDR0_DQ[0] CS L8 C1 VDDQ9 CS VDDQ9
DDR0_DQ00 L8 C1
B11 DDR0_DQ[1] B2;H5;I1 DDR01_RASb RAS K7 C3 VDDQ8 B2;E5;I1 RAS VDDQ8
DDR0_DQ01 DDR01_RASb K7 C3
B8 DDR0_DQ[2] B5;H5;I1 DDR01_CASb CAS L7 C7 VDDQ7 CAS VDDQ7
DDR0_DQ02 B5;E5;I1 DDR01_CASb L7 C7
D11 DDR0_DQ[3] B2;H5;I1 DDR01_WEb WE K3 C9 VDDQ6
B2;E5;I1 WE VDDQ6
DDR0_DQ03 DDR01_WEb K3 C9
E11 DDR0_DQ[4] HYNIX ELPIDA VDDQ5 VDDQ5
E9 E9
DDR0_DQ04 IC300-*2 IC300-*1
C8 DDR0_DQ[5] G1 VDDQ4 VDDQ4
DDR0_DQ05 H5PS1G63EFR-20L EDE1116ACBG-1J-E LDQS LDQS G1
C11 DDR0_DQ[6] B3 DDR0_DQS0 F7 VDDQ3 B3 DDR1_DQS0 F7
DDR0_DQ[0-15] G6 G3 G3 VDDQ3
DDR0_DQ06 B3 DDR0_DQS1 UDQS B7 B3 UDQS
C9 DDR0_DQ[7] VREF J2 G8 DQ0 VREF J2 G8 DQ0 VDDQ2 DDR1_DQS1 B7 VDDQ2
G7 G7
DDR0_DQ07 G2 DQ1 G2 DQ1
D8 DDR0_DQ[8] A0 H7 DQ2
A0 H7 DQ2
G9 VDDQ1 VDDQ1
DDR0_DQ08 A1
M8
H3 DQ3
A1
M8
H3 DQ3 G9
M3 M3
E10 DDR0_DQ[9] A2 H1 DQ4
A2 H1 DQ4
B3 DDR0_DM0 LDM F3 B3 LDM
DDR0_DQ09 A3
M7
H9 DQ5
A3
M7
H9 DQ5 DDR1_DM0 F3
N2 N2
E9 DDR0_DQ[10] F1 DQ6 F1 DQ6
B3 DDR0_DM1 UDM B3 UDM
DDR0_DQ10
A4
A5
N8
F9 DQ7
A4
A5
N8
F9 DQ7 B3 DDR1_DM1 B3
N3 N3
F11 DDR0_DQ[11] A6 N7
C8 DQ8
A6 N7
C8 DQ8
DDR0_DQ11 A7 C2 DQ9
A7 C2 DQ9
A3 VSS5 VSS5
F12 DDR0_DQ[12] A8
P2
D7 DQ10
A8
P2
D7 DQ10 A3
P8 P8
DDR0_DQ12 A9 D3 DQ11
A9 D3 DQ11
B3 DDR0_DQS0b LDQS E8 E3 VSS4 B3 LDQS VSS4
E8 DDR0_DQ[13] A10/AP
P3
D1 DQ12
A10
P3
D1 DQ12 DDR1_DQS0b E8 E3
M2 M2
DDR0_DQ13 D9 DQ13 D9 DQ13
B3 DDR0_DQS1b UDQS A8 J3 VSS3 UDQS VSS3
D10 DDR0_DQ[14]
A11 P7 DQ14
A11 P7 DQ14 B3 DDR1_DQS1b A8 J3
4 A12 B1 A12 B1
R2 R2
DDR0_DQ14 B9 DQ15 B9 DQ15
N1 VSS2 VSS2
F8 DDR0_DQ[15] N1
DDR0_DQ15 BA0 L2 BA0 L2
P9 VSS1 VSS1
C18 DDR1_DQ[0] BA1 L3 BA1 L3 NC4 NC4 P9
A1 VDD_5 A1 VDD_5 R3 R3
DDR1_DQ00 NC_4/BA2 L1
E1 VDD_4
BA2 L1
E1 VDD_4
C20 DDR1_DQ[1] VDD_3 VDD_3 NC5 R7 NC5
DDR1_DQ01 CK
J9
VDD_2 CK
J9
VDD_2
R7
J8 M9 J8 M9
A18 DDR1_DQ[2] CK K8 R1 VDD_1 CK K8 R1 VDD_1
DDR1_DQ02
B21
CKE K2 CKE K2 HYNIX
DDR1_DQ[3] B2 VSSQ10 ELPIDA VSSQ10
DDR1_DQ03 NC1 IC301-*2 NC1 B2
C21 DDR1_DQ[4] ODT VDDQ_10 ODT VDDQ_10 A2 VSSQ9 IC301-*1 A2
K9 A9 K9 A9
B8 H5PS1G63EFR-20L B8 VSSQ9
DDR1_DQ04 CS L8 C1 VDDQ_9 CS L8 C1 VDDQ_9 NC2 E2 EDE1116ACBG-1J-E NC2
B18 DDR1_DQ[5] RAS K7 C3 VDDQ_8 RAS K7 C3 VDDQ_8 VSSQ8 E2 VSSQ8
NC3 A7 A7
DDR1_DQ05 CAS L7 C7 VDDQ_7 CAS L7 C7 VDDQ_7
R8 VREF DQ0 NC3 R8
B20 DDR1_DQ[6] DDR1_DQ[0-15] J6
WE K3 C9 VDDQ_6 WE K3 C9 VDDQ_6
D2 VSSQ7 J2 G8 VREF J2 G8 DQ0
VSSQ7
DDR1_DQ06 E9 VDDQ_5 E9 VDDQ_5 G2 DQ1
G2 DQ1 D2
DQ2
D18 DDR1_DQ[7] LDQS G1 VDDQ_4
LDQS G1 VDDQ_4
D8 VSSQ6 A0 M8
H7
A0 H7 DQ2
VSSQ6
DDR1_DQ07 UDQS
F7
G3 VDDQ_3
UDQS
F7
G3 VDDQ_3 A1 M3
H3 DQ3
A1
M8
H3 DQ3 D8
B7 B7 DQ4 M3
E18 DDR1_DQ[8] G7 VDDQ_2 G7 VDDQ_2
VSSDL E7 VSSQ5 A2 M7
H1
A2 H1 DQ4
VSSQ5
DDR1_DQ08 G9 VDDQ_1 G9 VDDQ_1 J7 A3 N2
H9 DQ5
A3
M7
H9 DQ5 VSSDL J7 E7
DQ6 N2
D21 DDR1_DQ[9] LDM F3 LDM F3
F2 VSSQ4 A4 N8
F1
A4 F1 DQ6
VSSQ4
DDR1_DQ09 UDM B3 UDM B3 A5 N3
F9 DQ7
A5
N8
F9 DQ7 F2
DQ8 N3
F18 DDR1_DQ[10] VSS_5 VSS_5 F8 VSSQ3 A6 N7
C8
A6 C8 DQ8
VSSQ3
DDR1_DQ10 LDQS
A3
VSS_4 LDQS
A3
VSS_4 A7 P2
C2 DQ9
A7
N7
C2 DQ9 F8
E8 E3 E8 E3 DQ10 P2
E20 DDR1_DQ[11] UDQS VSS_3 UDQS VSS_3 H2 VSSQ2 A8 P8
D7
A8 D7 DQ10
VSSQ2
DDR1_DQ11 A8 J3
VSS_2
A8 J3
VSS_2 A9 P3
D3 DQ11
A9
P8
D3 DQ11 H2
N1 N1 DQ12 P3
A22 DDR1_DQ[12] VSS_1 VSS_1 VDDL J1 H8 VSSQ1 A10/AP M2
D1
A10 D1 DQ12
VDDL VSSQ1
DDR1_DQ12 NC_5/A14 R3
P9 NC_5 R3
P9
A11 P7
D9 DQ13
A11
M2
D9 DQ13 J1 H8
DQ14 P7
F17 DDR1_DQ[13] NC_6/A15 R7 NC_6 R7 A12 R2
B1
DQ15 A12 R2
B1 DQ14
DDR1_DQ13 B9 B9 DQ15
B22 DDR1_DQ[14] NC_1 A2
B2 VSSQ_10
NC_1 A2
B2 VSSQ_10
BA0
DDR1_DQ14 NC_2 E2
B8 VSSQ_9
NC_2 E2
B8 VSSQ_9
BA1
L2 BA0 L2
E17 DDR1_DQ[15] NC_3/A13 R8
A7 VSSQ_8
NC_3 R8
A7 VSSQ_8
NC_4/BA2
L3
A1 VDD_5 BA1 L3
A1 VDD_5
DDR1_DQ15 D2 VSSQ_7 D2 VSSQ_7 L1
E1 VDD_4 BA2 L1
E1 VDD_4
A10 DDR0_DM0 E4 D8 VSSQ_6 D8 VSSQ_6
J9 VDD_3
J9 VDD_3
DDR0_DM0 VSSDL J7 E7 VSSQ_5 VSSDL J7 E7 VSSQ_5 CK J8 M9 VDD_2 CK J8 M9 VDD_2
C10 DDR0_DM1 E4 F2 VSSQ_4 F2 VSSQ_4 CK K8 R1 VDD_1 CK K8 R1 VDD_1
DDR0_DM1 F8 VSSQ_3 F8 VSSQ_3 CKE K2 CKE K2
A20 VSSQ_2 VSSQ_2
3 DDR1_DM0
DDR1_DM1
F19
B10
DDR1_DM0
DDR1_DM1
H4
H4
VDDL J1
H2
H8 VSSQ_1 VDDL J1
H2
H8 VSSQ_1
ODT
CS
RAS
K9
L8
K7
A9
C1
C3
VDDQ_10
VDDQ_9
VDDQ_8
ODT
CS
RAS
K9
L8
K7
A9
C1
C3
VDDQ_10
VDDQ_9
VDDQ_8
DDR0_DQS0 E4 CAS VDDQ_7
DDR0_DQS0 WE
L7 C7
VDDQ_6
CAS L7 C7 VDDQ_7
B9 DDR0_DQS0b E4
K3 C9
VDDQ_5
WE K3 C9 VDDQ_6
DDR0_DQS0B E9
VDDQ_4
E9 VDDQ_5
F10 DDR0_DQS1 E4 LDQS F7
G1
VDDQ_3 LDQS F7
G1 VDDQ_4
DDR0_DQS1 UDQS B7
G3
VDDQ_2 UDQS B7
G3 VDDQ_3
F9 DDR0_DQS1b E4
G7
VDDQ_1
G7 VDDQ_2
DDR0_DQS1B LDM
G9 G9 VDDQ_1
B19 DDR1_DQS0 H4 UDM
F3 LDM F3
DDR1_DQS0 B3 UDM B3
C19 DDR1_DQS0b VSS_5
DDR1_DQS0B H4 * DDR_VTT LDQS E8
A3
E3 VSS_4 LDQS E8
A3
E3
VSS_5
VSS_4
E19 DDR1_DQS1 H4 UDQS A8 J3 VSS_3 UDQS A8 J3 VSS_3
DDR1_DQS1 N1 VSS_2
N1 VSS_2
D19 DDR1_DQS1b H4 NC_5/A14 P9 VSS_1
P9 VSS_1
DDR1_DQS1B NC_6/A15
R3 NC_5 R3
C16 DDR01_RASb DDR0_VREF0 R7 NC_6 R7
DDR01_RASB
A7 E5;H5;I1 DDR1_VREF0 DDR_VTT D3.3V NC_1 A2
B2 VSSQ_10
VSSQ_9 NC_1 A2
B2 VSSQ_10
DDR_VREF0 NC_2 E2
B8
VSSQ_8 NC_2 E2
B8 VSSQ_9
A23 NC_3/A13 R8
A7
VSSQ_7 NC_3 R8
A7 VSSQ_8
DDR_VREF1 D2
VSSQ_6
D2 VSSQ_7
C17 D1.8V DDR01_WEb
D8
VSSQ_5
D8 VSSQ_6
DDR01_WEB VSSDL J7 E7
VSSQ_4
VSSDL J7 E7 VSSQ_5
DDR_VTT
C7 F2
VSSQ_3
F2 VSSQ_4
DDR_VDDP1P8_1 F8 F8 VSSQ_3
C361
VSSQ_2
D22
C343
C342
C360
H2 VSSQ_2
C347
C344
C358
H2
C359
VDDL VSSQ_1
DDR_VDDP1P8_2 J1 H8 VDDL J1 H8 VSSQ_1
IC808
C355 C869 C874 C864 BD35331F-E2 D1.8V DDR01_A[0-3,7-13]
0.1uF 100uF 0.1uF
1uF 470pF 470pF 1uF 1uF 470pF 470pF 1uF 10uF
16V 10V 16V DDR1_A[4] R304
GND VTT DDR01_A[0] 75
1 8 C336
2 DDR0_A[4-6] DDR01_A[1]
DDR01_A[2]
0.01uF
EN VTT_IN
2 7 R305
C337
DDR1_VREF0 DDR0_A[4] 75 0.01uF
VTTS VCC DDR0_A[5]
3 6
DDR0_VREF0 DDR0_A[6]
C338
DDR01_A[3] R306 0.01uF
R850 0 VREF VDDQ
4 5 DDR01_A[7] 75
DDR01_A[8]
C339
R851 0 C871 DDR01_A[9] 0.01uF
C867 C897
1uF DDR01_A[10] R307
100uF 0.1uF
6.3V
16V 16V DDR01_A[11] 75
16V
C340
DDR01_A[12] 0.01uF
C866
C831 C834 BCM recommends to remove this R

0.1uF 0.1uF 1M DDR01_A[13]
0.1uF
16V 16V OPT

R858 DDR01_CKE 75 R310 C341
B6;E5;H5
DDR1_A[5] R308 0.01uF
DDR1_A[6] 75
B5;E5;H5 DDR01_BA1 C362
DDR1_A[4-6] 0.1uF
B5;E5;H5 DDR01_BA2
B2;E5;H5 DDR01_RASb R309
1 B5;E5;H5
B5;E5;H5
DDR01_BA0
DDR01_CASb
75
B2;E5;H5 DDR01_WEb
B6;E5;H5 DDR01_ODT 75 R311

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR HONG YEON HYUK
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. DDR Memory 6 15
A B C D E F G H I J
LVDS_TX_0_DATA4_P
LVDS_TX_0_DATA4_N
LVDS_TX_0_DATA3_P
LVDS_TX_0_DATA3_N
LVDS_TX_0_DATA2_P
LVDS_TX_0_DATA2_N
LVDS_TX_0_DATA1_P
LVDS_TX_0_DATA1_N
LVDS_TX_0_DATA0_P
LVDS_TX_0_DATA0_N
LVDS_TX_1_DATA4_P
LVDS_TX_1_DATA4_N
LVDS_TX_1_DATA3_P
LVDS_TX_1_DATA3_N
LVDS_TX_1_DATA2_P
LVDS_TX_1_DATA2_N
LVDS_TX_1_DATA1_P
LVDS_TX_1_DATA1_N
LVDS_TX_1_DATA0_P
LVDS_TX_1_DATA0_N
R929
LVDS_TX_0_CLK_P
LVDS_TX_0_CLK_N
LVDS_TX_1_CLK_P
LVDS_TX_1_CLK_N
* XTAL 1M
X901
M_XTALO
M_XTALI
M_XTALO M_XTALI
C946 12MHz C947
22pF 22pF
R917 R923
100 100
+3.3V_MEMC 12V_TCON
7 R918 R924
CB3216PA501E
+3.3V_MEMC
BLM18PG121SN1D
BLM18PG121SN1D
URSA_A0P
URSA_A0M
URSA_A1P
URSA_A1M
URSA_A2P
URSA_A2M
URSA_ACKP
URSA_ACKM
URSA_A3P
URSA_A3M
URSA_A4P
URSA_A4M
URSA_B0P
URSA_B0M
URSA_B1P
URSA_B1M
100 100
L909
R919 R925
L907
100 100
L908
+1.26V_MEMC R920 R926 P903
100 100 TF05-51S
+3.3V_MEMC
R921 R927
BLM18PG121SN1D
10uF
1
10uF
BLM18PG121SN1D
2
100 100
L905
0.1uF 50V
22uF/16 CST PROBLEM
1000pF 50V
0.1uF
C943
C944
3
1uF
6.3V
6.3V
C961
C960
R922 R928 4
L906
C952
5
C954
100 100 6
0.1uF
0.1uF
C914 0.1uF
0.1uF
10uF
10uF
C3019 10uF
0.1uF
7
C940
C942
8
10V
10
C915
0.1uF
0.1uF
C916
0.1uF
0.1uF
C923
C926
C937
URSA_B4M
C935
C948
C949
10uF
11
C931
C933
10uF
URSA_B4P 12
URSA_B3M
AVDD_LVDS_1
AVDD_LVDS_2
13
PI Result
R931 URSA_B3P 14
GPIO[25]
AVDD_PLL
15
GPIO_13
GPIO_14
GPIO_12
820 URSA_BCKM
GPIO_2
GPIO_1
GPIO_9
GPIO_8
LVACKP
LVACKM
GPIO_6
GPIO_4
16
RECKP
RECKN
GND_6
ROCKP
ROCKN
GND_5
GND_2
LVA0P
LVA0M
LVA1P
LVA1M
LVA2P
LVA2M
LVA3P
LVA3M
LVA4P
LVA4M
LVB0P
LVB0M
LVB1P
LVB1M
URSA_BCKP 17
RE4P
RE4N
RE3P
RE3N
RE2P
RE2N
RE1P
RE1N
RE0P
RE0N
RO4P
RO4N
RO3P
RO3N
RO2P
RO2N
RO1P
RO1N
RO0P
RO0N
XOUT
SDAM
SCLM
REXT
R909 0
XIN
A3 ISP_RXD_TR 18
R910 0 C955 URSA_B2M 19
A3 ISP_TXD_TR URSA_B2P 20
URSA_B1M
B1
A1
C1
C2
A2
B2
B3
A3
C3
C4
A4
B4
F11
H8
B5
A5
C5
C6
A6
B6
B7
A7
C7
C8
A8
B8
G11
H7
K15
K16
D4
D3
B14
A14
D5
D6
N7
E11
D13
D11
G8
F10
B9
A9
C9
C10
A10
B10
B11
A11
C11
C12
A12
B12
D9
D7
B13
A13
C13
C14
D12
21
0.1uF
R911 100 SDAS GPIO_5 URSA_B1P 22
9:I4 SDA3_3.3V E1 D8 URSA_B0M 23

R912 100 SCLS GPIO_7
SCL3_3.3V D1 D10 URSA_B0P OPT
9:I4 24
0.1uF
GPIO[8] GPIO_11 R953
F1 E10 BIT_SEL 25
GPIO[9] GPIO_10 0 26
G1 E3 URSA_A4M 27
GND_14 K8 [E1] D2 GPIO_3 URSA_A4P 28
OPT VDDC_1 E5 [D1] C15 LVB2P URSA_B2P URSA_A3M 29
C929 GPIO[10] LVB2M URSA_B2M URSA_A3P 30

LVDS_SEL R3029 E2 B15
31
0 GPIO[11] LVBCKP URSA_BCKP
F2 A15 URSA_ACKM
9:G6;I5 32
1/16W GPIO[12] F3 A16 LVBCKM URSA_BCKM URSA_ACKP 33
5% GPIO[13] G2 B16 LVB3P URSA_B3P 34

URSA_A2M 35
+3.3V_MEMC GPIO[22] M4 C16 LVB3M URSA_B3M URSA_A2P 36
GPIO[23] M5 D15 LVB4P URSA_B4P URSA_A1M 37
+3.3V_MEMC URSA_A1P
GPIO[14] G3 D16 LVB4M URSA_B4M 38
URSA_A0M
BLM18PG121SN1D
R915 1K 39
GPIO[15] E4 F9 AVDD_33_2 C956 URSA_A0P 40
GPIO[16] F4 G10 GND_4 41
L903
GPIO[17] LVC0P URSA_C0P OPT 42

G4 E15 R936 0 43
GPIO[18] LVC0M 0.1uF URSA_C0M OPC_OUT1
H4 E16
5 C912 C913
R916
OPT
1K GPIO[19]
GPIO[20]
J4 E14 LVC1P
LVC1M
URSA_C1P
URSA_C1M
PWM_DIM
+3.3V_MEMC
R937 0
OPC_EN
44
45
46
C911
10uF
K4 F14
10uF
C910
0.1uF 0.1uF GPIO[21] LVC2P URSA_C2P 12V_TCON 47

L4 F16 48
16V 16V
C930 VDDP_2 LVC2M URSA_C2M
OPC_EN
J6 F15 49
R948
R954
3.3K
OPT
GND_7 LVCCKP URSA_CCKP 50
499
H9 G15
51
PI Result 0.1uF 0.1uF GND_15 K9 LVCCKM URSA_CCKM
G16
52
G14 LVC3P URSA_C3P R941 0 OPC_EN
OPC_EN
URSA_DQ[0-31]
VDDC_2 F6 H14 LVC3M URSA_C3M

C927 R940 0
URSA_DQ[20] MDATA[20] H1 H16 LVC4P URSA_C4P LVDS_SEL
URSA_DQ[19] MDATA[19] H2 H15 LVC4M URSA_C4M
J15 LVD0P URSA_D0P
R949
3.3K
3.3K
R955
IC901
OPT
+1.8V_MEMC URSA_DQ[17] MDATA[17] H3 J16 LVD0M URSA_D0M
URSA_DQ[22] MDATA[22] J1 J14 LVD1P URSA_D1P
BLM18PG121SN1D
K14 LVD1M URSA_D1M

L904
22uF/16 CST PROBLEM URSA_DQ[27] MDATA[27] J2

URSA_DQ[28] MDATA[28] J3
URSA_DQ[25]
C918 0.1uF
MDATA[25] K1
LGE7329A L14
G9 GND_3
LVD2P
C957
URSA_D2P
0.1uF
10uF
0.1uF
C3020
URSA_DQ[30] MDATA[30] LVD2M 0.1uF URSA_D2M

10uF
10uF
C901
K2 L15
C904
C907
C909
AVDD_DDR_2 K6 L16 LVDCKP URSA_DCKP
4 URSA_DQM3
DQM[3]
DQM[2]
K3
L1
M16
F8
LVDCKM
AVDD_33_1
URSA_DCKM
URSA_DQM2 0.1uF GND_10 J8 M15 LVD3P URSA_D3P

C919
DQS[2] L2 M14 LVD3M URSA_D3M
URSA_DQS2
DQSB[2] L3 N16 LVD4P URSA_D4P
URSA_DQSB2
AVDD_DDR_4 L6 N15 LVD4M C953 URSA_D4M
* ISP Port for MEMC 0.1uF VDDP_3 L8
GND_8 H10 H6 VDDC_5
C928
DQS[3] GPIO[24] 0.1uF +3.3V_MEMC
URSA_DQS3 M1 N6
DQSB[3] M2 E12 GPIO[7]
URSA_DQSB3
AVDD_DDR_5 L7 D14 GPIO[6]
URSA_DQ[31] MDATA[31] M3 F12 GPIO[5]
URSA_DQ[24] 0.1uF MDATA[24] GPIO[4]
P902 +5.0V N1 E13 P904
GND_11 GPIO[3] TF05-41S
C920 J9 F13
R938
TJC2508-4A
R942
1K
1K
URSA_DQ[26] MDATA[26] N2 G13 GPIO[2]
1
URSA_DQ[29] MDATA[29] N3 H13 GPIO[1]
2
+3.3V_MEMC AVDD_DDR_6 L10 J13 GPIO[0] URSA_D4M 3
1 URSA_D4P
BLM18PG121SN1D
URSA_DQ[23] MDATA[23] P1 K12 PWM0 4

OPT
2.2K
R908
2.2K
R907
OPT
URSA_D3M 5
URSA_DQ[16] MDATA[16] R1 [N13] L12 PWM1
URSA_D3P 6
2 URSA_DQ[18] MDATA[18] T1 [L9] K13 CSZ 7
3 URSA_DQ[21] MDATA[21]
[N12]
SDO
M_SPI_CZ
URSA_DCKM
L902
8
T2 [N5] M12 M_SPI_DO URSA_DCKP
R939
R943
9
ISP_RXD_TR MCLK[0] SDI
OPT
OPT
1K
1K
URSA_MCLK R2 [N4] M13 M_SPI_DI 10
3 MCLKZ[0] SCK
B6 P2 L13 URSA_D2M 11
URSA_MCLKZ C925 0.1uF M_SPI_CK
GND_1 GPIO[30] URSA_D2P 12
G7 N14
URSA_D1M 13
4 AVDD_MEMPLL GPIO[29]
B6 L9 N13 URSA_D1P 14
0.1uF
C906
MVREF GPIO[28]
10uF
C908
URSA_D0M 15
ISP_TXD_TR N5 N12
ODT URSA_D0P 16
URSA_ODT N4 17
J10
L11
K10
T10
K11
R10
P10
T11
R11
J11
P11
T12
R12
P12
H11
T13
R13
P13
T14
R14
P14
T15
R15
P15
T16
R16
P16
N10
N11
M11
0.1uF C921
T3
R3
P3
T4
R4
P4
T5
R5
P5
T6
R6
P6
T7
R7
P7
T8
R8
P8
N8
F7
T9
R9
K7
P9
J7
N9
G6
18
URSA_C4M 19
URSA_C4P 20
GND_9
RASZ
CASZ
MADR[0]
MADR[2]
MADR[4]
GND_12
MADR[6]
MADR[8]
MADR[11]
WEZ
BADR[1]
BADR[0]
MADR[1]
MADR[10]
AVDD_DDR_7
MADR[5]
MADR[9]
MADR[12]
MADR[7]
MADR[3]
MCLKE
GND_16
VDDC_3
MDATA[4]
MDATA[3]
GND_13
MDATA[1]
MDATA[6]
AVDD_DDR_3
MDATA[11]
MDATA[12]
MDATA[9]
MDATA[14]
AVDD_DDR_1
DQM[1]
DQM[0]
DQS[0]
DQSB[0]
VDDP_1
DQS[1]
DQSB[1]
MDATA[15]
MDATA[8]
MDATA[10]
MDATA[13]
MDATA[7]
MDATA[0]
MDATA[2]
MDATA[5]
MCLK[1]
MCLKZ[1]
GPIO[26]
GPIO[27]
GND_17
RESET
VDDC_4
0.1uF GPIO8 PWM1 PWM0 URSA_C3M 21
URSA_C3P 22
23
C922
I2C HIGH LOW HIGH URSA_CCKM 24
URSA_CCKP 25
26
EEPROM HIGH URSA_C2M
0.1uF
HIGH LOW 27
0.1uF
C950
C941
URSA_C2P 28
URSA_C1M 29
* SPI FLASH URSA_C1P 30
SPI HIGH HIGH HIGH
0.1uF
0.1uF
C945
C951
URSA_C0M 31
URSA_C0P 32
+3.3V_MEMC
33
+3.3V_MEMC
2
C932
C934
C936
C938
R913
C939
34
10K
35
36
37
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
R930
38
0
0.1uF
4.7K
URSA_A[11]
URSA_A[10]
URSA_A[12]
39
C958
R933
URSA_A[0]
URSA_A[2]
URSA_A[4]
URSA_A[6]
URSA_A[8]
URSA_A[1]
URSA_A[5]
URSA_A[9]
URSA_A[7]
URSA_A[3]
40
41
IC902
0.1uF
C917
42
R914
C924
1uF
W25X20AVSNIG
10K
FRC_RESET
R945 56 CS
1 8
VCC
M_SPI_CZ
URSA_DQ[11]
URSA_DQ[12]
URSA_DQ[14]
URSA_DQ[15]
URSA_DQ[10]
URSA_DQ[13]
URSA_DQ[4]
URSA_DQ[3]
URSA_DQ[1]
URSA_DQ[6]
URSA_DQ[9]
URSA_DQ[8]
URSA_DQ[7]
URSA_DQ[0]
URSA_DQ[2]
URSA_DQ[5]
R946 56 DO
2 7
HOLD
M_SPI_DO
R947 10K WP CLK R951 56
3 6
M_SPI_CK H3
GND
4 5
DIO R952 56
M_SPI_DI H3
URSA_DQ[0-31]
URSA_RASZ
URSA_CASZ
URSA_WEZ
URSA_BA1
URSA_BA0
URSA_MCLKE
URSA_A[0-12]
URSA_DQM1
URSA_DQM0
URSA_DQS0
URSA_DQSB0
URSA_DQS1
URSA_DQSB1
URSA_MCLK1
URSA_MCLKZ1
1

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR PARK.S.W
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LVDS / Mstar FRC 7 15
29 DDR2 1.8V By CAP - Place these Caps near Memory
+1.8V_MEMC +1.8V_FRC_DDR +1.8V_FRC_DDR +1.8V_FRC_DDR
28 BLM18PG121SN1D
L1002
10V
10V
0.1uF
0.1uF
0.1uF
C1006
C1008
C1010
C1011
C1012
C1013
C1014
C1015
C1016
C1017
C1018
C1019
C1020
C1043
C1044
C1045
0.1uF
C1003
C1007
C1009
C1021
C1042
C1024
0.1uF
C1005
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C1026
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10uF
C1027
C1028
C1029
C1030
C1031
C1032
C1033
C1034
C1035
C1036
C1037
C1038
C1039
C1040
C1041
C1004
0.1uF
0.1uF
C1025
10uF
10uF
10uF
27
10uF
10uF
PI Result
26
25
24
23 +1.8V_FRC_DDR +1.8V_FRC_DDR
R1002
1K 1%
R1022
URSA_DQ[0-31]
URSA_A[0-12]
AR1018
1K
22 7:G1;AM22
AR1004
DDR_DQ[15]
DDR_DQ[8] 56
URSA_DQ[15]
URSA_DQ[8]
URSA_DQ[0-31]
7:G1;C22
DDR_DQ[10] URSA_DQ[10]
URSA_DQ[27] DDR_DQ[27]
R1023
1000pF
1K 1%
1000pF
R1003
C1022
0.1uF
C1023
C1002
0.1uF
C1001
IC1001 IC1002
1K
URSA_DQ[25] 56 DDR_DQ[25] AR1017
21 URSA_DQ[30] DDR_DQ[30] H5PS5162FFR-S6C H5PS5162FFR-S6C DDR_DQ[7]

DDR_DQ[0] 56
URSA_DQ[7]
URSA_DQ[0]
AR1003 DDR_DQ[2] URSA_DQ[2]
URSA_DQ[17] DDR_DQ[17] DDR_DQ[16] DQ0 G8 J2 VREF VREF J2 G8 DQ0 DDR_DQ[0]
URSA_DQ[19] 56 DDR_DQ[19] DDR_DQ[17] DQ1 G2 G2 DQ1 DDR_DQ[1] AR1016
20 URSA_DQ[20] DDR_DQ[20] DDR_DQ[18]

DDR_DQ[19]
DQ2
DQ3
H7
H3
M8 A0 DDRB_A[0]
DDRB_A[10] AR1005 URSA_A[10]
URSA_A[3]
URSA_A[1]
AR1012
22
DDRA_A[3]
DDRA_A[1]
DDRA_A[0] A0 M8
H7
H3
DQ2
DQ3
DDR_DQ[2]
DDR_DQ[3]
DDR_DQ[11]
DDR_DQ[12] 56
URSA_DQ[11]
URSA_DQ[12]
DDR_DQ[16-31]
AR1002 A1 DDRB_A[1] DDRA_A[1] A1 DDR_DQ[9] URSA_DQ[9]
DDR_DQ[0-15]
URSA_DQ[31] DDR_DQ[31] DDR_DQ[20] DQ4 M3 DDRB_A[1] 22 URSA_A[1] URSA_A[10] DDRA_A[10] M3 DQ4 DDR_DQ[4]
H1 A2 DDRB_A[2] DDRA_A[2] A2 H1
M7 M7 DDR_DQ[14] URSA_DQ[14]
DDRA_A[0-12]
URSA_DQ[24] DDR_DQ[24] DDR_DQ[21] DQ5 H9 DDRB_A[3] URSA_A[3] H9 DQ5 DDR_DQ[5]
A3 DDRB_A[3] DDRA_A[3] A3
DDRB_A[0-12]
URSA_DQ[26] 56 DDR_DQ[26] DDR_DQ[22] DQ6 N2 DDRB_A[9] URSA_A[9] URSA_A[9] DDRA_A[9] N2 DQ6 DDR_DQ[6]
F1 F1 AR1015
A4 DDRB_A[4] DDRA_A[4] A4
DDR_DQ[24]
DQ7
DQ8
F9
C8
N8
N3 A5 DDRB_A[5]
DDRB_A[12]
DDRB_A[7]
AR1006
22
URSA_A[12]
URSA_A[7]
URSA_A[12] AR1013
URSA_A[7] 22
DDRA_A[12]
DDRA_A[7]
DDRA_A[5] A5
N8
N3
F9
C8
DQ7
DQ8
DDR_DQ[7]
DDR_DQ[8]
DDR_DQ[6]
DDR_DQ[1] 56
URSA_DQ[6]
URSA_DQ[1]
AR1001 N7 A6 DDRB_A[6] DDRA_A[6] A6 N7 DDR_DQ[3] URSA_DQ[3]
URSA_DQ[23] DDR_DQ[23] DDR_DQ[25] DQ9 DDRB_A[5] URSA_A[5] URSA_A[5] DDRA_A[5] DQ9 DDR_DQ[9]
C2 A7 DDRB_A[7] DDRA_A[7] A7 C2
P2 DDRB_A[0] URSA_A[2] DDRA_A[2] P2 DDR_DQ[4] URSA_DQ[4]
URSA_DQ[16] DDR_DQ[16] DDR_DQ[26] DQ10 D7 URSA_A[0] D7 DQ10 DDR_DQ[10]
P8 A8 DDRB_A[8] DDRA_A[8] A8 P8
URSA_DQ[18] 56 DDR_DQ[18] DDR_DQ[27] DQ11 DDRB_A[2] AR1007 URSA_A[2] URSA_A[0] AR1014 DDRA_A[0] DQ11 DDR_DQ[11]
D3 A9 DDRB_A[9] DDRA_A[9] A9 D3
DDR_DQ[29]
DQ12
DQ13
D1
D9
P3
M2 A10/AP DDRB_A[10]
DDRB_A[4]
DDRB_A[6]
22 URSA_A[4]
URSA_A[6]
URSA_A[6]
URSA_A[4]
22 DDRA_A[6]
DDRA_A[4]
DDRA_A[10] A10/AP
P3
M2
D1
D9
DQ12
DQ13
DDR_DQ[12]
DDR_DQ[13]
P7 A11 DDRB_A[11] AR1008 DDRA_A[11] A11 P7
DDR_DQ[30] DQ14 B1 AR1011 B1 DQ14 DDR_DQ[14]
A12 DDRB_A[12] B_URSA_RASZ URSA_RASZ URSA_RASZ A_URSA_RASZ DDRA_A[12] A12
DDR_DQ[31] DQ15 R2 R2 DQ15 DDR_DQ[15]
B9 B_URSA_CASZ URSA_CASZ URSA_CASZ A_URSA_CASZ B9
DDRB_A[11] URSA_A[11] URSA_A[8] 22 DDRA_A[8]
17 +1.8V_FRC_DDR
L2
L3
BA0
BA1
B_URSA_BA0
B_URSA_BA1
DDRB_A[8]
22
URSA_A[8] URSA_A[11] DDRA_A[11]
A_URSA_BA0
A_URSA_BA1
BA0
BA1
L2
L3
+1.8V_FRC_DDR
VDD5 A1 A1 VDD5
R1004 22 R1013 22
VDD4 URSA_MCLK 7:B3 7:G1 URSA_MCLK1 VDD4
R1001
E1 E1
R1024
OPT
OPT
150
150
VDD3 J9 J8 CK CK J8 J9 VDD3
VDD2 CK R1005 22 R1014 22 CK VDD2
16 VDD1
M9
R1
K8
K2 CKE
URSA_MCLKZ
B_URSA_MCLKE
7:B3
T11
7:G1 URSA_MCLKZ1
U10 A_URSA_MCLKE
CKE
K8
K2
M9
R1 VDD1
K9 ODT R1006 22 R1015 22 ODT K9

URSA_ODT 7:B3;X15 7:B3;Q15 URSA_ODT
VDDQ10 A9 L8 CS CS L8 A9 VDDQ10
15 VDDQ9
VDDQ8
C1
C3
K7
L7
RAS
CAS
B_URSA_RASZ
B_URSA_CASZ
R17 X17 A_URSA_RASZ
A_URSA_CASZ
RAS
CAS
K7
L7
C1
C3
VDDQ9
VDDQ8
R17 X17
VDDQ7 C7 K3 WE WE K3 C7 VDDQ7
B_URSA_WEZ T11 U10 A_URSA_WEZ
VDDQ6 C9 C9 VDDQ6
VDDQ5 E9 E9 VDDQ5
LDQS R1007 56 R1016 56 LDQS
14 VDDQ4
VDDQ3
G1
G3
F7
B7 UDQS R1008 56
URSA_DQS2
URSA_DQS3
7:B4
7:B4
7:F1
7:F1
URSA_DQS0
URSA_DQS1
R1017 56 UDQS
F7
B7
G1
G3
VDDQ4
VDDQ3
VDDQ2 G7 G7 VDDQ2
VDDQ1 G9 F3 LDM R1009 56 R1018 56 LDM F3 G9 VDDQ1
URSA_DQM2 7:B4 7:F1 URSA_DQM0
B3 UDM R1010 56 R1019 56 UDM B3
URSA_DQM3 URSA_DQM1
13 7:B4 7:F1
VSS5 A3 E8 LDQS R1011 56 R1020 56 LDQS E8 A3 VSS5

URSA_DQSB2 7:B4 7:F1 URSA_DQSB0
VSS4 E3 A8 UDQS R1012 56 R1021 56 UDQS A8 E3 VSS4
URSA_DQSB3 7:B4 7:F1 URSA_DQSB1
VSS3 J3 J3 VSS3
VSS2 VSS2
12 VSS1
N1
P9
L1
R3
NC4
NC5 B_URSA_BA0
AR1009
URSA_BA0 7:D1;T11
NC4
NC5
L1
R3
N1
P9 VSS1
NC6 B_URSA_BA1 URSA_BA1 7:D1;T10 NC6

R7 R7
Q16 B_URSA_MCLKE URSA_MCLKE 7:E1;T10
VSSQ10 Q14 B_URSA_WEZ URSA_WEZ 7:D1;T10 VSSQ10
B2 NC1 22 NC1 B2
11 VSSQ9
VSSQ8
B8
A7
A2
E2 NC2
7:D1;U12 URSA_BA0
AR1010
A_URSA_BA0
NC2
A2
E2
B8
A7
VSSQ9
VSSQ8
R8 NC3 AA17 NC3 R8
VSSQ7 D2 +1.8V_FRC_DDR D2 VSSQ7
+1.8V_FRC_DDR 7:D1;U12 URSA_BA1 A_URSA_BA1 AA17
VSSQ6 D8 D8 VSSQ6
7:E1;U11 URSA_MCLKE A_URSA_MCLKE Z16
VSSQ5 E7 VSSDL VSSDL E7 VSSQ5
J7 7:D1;U11 URSA_WEZ A_URSA_WEZ J7
10 VSSQ4
VSSQ3
F2
F8
22 X14
F2
F8
VSSQ4
VSSQ3
VSSQ2 H2 H2 VSSQ2
VSSQ1 H8 J1 VDDL VDDL J1 H8 VSSQ1
6
resonance Compensation
5 +1.8V_MEMC
+1.8V_FRC_DDR
4
0.1uF
C1046
0.1uF
0.1uF
C1047
C1048
C1049
C1050
C1051
C1052
C1053
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF

1 ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
M-STAR FRC DDR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HONG.Y.H 8 15
A B C D E F G H I J
RESET Hot Plug input pin should be feeded over 5mA.

BCM Recommend
IC100
D3.3V
P100 BCM3556
D3.3V D3.3V GIL-G-06-S3T2
R2003
0 J23 N26
R2025 OPT EBI_ADDR3 GPIO_00
0 J24 L26
OPT 1 EBI_ADDR4 GPIO_01 TUNER_RESETb I3;14:A6
R409
POWER_DET H25 N25
910
7 12:B3;12:I4 EBI_ADDR2 GPIO_02
R410
IC400 H24 L25 R199 22
10K
EBI_ADDR1 GPIO_03 OPT
KIA7029AF 2 H23 K27 R2001 22
G6 BCM_AVC_DEBUG_TX1 EBI_ADDR0 GPIO_04 OPT
J25 K28 R2002 22
R408 EBI_ADDR5 GPIO_05
330 I O F26 K24
RESET 1 3 SYS_RESETb 3 D3.3V EBI_ADDR6 GPIO_06 OPT
G6 BCM_AVC_DEBUG_RX1 H28 K26 100 OPT R2005
10:I2;12:I5 2 10:E4 EBI_ADDR8 GPIO_07 AMP_RST
J26 K25 100 R2004
G EBI_ADDR9 GPIO_08 VREG_CTRL
C400 4 H27 AA27
10uF EBI_ADDR13 GPIO_09 PWM_DIM I3;4:A5;7:I5
G26 AA28 R2009 100
4.7K
R116
EBI_ADDR12 GPIO_10
J27 AA26
5 EBI_ADDR11 GPIO_11 GAIN_SWITCH 14:A6
G5 BCM_AVC_DEBUG_TX2 J28 L1
EBI_ADDR10 GPIO_12 DSUB_DET
F27 L3 OPT
EBI_ADDR7 GPIO_13
6 G24 L2 0 R189
G5 BCM_AVC_DEBUG_RX2 EBI_TAB GPIO_14
R117 H26 Y25
EBI_WE1B GPIO_15 BCM_RX
33 G27 Y26
EBI_CLK_IN GPIO_16 BCM_TX
G28 M27
EBI_CLK_OUT GPIO_17
K23 AA25
EBI_RWB GPIO_18 RF_SWITCH 14:A6
G25 R25
EBI_CS0B GPIO_19
NAND_IO[0-7] N28
GPIO_20 SIDE_CVBS_DET
N27 R105
GPIO_21 22
D3.3V NAND_IO[0] U24 AH18
AUDIO_M_CLK
6 NAND_IO[1]
NAND_IO[2]
T26
T27
NAND_DATA0
NAND_DATA1
GPIO_22
GPIO_23
P23
M23
0 R195
OPT
3:C4
NAND_DATA2 GPIO_24 A_DIM
4.7K
4.7K
4.7K
NAND_IO[3] I3;4:A6
U26 AD19 100 R2008
NAND_DATA3 GPIO_25
NAND_IO[4] U27 AE19
NAND_DATA4 GPIO_26
NAND_IO[5] V26 M4
NAND_DATA5 GPIO_27 BIT_SEL
NAND_IO[6] V27 M5 R2018 OPT 100
R194
R193
R192
NAND_DATA6 GPIO_28 LVDS_SEL
NAND_IO[7] V28 L23 R3030 100
NAND_DATA7 GPIO_29 OPT
SMD Gasket Option T24 Y28
NVRAM D3.3V C3
C2
C3
NAND_CEb
NAND_ALE
NAND_REb
R23
T23
NAND_CS0B
NAND_ALE
GPIO_30
GPIO_31
Y27
G2 SF_SCK 0 R198 OPT
BCM_AVC_DEBUG_TX1
BCM_AVC_DEBUG_RX1
C7
C7
NAND_REB GPIO_32
C2 NAND_CLE T25 G3 SF_MISO 0 R196 OPT
32/42/55 - 6T SMD Gasket NAND_CLE GPIO_33
C2 NAND_WEb R24 G5 SF_MOSI 0 R197 OPT
NAND_WEB GPIO_34
C3 NAND_RBb U25 G6 SF_CSB 0 R109 OPT
GAS1 GAS2 GAS3 GAS4 GAS5 NAND_RBB GPIO_35
IC403 G4
GPIO_36 AV1_CVBS_DET 14:A5
MDS61887702
MDS61887702
MDS61887702
MDS61887702
MDS61887702
L24 0 R161
AT24C512BW-SH-T
GAS5_6T
GPIO_37 BLUETOOTH_RESET
GAS1_6T
GAS2_6T
GAS3_6T
GAS4_6T
I3;14:I3
4.7K
W24 P25
4.7K
R422
SF_MISO GPIO_38
U23 L5 R103 100
R419
SF_MOSI GPIO_39 FRC_RESET 7:H2

A0 VCC V23 K4
1 8 SF_SCK GPIO_40
V24 K1
C416 SF_CSB GPIO_41
0.1uF L27
BCM_AVC_DEBUG_RX2
5 A1
2 7
WP GPIO_42
GPIO_43
M26
N23
BCM_AVC_DEBUG_TX2
C6
C7
R3016 R411 GPIO_44
A2 SCL R28
4.7K 22 GPIO_45
3 6 SCL2_3.3V I4;12:F3 R27
47 - 7T SMD Gasket
GPIO_46
R412 R26
GND SDA 22 GPIO_47
4 5 GAS1-*1 GAS2-*1 GAS3-*1 GAS4-*1 GAS5-*1 P28
SDA2_3.3V I4;12:F3 GPIO_48
P27
MDS61887703
MDS61887703
MDS61887703
MDS61887703
MDS61887703
GPIO_49
GAS1_7T
GAS2_7T
GAS3_7T
GAS4_7T
GAS5_7T
K6
GPIO_50 R2024
K5 22
GPIO_51 DDC_SCL I3;14:A6
P26 22 R160 D3.3V
GPIO_52 DDC_SDA I3;14:A6
M3 22 R102
GPIO_53
M2
GPIO_54 HDMI_HPD_IN
M1 OPT OPT
GPIO_55 COMP1_DET 14:A6
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
R187
R184
R183
R180
R177
R176
R171
R170
L4
GPIO_56
L6
GPIO_57 COMP2_DET 14:A5
W27 22 R186
SGPIO_00 SCL0_3.3V 14:A6
W28 22 R174
SGPIO_01 SDA0_3.3V 14:A6
W26 22 R175
SGPIO_02 SCL1_3.3V 3:D3;2:AH5
W25 22 R178
SGPIO_03 SDA1_3.3V 3:D3;2:AH5
J2 22 R179
SCL2_3.3V
4 SGPIO_04
SGPIO_05
J1
K3
22
22
R181
R182
SDA2_3.3V
B5;12:F3
B5;12:F3
SGPIO_06 SCL3_3.3V 7:B6
K2 22 R185
SGPIO_07 SDA3_3.3V 7:B6
* NAND FLASH MEMORY 1Gbit (128M)
Boot Strap D3.3V

D3.3V
D3.3V D3.3V D3.3V

IC101
2.7K
NAND01GW3A2CN6E
R2016
R2010
R2011
R2013
R2014
R2015
2.7K
2.7K
2.7K
2.7K
2.7K
R2032
2.7K
OPT
2.7K
* I2C MAP
2.7K
2.7K
R316
R314
R131
NC_1 NC_29
E3;E6 1 48
NAND_IO[0] NAND_IO[3] NAND_IO[2]
NC_2 NC_28
* I2C_0 : TUNER
2.7K
G6;4:A6
2.7K
2 47 A_DIM
E3;E6
R2029
E3;E6 G7;4:A5;7:I5 PWM_DIM

OPT
2.7K
2.7K
NC_3 NC_27 * I2C_1 : Audio amp, HDMI S/W

R317
3 46
BLUETOOTH_RESET
NC_4 NC_26 NAND_IO[0-7]
3 4 45 * I2C_2 : NVRAM,Micom
R191
R2040
NC_5 I/O7 NAND_IO[7]

5 44 G7;12:I4;3:C5 AMP_RST
NC_6 I/O6
* I2C_3 : FRC
NAND_IO[6] VREG_CTRL
6 43
Open Drain RB I/O5 HDMI_HPD_IN
NAND_RBb 7 42 NAND_IO[5]
E5 G7;14:A6 TUNER_RESETb
D3.3V R I/O4
D3.3V NAND_REb 8 41 NAND_IO[4]
E6
E NC_25
E6 NAND_CEb 9 40
R2033
2.7K
NC_7 NC_24 D3.3V

R321
2.7K
10 39
OPT
C3024
4700pF NC_8 NC_23
NAND_IO[0-7]
E3;E6 11 38 C136 10uF
NAND_IO[4] NAND_IO[5] NAND_IO[6] 6.3V
VDD_1 VDD_2
E3;E6 C114 12 37
R2031
E3;E6
R2030
C115
2.7K
2.7K
0.1uF
2.7K
VSS_1 VSS_2 0.1uF

R315
13 36
NC_9 NC_22
OPT
14 35
NC_10 NC_21
15 34
CL NC_20
E5 NAND_CLE 16 33
NAND_IO[0] : Flash Select (1) IF FUNDMENTAL IS USED => LOW AL I/O3 NAND_IO[3]
E6 NAND_ALE 17 32
2 0 : Boot From Serial Flash
1 : Boot From NAND Flash IF DIP IS USED => HIGH E5 NAND_WEb
W
18 31
I/O2 NAND_IO[2]
D3.3V WP I/O1 NAND_IO[1]

19 30
NAND_IO[1] : NAND Block 0 Write (DNS)
NC_11 I/O0 NAND_IO[0]
0 : Enable Block 0 Write 20 29
R136
4.7K
1 : Disable Block 0 Write NC_12 NC_19

21 28
NC_13 NC_18
NAND_IO[3:2] : NAND ECC (10) 22 27
00 : No ECC C
NC_14 NC_17
23 26
01 : 1 ECC Bit
B Q101 NC_15 NC_16
10 : 4 ECC Bit FLASH_WP_1 KRC103S
24 25
11 : 8 ECC Bit
E
NAND_IO[4] : CPU Endian (0)
0 : Little Endian
1 : Big Endian
NAND_IO[6:5] : Xtal Bias Control (1, DNS)

00 : 1.2mA
01 : 1.8mA
1 10 : 2.4mA (Recommand)
11 : 3.0mA

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR JANG.J.H
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. BCM3556 & NAND FLASH 9 15
A B C D E F G H I J K
When usding FUNDMENTAl then series R = 0 ohm and CL = 8 pF
IC100 54MHz X-TAL

BCM3556 When usding Dip-type X-tal then series R = 22 ohm and CL = 12 pF
D23 B4
TU_SCLK PKT0_CLK LVDS_TX_0_DATA0_P LVDS_TX_1_DATA4_N 7:D7
C24 A4
1 TU_SDATA
TU_SYNC
B26
PKT0_DATA
PKT0_SYNC
LVDS_TX_0_DATA0_N
LVDS_TX_0_DATA1_P
C6
LVDS_TX_1_DATA4_P
LVDS_TX_1_DATA3_N
7:D7
7:D7 22
C230
A25 B6
RMX0_CLK LVDS_TX_0_DATA1_N LVDS_TX_1_DATA3_P 7:D7 12pF
B25 B3 R212
RMX0_DATA LVDS_TX_0_DATA2_P LVDS_TX_1_DATA2_N 7:D7
A26 A3
RMX0_SYNC LVDS_TX_0_DATA2_N LVDS_TX_1_DATA2_P 7:D7
A1
C3012
1008LS-272XJLC 33pF
LVDS_TX_0_DATA3_P LVDS_TX_1_DATA1_N 7:D7
A2
LVDS_TX_0_DATA3_N LVDS_TX_1_DATA1_P 7:D7
G23 D5
POD2CHIP_MCLKI LVDS_TX_0_DATA4_P LVDS_TX_1_DATA0_N 7:D7
D25 D6
2
POD2CHIP_MDI0 LVDS_TX_0_DATA4_N LVDS_TX_1_DATA0_P 7:D7
54MHz
D24 C5
X903
3
L8014
POD2CHIP_MDI1 LVDS_TX_0_CLK_P LVDS_TX_1_CLK_N 7:D7
C25 B5 54MHz_XTAL_N
POD2CHIP_MDI2 LVDS_TX_0_CLK_N LVDS_TX_1_CLK_P 7:D7
E27 B1
1
POD2CHIP_MDI3 LVDS_TX_1_DATA0_P LVDS_TX_0_DATA4_N 7:E7 54MHz_XTAL_P
E26 B2
POD2CHIP_MDI4 LVDS_TX_1_DATA0_N LVDS_TX_0_DATA4_P 7:E7
R3027
D28 C2
POD2CHIP_MDI5 LVDS_TX_1_DATA1_P LVDS_TX_0_DATA3_N 7:E7
604
D27 C3
POD2CHIP_MDI6 LVDS_TX_1_DATA1_N LVDS_TX_0_DATA3_P 7:E7
D26 D1
POD2CHIP_MDI7 LVDS_TX_1_DATA2_P LVDS_TX_0_DATA2_N 7:E7
E23 D2
POD2CHIP_MISTRT LVDS_TX_1_DATA2_N LVDS_TX_0_DATA2_P 7:E7
E24 E1
POD2CHIP_MIVAL LVDS_TX_1_DATA3_P LVDS_TX_0_DATA1_N 7:E7
F25 E2 22
CHIP2POD_MCLKO LVDS_TX_1_DATA3_N LVDS_TX_0_DATA1_P 7:E7 R211 12pF
C27 E3
CHIP2POD_MDO0 LVDS_TX_1_DATA4_P LVDS_TX_0_DATA0_N 7:E7 C229
C26 E4
2 B28
CHIP2POD_MDO1
CHIP2POD_MDO2
LVDS_TX_1_DATA4_N
LVDS_TX_1_CLK_P
D3
LVDS_TX_0_DATA0_P
LVDS_TX_0_CLK_N
7:E7
7:E7
A1.2V A2.5V
B27 D4
CHIP2POD_MDO3 LVDS_TX_1_CLK_N LVDS_TX_0_CLK_P 7:E7
A27 F5 C228 OPT
CHIP2POD_MDO4 LVDS_PLL_VREG 10uF
F24 F1
CHIP2POD_MDO5 LVDS_TX_AVDDC1P2
F23 F4
CHIP2POD_MDO6 LVDS_TX_AVDD2P5_1
E25 F2
CHIP2POD_MDO7 LVDS_TX_AVDD2P5_2
C28 C1
A3.3V A1.2V A2.5V CHIP2POD_MOSTRT LVDS_TX_AVSS_1
A28 F3
CHIP2POD_MOVAL LVDS_TX_AVSS_2
0.1uF
0.1uF
0.1uF
4.7uF
4.7uF
C4
C3005
0
0
R236
R237
C236
C239
C242
C295
LVDS_TX_AVSS_3
A5
L202 LVDS_TX_AVSS_4
BLM18PG121SN1D AC18 E5
VDAC_AVDD2P5 LVDS_TX_AVSS_5
AF20 E6
VDAC_AVDD1P2 LVDS_TX_AVSS_6
AG20 D7
VDAC_AVDD3P3_1 LVDS_TX_AVSS_7
4.7uF
AG21 E7
0.1uF
0.1uF
0.1uF
VDAC_AVDD3P3_2 LVDS_TX_AVSS_8
C214
C219
C223
C212
F7
BROAD BAND STUDIO LVDS_TX_AVSS_9
G7
LVDS_TX_AVSS_10 A1.2V
AF19 H7
VDAC_AVSS_1 LVDS_TX_AVSS_11
AD20 A2.5V
VDAC_AVSS_2
0.1uF
D3.3V AE20
C218
R220 560AH22 VDAC_AVSS_3
R220 : BCM recommened resistor 562 ohm AD27
3
C3008
0.1uF
P200 C215 VDAC_RBIAS CLK54_AVDD1P2
R241 0 AH20 AD28
TJC2508-4A 0.1uF VDAC_1 CLK54_AVDD2P5
OPT AG19 AD26
VDAC_2 CLK54_AVSS
C213 AC26
JP200 0.01uF CLK54_XTAL_N 54MHz_XTAL_N I2
MNT OUT FOR BCM AH21 AC27
4.7uF
R200
1.5K
54MHz_XTAL_P
R201
1.5K
1 VDAC_VREG CLK54_XTAL_P I2
C200
AE25
JP201 CLK54_MONITOR
R242 0 Y23
PM_OVERRIDE
2 OPT M25
BSC_S_SCL
M24
JP202 BSC_S_SDA
AA23 A1.2V
3 VCXO_AGND_1
AB24
JP203 VCXO_AGND_2
R6 AC24 L203
USB_AVSS_1 VCXO_AGND_3 BLM18PG121SN1D
4 T6 AF25
A3.3V USB_AVSS_2 VCXO_AVDD1P2
R7 AF24 C233 C235
A1.2V USB_AVSS_3 VCXO_PLL_AUDIO_TESTOUT 0.1uF 4.7uF
A2.5V T7
USB_AVSS_4
T8
USB_AVSS_5 D3.3V
R3 P24
USB_AVDD1P2 RESET_OUTB
U3 F6 SYS_RESETb
USB_AVDD1P2PLL RESETB 4.7K 9:B7
L200 T4 N24
BLM18PG121SN1D USB_AVDD2P5 NMIB
T3 J5 R221
USB_AVDD2P5REF TMODE_0
R4 J4 A2.5V
4 U4
USB_AVDD3P3
USB_RREF
TMODE_1
TMODE_2
J6 L201
BLM18PG121SN1D
Route INCM between associated V1 J3
0.1uF
0.1uF
0.1uF
4.7uF
0.1uF
USB_DM1 USB_DM1 TMODE_3

left and right signals of same channel V2 V25 A1.2V
USB_DP1 USB_DP1 SPI_S_MISO C231 C234
C201 R209 U1 AH3 10uF 0.1uF
The INCM trace ends at the 3.9K USB_DM2 USB_DM2 POR_OTP_VDD2P5
100pF U2 AB8
same point where the connector
D3.3V USB_DP2 USB_DP2 POR_VDD1P2
ground connects to the board ground T5 D3.3V
C207
C208
C209
C202
C203
(thru-hole connector pin). R210 USB_MONCDR

120 R5 H4
USB_MONPLL EJTAG_TCK
Place test points, resistors R1 H3 OPT OPT
near audio connector. USB_OCD1 USB_PWRFLT_1 EJTAG_TDI
R235 R2 H2 R224 R225
Connect the other side of USB_PWRFLT_2 EJTAG_TDO
the resistor to GND as close 2.7K T2 H1 4.7K 4.7K
USB_CTL1 USB_PWRON_1 EJTAG_TMS
as possible to the ground T1 G1
connection of the associated USB_PWRON_2 EJTAG_TRSTB
H6
audio connector. EJTAG_CE0
P6
EJTAG_CE1
H5
CONNECT NEAR BCM CHIP
R218
240 1K R219 EPHY_VREF R226
P5 L204 A1.2V R227
EPHY_RDAC BLM18PG121SN1D 4.7K 4.7K
P3 AB26
EPHY_RDN PLL_MAIN_AVDD1P2
P2 AC25
A1.2V A2.5V
N3
EPHY_RDP PLL_MAIN_AGND
AB27 R240 INCM
EPHY_TDN PLL_MAIN_MIPS_EREF_TESTOUT
N2 M6 390 L207 A1.2V
EPHY_TDP PLL_RAP_AVD_TESTOUT OPT BLM18PG121SN1D C4001 0.1uF
P1 N6 5.1
5 P4
EPHY_AVDD1P2 PLL_RAP_AVD_AVDD1P2
N7
TU_CVBS_INCM
0.1uF
4.7uF
3:T25 SIDE_INCM
0.1uF
4.7uF
C240
C241
C237
EPHY_AVDD2P5 PLL_RAP_AVD_AGND
C238
N4 R4009 3:T18
0.15uF
EPHY_PLL_VDD1P2 C4010 0.47uF
N1
EPHY_AGND_1 C4014
N5 AA24
EPHY_AGND_2 BYP_CPU_CLK C4002 0.1uF
P7 Y24
EPHY_AGND_3 BYP_DS_CLK SIDE_CVBS_INCM
AE24 5.1
1K R222 3:T19
BYP_SYS216_CLK AV1_INCM 3:T20
AD25 1K R223
BYP_SYS175_CLK R4011
R204 51 C206 15nF AE6 0.15uF
14:A5 AV1_L_IN AUDMX_LEFT1 C4011
R214 51 C210 15nF AD7 0.47uF
14:A5 AV1_R_IN AUDMX_RIGHT1
AF6 C4003 0.1uF C4015
14:A5 AV1_INCM AUDMX_INCM1 AV1_CVBS_INCM
R215 51 C211 15nF AH4 3:T19
14:A6 COMP1_L_IN AUDMX_LEFT2
R228 51 C232 15nF AG5
R4000
R4004
R4006
14:A6 COMP1_R_IN AUDMX_RIGHT2 5.1
AG4
COMP1_INCM AUDMX_INCM2 COMP1_INCM
34
34
34
14:A6 AG6
R229 51 C220 15nF R4012
14:A5 COMP2_L_IN AUDMX_LEFT3 3:T24
R230 51 C221 15nF AF7 0.15uF C4016
14:A5 COMP2_R_IN AUDMX_RIGHT3 C4008
AE7 0.47uF
14:A5 COMP2_INCM AUDMX_INCM3
R231 51 C224 15nF AH5
14:A4 SIDE_L_IN AUDMX_LEFT4
R232 51 C225 15nF AG7
14:A4 SIDE_R_IN AUDMX_RIGHT4
AH6
14:A4 SIDE_INCM AUDMX_INCM4
AD8
6 14:A3
14:A3
PC_L_IN
PC_R_IN
R233
R234
51
51
C226
C227
15nF
15nF AF8
AUDMX_LEFT5
AUDMX_RIGHT5
C4004 0.1uF
COMP1_VID_INCM 3:T23
5.1
R4010
COMP2_INCM
3:T22
AE8 0.15uF
14:A3 PC_INCM AUDMX_INCM5
AH7 C4009 0.47uF
AUDMX_LEFT6 C4005 0.1uF
AH8 COMP2_VID_INCM C4013
R4001
R4005
AUDMX_RIGHT6 3:T21
AG8
AUDMX_INCM6
34
34
AF5
AUDMX_AVSS_1
AB9 5.1
AUDMX_AVSS_2
AA10 PC_INCM
AUDMX_AVSS_3
AB10 R4008 3:T14
0.15uF
47nF
47nF
47nF
47nF
47nF
C3004 47nF
C3007 47nF
C3001 47nF
C3002 47nF
C3003 47nF
AUDMX_AVSS_4 C4000 0.1uF 0.47uF

AA11 R_VID_INCM C4012
C222 AUDMX_AVSS_5 3:T15 C4017
AB11
0.1uF AUDMX_AVSS_6
AC8
C274
C277
C279
C296
C298
AUDMX_LDO_CAP C4006 0.1uF

AE5 G_VID_INCM
AUDMX_AVDD2P5 3:T15
C4007 0.1uF
B_VID_INCM
R4002
R4003
R4007
3:T15
34
34
34
A2.5V
7 C217
10uF

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR JANG.J.H
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. BCM3556 AUD_IN/LVDS 10 15
A B C D E F G H I J
7
IC100
BCM3556
AG28 AE18 R162 0

DS_AGCI_CTL I2S_CLK_IN
AH28 AF18 OPT
DS_AGCT_CTL I2S_CLK_OUT BCM_I2S_BIT_CLK 3:D3
AA21 AD17 R163 0
EDSAFE_AVSS_1 I2S_DATA_IN
A2.5V AB22 AH19 OPT
EDSAFE_AVSS_2 I2S_DATA_OUT BCM_I2S_DATA_OUT
AF26 AD18 R164 0 3:D3
EDSAFE_AVSS_3 I2S_LR_IN
A1.2V AF27 AG18 OPT
BLM18PG121SN1D EDSAFE_AVSS_4 I2S_LR_OUT 0 BCM_I2S_WORD_CLK 3:D3
AF28 AG26 R165
L102 EDSAFE_AVSS_5 AUD_LEFT0_N A2.5V
AG27 AH26 OPT
EDSAFE_AVDD2P5 AUD_LEFT0_P
AE26 AF23
EDSAFE_DVDD1P2 AUD_AVDD2P5_0
AE28 AA20 C147 C155 C162
C113 C116 EDSAFE_IF_N AUD_AVSS_0_1 0.01uF 0.1uF 10uF
A1.2V AE27 AB21
0.1uF 4.7uF C144 EDSAFE_IF_P AUD_AVSS_0_2
0.1uF AD24 AC22
L103 PLL_DS_AGND AUD_AVSS_0_3
AB19 AC23
PLL_DS_AVDD1P2 AUD_AVSS_0_4
C119 C122 AB25 AD23
BLM18PG121SN1D PLL_DS_TESTOUT AUD_AVSS_0_5
0.1uF 4.7uF AH25 R168 0
6 A1.2V A2.5V
AB18
AUD_RIGHT0_N
AUD_RIGHT0_P
AG25
AH23 R166
OPT
0
BLM18PG121SN1D SD_V5_AVDD1P2 AUD_LEFT1_N
C111 C112 AC17 AG23 OPT
SD_V5_AVDD2P5 AUD_LEFT1_P R167 0
0.1uF 0.1uF
L104 C120 C123 AB17 AG24
SD_V5_AVSS AUD_RIGHT1_N
1000pF 0.01uF AD14 AH24 OPT
BLM18PG121SN1D SD_V1_AVDD1P2 AUD_RIGHT1_P
AD16 AE22
SD_V1_AVDD2P5 AUD_AVDD2P5_1
AB15 AB20 C148 C156 C163
L105 SD_V1_AVSS_1 AUD_AVSS_1_1
AC15 AC21 0.01uF 0.1uF 10uF
C117 SD_V1_AVSS_2 AUD_AVSS_1_2
1000pF C118 AD13 AE23
0.01uF SD_V2_AVDD1P2 AUD_AVSS_1_3 R169 0
AE13 AF21
SD_V2_AVDD2P5 AUD_LEFT2_N
AC13 AE21 OPT
SD_V2_AVSS_1 AUD_LEFT2_P R172 0
AB14 AF22
SD_V2_AVSS_2 AUD_RIGHT2_N
AC14 AG22 OPT
SD_V2_AVSS_3 AUD_RIGHT2_P
14:A4 DSUB_R AC12 AD21
SD_V3_AVDD1P2 AUD_AVDD2P5_2 A2.5V
14:A4 R_VID_INCM AD12 AC20 C149 C157 C164 A2.5V
SD_V3_AVDD2P5 AUD_AVSS_2_1 0.01uF 0.1uF 10uF
14:A4 DSUB_G AB13 AD22
470
270
SD_V3_AVSS_1 AUD_AVSS_2_2
14:A3 G_VID_INCM AA14 AH2
SD_V3_AVSS_2 AUD_SPDIF SPDIF_OUT14:A3
OPT
14:A3 DSUB_B AC11 AC6
SD_V4_AVDD1P2 SPDIF_AVDD2P5
AD11 AE4
R3041
OPT
14:A3 B_VID_INCM
R3042
SD_V4_AVDD2P5 SPDIF_AVSS C150 +5.0V
AB12 AF3 0.1uF
5 C127 0.1uF AD10
SD_V4_AVSS SPDIF_IN_N
AH1
75
R118 75
14:A6 COMP1_Y_IN
R119 75
SD_R SPDIF_IN_P
AC10
R2035
COMP1_Pr_IN HDMI_HPD_IN_5MA
10pF
10pF
14:A5
10pF
C101
C102
C103
SD_INCM_R
R115
14:A6 COMP1_Pb_IN C128 0.1uF AE9 R2036
SD_G C
1K
0
14:A6 COMP1_VID_INCM AF9 AG1
SD_INCM_G HDMI_RX_0_CEC_DAT Q906 B
OPT
C129 0.1uF AH9 AA6 ISA1530AC1 HDMI_HPD_IN 9:G4;9:I3

91
R127 91
91
SD_B HDMI_RX_0_HTPLG_IN HDMI_HPD_IN_5MA G5

AG9 AA5 R188 10K A2.5V
10pF
SD_INCM_B HDMI_RX_0_HTPLG_OUT E
R120
C130
C104
R129
0.1uF AG15 AB3 0 R157

SD_Y1 HDMI_RX_0_DDC_SCL HDMI_SCL 2:AA19
C131 0.1uF AE15 Y6 0 R158
SD_PR1 HDMI_RX_0_DDC_SDA HDMI_SDA 2:AA19
C132 0.1uF AF15 AC4 499 R152
SD_PB1 HDMI_RX_0_RESREF C3006
AH15 AC1
SD_INCM_COMP1 HDMI_RX_0_CLK_N HDMI0_RXC-_BCM 2:AA18 0.1uF
C133 0.1uF AG16 AC2
14:A5 COMP2_Y_IN SD_Y2 HDMI_RX_0_CLK_P HDMI0_RXC+_BCM 2:AB18 16V
C134 0.1uF AF16 AD1
14:A5 COMP2_Pr_IN SD_PR2 HDMI_RX_0_DATA0_N HDMI0_RX0-_BCM 2:AB18
C135 0.1uF AH17 AD2
14:A5 COMP2_Pb_IN SD_PB2 HDMI_RX_0_DATA0_P HDMI0_RX0+_BCM 2:AB18 A3.3V
AH16 AE1
14:A5 COMP2_VID_INCM SD_INCM_COMP2 HDMI_RX_0_DATA1_N HDMI0_RX1-_BCM 2:AC18
AG14 AE2
OPT
HDMI0_RX1+_BCM
R135 91
R138 91
R140 91 TP101 SD_Y3 HDMI_RX_0_DATA1_P 2:AC18

AE14 AF1 BLM18PG121SN1D
TP102 SD_PR3 HDMI_RX_0_DATA2_N HDMI0_RX2-_BCM 2:AC18 L109
10pF
AF14 AF2
C105
TP103 SD_PB3 HDMI_RX_0_DATA2_P HDMI0_RX2+_BCM 2:AD18

AH14 AD3 A1.2V A2.5V
TP104 SD_INCM_COMP3 HDMI_RX_0_VDD3P3
AH10 AE3
TP105 SD_L1 HDMI_RX_0_VDD1P2
AG10 AC3
4 R142 91
TP106
TP107
AE10
AE11
SD_C1
SD_INCM_LC1
HDMI_RX_0_VDD2P5
HDMI_RX_0_AVSS_1
AD4
AB5
C145
4.7uF
C153
0.1uF
C160
0.1uF
TP108 SD_L2 HDMI_RX_0_AVSS_2 BLM18PG121SN1D
AF11 AB6
OPT TP109 SD_C2 HDMI_RX_0_AVSS_3 L107
R143 91 AH11 AG2
TP110 SD_INCM_LC2 HDMI_RX_0_AVSS_4
AH13 AB4
OPT TP111 SD_L3 HDMI_RX_0_AVSS_5
R141 AE12 AA7
75 TP112 SD_C3 HDMI_RX_0_AVSS_6
AF12 Y8
OPT TP113 SD_INCM_LC3 HDMI_RX_0_PLL_AVSS C158 C151 C165
C110 0.1uF AD9 AC5 1000pF 0.01uF 10uF
14:A6 TU_CVBS_IN SD_CVBS1 HDMI_RX_0_PLL_DVDD1P2
C124 0.1uF AG11 W8
14:A5 AV1_CVBS_IN SD_CVBS2 HDMI_RX_0_PLL_DVSS
C125 0.1uF AG12
14:A5 SIDE_CVBS_IN SD_CVBS3 D3.3V
10K
10K
10K
10K
AF13
R2037
SD_CVBS4
OPT
14:A6 TU_CVBS_INCM AC9 AA3
14:A5 AV1_CVBS_INCM SD_INCM_CVBS1 HDMI_RX_1_CEC_DAT
AF10 V4
R146
R2039
SD_INCM_CVBS2 HDMI_RX_1_HTPLG_IN
R2038
14:A5 SIDE_CVBS_INCM A2.5V AH12 U6
A2.5V
SD_INCM_CVBS3 HDMI_RX_1_HTPLG_OUT
AG13 V5
AF17
SD_INCM_CVBS4 HDMI_RX_1_DDC_SCL
V3
R4020 SD_SIF1 HDMI_RX_1_DDC_SDA
R137 AG17 W4 499 R153
10K 10K SD_INCM_SIF1 HDMI_RX_1_RESREF
AD15 W2
0.1uF SD_FB HDMI_RX_1_CLK_N
R128 C106 A1.2V AE16 W3
0 SD_FS HDMI_RX_1_CLK_P
L106 AE17 Y1
3 14:A6 TU_SIF
R3055
240
R139
BLM18PG121SN1D AB16
AA15
SD_FS2 HDMI_RX_1_DATA0_N
HDMI_RX_1_DATA0_P
PLL_VAFE_AVDD1P2
Y2
AA2
A3.3V
C121 C140
12K PLL_VAFE_AVSS HDMI_RX_1_DATA1_N
0.1uF 4.7uF AC16 AA1
HDMI_RX_1_DATA1_P
AG3 PLL_VAFE_TESTOUT AB2 BLM18PG121SN1D
RGB_HSYNC HDMI_RX_1_DATA2_N
R4021
AF4 AB1 L110

12K
C4020 RGB_VSYNC HDMI_RX_1_DATA2_P

120
R3056
Y3 A1.2V A2.5V
0.1uF HDMI_RX_1_VDD3P3
Y4
HDMI_RX_1_VDD1P2
W5
HDMI_RX_1_VDD2P5
W1
HDMI_RX_1_AVSS_1
U5 C146 C154 C161
14:A3 RGB_HSYNC HDMI_RX_1_AVSS_2 4.7uF 0.1uF 0.1uF
W6
14:A3 RGB_VSYNC HDMI_RX_1_AVSS_3 BLM18PG121SN1D
CONNECT NEAR BCM CHIP U7
HDMI_RX_1_AVSS_4 L108
V7
HDMI_RX_1_AVSS_5
W7
HDMI_RX_1_AVSS_6
U8
HDMI_RX_1_AVSS_7
V8
HDMI_RX_1_AVSS_8
Y5
HDMI_RX_1_AVSS_9
V6
HDMI_RX_1_PLL_AVSS
AA4
HDMI_RX_1_PLL_DVDD1P2
Y7 C159 C152 C166
2 HDMI_RX_1_PLL_DVSS 1000pF 0.01uF 10uF

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BRAZIL VENUS 2009.03.23
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR JANG.J.H.
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. BCM3556 VIDEO IN 11 15
A B C D E F G H I J
14:E6
14:E7
14:E5
14:E5
7
4:C5
UCOM_SDA_3.3V
UCOM_SCL_3.3V
LED_WARM_STBY
LED_POWER_ON
ERROR_OUT
+3.3V_ST
R435 : READY FO 1.2V BCM ENABLE

D3.3V
R454 2K
2:AD26
R451 2K
100
100
100
100
100
OPT
OPT
HDMI_CEC
4.7K
100
R435
R439
+3.3V_ST +3.3V_ST
R440
R464
R471
R474
R470
IC402 +3.3V_ST
OPT
R489
R444
R442
33K
0
+3.3V_ST
R414
10K
P1.4/DA3
P1.3/DA2
P1.2/DA1
P1.1/DA0
P1.0/ET2
P4.2/AD2
R407
47K
KIA7029AF
C410
R488
C C407 GND C411
33K
Q401 0.1uF 100uF
I O B OPT
16V 16V
P5.0
P5.1
P5.2
P5.3
1 3
OPT
2SC3875S(ALY)
VDD
2
E
C402 G C403 GND
0.1uF 0.1uF +3.3V_ST R430
16V 16V GND
100
R401
44
43
42
41
40
39
38
37
36
35
34
1K
HSYNC/P1.5 P5.4
4.7K
R427
GND GND GND
1 33 R465 100
5 OPT VSYNC/P1.6 P5.5 R466 OPT 100
PANEL_CTL 4:H1
M5V_ON 2 32 FLASH_WP_1 4:C5

R403 0
R416 0
P1.7/SOGI 3 31 P5.6 R468 100
OPT
INV_ON/OFF 4:C5
+3.3V_ST
RST P5.7/CLKO2
OPT
4 30 R467 22
RL_ON 4:C7;14:E5
R402
HSCL1/P3.0/RXD P7.0/HBLANK
R499
4.7K
R494
4.7K
R406 R431 100
R417 22
5 29 RESET 9:A7
GND 4.7K
IC406 OPT
9:G7;14:A4 DDC_SCL P4.3/AD3 6 28 P4.1/AD1
HSDA1/P3.1/TXD MTV416GMF P7.1/VBLANK
9:G7;14:A4 DDC_SDA R420 22 7 27 R475 1K
POWER_DET 9:C1
R421 4.7K
P3.2/INT0 8 26 P7.2/HCLAMP
14:A3;14:E6 IR AMP_RST 9:G7;9:I3;3:C5
R405
220 R423 OPT P3.3/INT1 9 25 P6.7 R449 100
14:H2 UCOM_RX
OPT
R424 22
ISDA/P3.4/T0 10 24 P6.6 R450 100 OPT +5.0V
R404
OPT
220 ISCL/P7.5 11 23 P6.5
4 14:I1 UCOM_TX R425 22
15K
R472
4.7K
12
13
14
15
16
17
18
19
20
21
22
R460
6.8K
C412
68K
R461
C415 R429 0.1uF
OPT
R428
R418 0.1uF OPT OPT EDID_WP 14:A4
4.7K
OPT
16V
HSDA2/P7.4
HSCL2/P7.3
X2
X1
VSS
P4.0/AD0
P6.0/CLKO1
P6.1
P6.2
P6.3
P6.4
C
GND B Q402
+3.3V_ST RT1N141C-T112-1
OPT
R459
4.7K E
GND R447 4.7K

POWER DETECT +3.3V_ST
+5V_ST +24V
OPT
R455
4.7K GND
R452 R462
+5.0V 47K OPT 100
R485 KEY2 14:E6

OPT IC405 +3.3V_ST GND
+12V 10K 9:A7;I4
R481 R484 R456
R482
OPT
R478 POWER_DET 30K 100

30K KEY1 14:E6
10K 0
OPT
R453
100
OPT C
22
1K
OPT
0
0
R479 X401
R476 B Q405 24LC16BT-I/SN 24MHz
3 15K
1K
2SC3052 R490
0
OPT +3.3V_ST C414
R446
R415
OPT C
R441
R443
R445
R413
C413
22
22
R492 E C408 C409 0.1uF
0 A0 VCC 0.1uF
B Q404 R480 1 8 22pF 22pF GND 16V
IC1003 C406
OPT
OPT
2.2K
R432
READY FO 1.2V BCM ENABLE

50V 50V
R434
R436
2SC3052
47K
OPT OPT NCP803SN293 0.1uF
4.7K
4.7K
E A1 WP 16V
R495
R496
R477
2 7
4.7K
4.7K
6.8K RESET VCC OPT

2 3
1 R486 A2 SCL
R487 3 6
0 GND GND
100K GND
R491
5.1K
OPC_EN
AMP_MUTE
OPT VSS SDA
4 5
SDA2_3.3V
SCL2_3.3V
3:E3
R483 GND
7:I5
0
9:B5;9:I4
9:B5;9:I4
2

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
LIM.K.R MICOM 12 15
A B C D E F G H I J
D1.2V
C243 C249 C250 C251 C252 C253 C254 C286 C287

0.1uF 4.7uF 1000pF 0.01uF 0.1uF 10uF 10uF 33uF 33uF
IC100
BCM3556
6
D1.2V D1.2V
IC100 AD5 P16
BCM3556 AD6
DVSS_1 DVSS_62
R16
DVSS_2 DVSS_63
J7 T16
DVSS_3 DVSS_64
K7 U16
H8 DVSS_4 DVSS_65
VDDC_1 L7 V16
C244 C246 C256 C258 C259 C262 C265 C266 C288 C290 J8 DVSS_5 DVSS_66
1000pF 0.01uF 0.1uF 4.7uF 1000pF 0.01uF 0.1uF 4.7uF 1000pF 0.01uF VDDC_2 M7 AA16
K8 DVSS_6 DVSS_67
VDDC_3 AB7 D17
L8 DVSS_7 DVSS_68
VDDC_4 AC7 L17
M8 DVSS_8 DVSS_69
VDDC_5 G8 M17
N8 DVSS_9 DVSS_70
VDDC_6 D9 N17
P8 DVSS_10 DVSS_71
VDDC_7 AA9 P17
R8 DVSS_11 DVSS_72
VDDC_8 G10 R17
AA8 DVSS_12 DVSS_73
D3.3V VDDC_9 A11 T17
H9 DVSS_13 DVSS_74
VDDC_10 L11 U17
H10 DVSS_14 DVSS_75
VDDC_11 M11 V17
H11 DVSS_15 DVSS_76
VDDC_12 N11 AA17
H12 DVSS_16 DVSS_77
VDDC_13 P11 AC19
C245 C255 C257 C261 C263 C264 C267 C289 C291 H13 DVSS_17 DVSS_78
4.7uF 1000pF 0.01uF 0.1uF 4.7uF 1000pF 0.01uF 0.1uF 10uF VDDC_14 R11 G18
5 H14
H15
VDDC_15
VDDC_16
T11
U11
DVSS_18
DVSS_19
DVSS_79
DVSS_80
L18
M18
H16 DVSS_20 DVSS_81
VDDC_17 V11 N18
H17 DVSS_21 DVSS_82
VDDC_18 D12 P18
H18 DVSS_22 DVSS_83
VDDC_19 G12 R18
H19 DVSS_23 DVSS_84
VDDC_20 L12 T18
D3.3V H21 DVSS_24 DVSS_85
VDDC_21 M12 U18
J21 DVSS_25 DVSS_86
VDDC_22 N12 V18
K21 DVSS_26 DVSS_87
VDDC_23 P12 D20
L21 DVSS_27 DVSS_88
VDDC_24 R12 G20
M21 DVSS_28 DVSS_89
C216 C268 C269 C270 C271 C292 C293 C294 VDDC_25 T12 H20
N21 DVSS_29 DVSS_90
0.1uF 1000pF 0.01uF 0.1uF 4.7uF 1000pF 0.01uF 0.1uF VDDC_26 U12 A21
P21 DVSS_30 DVSS_91
VDDC_27 V12 E21
R21 DVSS_31 DVSS_92
VDDC_28 L13 F21
T21 DVSS_32 DVSS_93
VDDC_29 M13 G21
A3.3V U21 DVSS_33 DVSS_94
VDDC_30 N13 E22
V21 DVSS_34 DVSS_95
VDDC_31 P13 F22
W21 DVSS_35 DVSS_96
R205 VDDC_32 R13 G22
Y21 DVSS_36 DVSS_97
D1.8V 20 VDDC_33 T13 H22
DVSS_37 DVSS_98
U13 J22
4 AH27
AGC_VDDO
V13
G14
DVSS_38
DVSS_39
DVSS_99
DVSS_100
K22
L22
D3.3V DVSS_40 DVSS_101
L14 M22
DVSS_41 DVSS_102
C247 C272 C275 C276 C278 C280 C297 C2003 M14 N22
C2004 AA12 DVSS_42 DVSS_103
0.1uF 0.1uF 0.1uF 0.1uF 4.7uF 4.7uF 4.7uF 33uF 0.1uF VDDO_1 N14 P22
AA13 DVSS_43 DVSS_104
VDDO_2 P14 R22
VDDO_3 R14 T22
VDDO_4 T14 U22
E28 DVSS_46 DVSS_107
VDDO_5 U14 V22
L28 DVSS_47 DVSS_108
VDDO_6 V14 W22
U28 DVSS_48 DVSS_109
VDDO_7 L15 Y22
AB28 DVSS_49 DVSS_110
VDDO_8 M15 AA22
D1.8V DVSS_50 DVSS_111
D1.8V N15 W23
DVSS_51 DVSS_112
P15 AB23
A9 DVSS_52 DVSS_113
DDRV_1 R15 F28
G9 DVSS_53 DVSS_114
DDRV_2 T15 M28
C248 C281 C282 C283 C284 C285 C2005 C2006 G11 DVSS_54 DVSS_115
1000pF 0.01uF 0.01uF 0.01uF 0.01uF DDRV_3 U15 T28
1000pF 1000pF 1000pF G13 DVSS_55 DVSS_116
DDRV_4 V15 AC28
A14 DVSS_56 DVSS_117
DDRV_5 A16
G15 DVSS_57
DDRV_6 G16
3 G17
A19
DDRV_7
DDRV_8
L16
M16
DVSS_58
DVSS_59
G19 DVSS_60
DDRV_9 N16
DVSS_61
D1.8V
C365 C364 C363 C357 C348 C320 C319 C318 C304

C356
0.1uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
16V 16V 16V 10V 16V 16V 16V 16V 16V 16V

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS BRAZIL DVR DV 2009.03.23
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
JANG.J.H BCM3549 POWER 13 15
A B C D E F G H I J
7
CONTROL IR & LED USB JACK & USB +5V Current Protection
D3.3V
+5V_ST +5.0V
BCM Tolerance
MLB-201209-0120P-N2
MLB-201209-0120P-N2
P701 R718 R721
USB_POWER_OUT_2 IC701 2.7K
12507WS-12L 2.7K L709
MIC2009YM6-TR
USB_5VST L710
USB_+5V
VOUT VIN
SCL 6 1
1
CDS3C05HDMI1
CDS3C05HDMI1
UCOM_SCL_3.3V 12:F6
ILIMIT GND C716
SDA 5 2 0.1uF
2 UCOM_SDA_3.3V
OPT OPT 12:F6 16V
C705 C707
6 3
GND D701 D702 1000pF
50V
1000pF
50V R716
FAULT/
4 3
ENABLE
USB_CTL1
130 10:D5
KEY1
4 KEY1 12:H3
L703
KEY2 BG2012B080TF R717
5 KEY2 USB_OCD1 10:D4
12:H3
L704 47
L705
5V_ST BG2012B080TF CB3216PA501E USB_POWER_OUT_2
+5V_ST
6
Make this trace minimum 12 mil
C704 C706 KJA-UB-4-0004
GND C708 +3.3V_ST
7 0.1uF 0.1uF JK702 L708
ZD701 ZD703 0.1uF
R710
10K
R712 BLM18PG121SN1D
WARM_ST
1
0
8
USB DOWN STREAM

C
R711
IR 0
2
Q702 B USB_DM2 10:D4
9 IR C710 LED_WARM_STBY C714
2SC3052 C715
12:D4;A3 0.1uF OPT 100uF 100uF
R715
120K
OPT L701
OPT
16V OPT E 16V
GND C702
3
ZD702 BG2012B080TF USB_DP2 10:D4
10
100pF
+3.3V_ST
5 3.3V_ST
4
11 +3.3V_ST Not enough space
R707
D703
10K
D704
5
L702 CDS3C05GTA
5.6V CDS3C05GTA
POWER_ON CB3216PA501E OPT OPT
12 OPT 5.6V
RL_ON OPT
C709 0 0
0.1uF C R708 R714
13
C701 C703 16V
0.1uF 1000pF Q701 B
50V 2SC3052 LED_POWER_ON
GND
R709 R713
E 4.7K 0
D3.3V
RS232_SWITCHING Blue Tooth
CB3216PA501E
L707
11
JP712
10
R702
0 C713
10uF
RS232_BYPASS +5V_ST 9 16V
IC702 JP711 R722
MC14053BDR2G 27
USB_DM1 10:D4
8
0ISTL00024A D705
CDS3C05GTA
L706 5.6V
3 BCM_RX
R701
0 Y1
1 16
VDD
MLB-201209-0120P-N2 7 OPT JP713
R723
27
9:G6 C712 D706 USB_DP1 10:D4
6
Y0 Y A3 C711 CDS3C05GTA
2 15 RS232C_RxD 47uF 5.6V
UCOM_RX
12:D4 16V 0.1uF 16V OPT
5 JP715
Z1 X RS232_BYPASS
3 14 R720
RS232C_TxD A3 0
R705
0
BLUETOOTH_RESET
R703 4
Z X1 0
4 13 BCM_TX 9:G6
+5.0V 3 JP716
Z0 X0
5 12 R719
UCOM_TX 12:D4 0
VREG_CTRL
R706 2
INH A 4.7K
6 11
R_RS232_SWITCHING 1
VEE B
7 10 R704
100K
VSS C 12507WR-10L
8 9
P702

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR DO.J.G
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. CONTROL IR/BT/USB 14 15
A B C D E F G H I J
7
D3.3V
TU_+5.0V
R5015
4.7K
L5000
OPT
LGIT
C5005-*1
0.1uF
CTR 50V 0 RF_SWITCH
1 LGIT RF_SWITCH 3:T24
RF-GAIN_SW C5005 R5014
2 2200pF
16V C5002 50V 0 GAIN_SWITCH
B0[+5V]
3 22uF 0.1uF GAIN_SWITCH 3:T24 TU_+5.0V
C5000 50V TU101 R5013
VTU R50010 LGIT
4 LGIT LGIT VA1G5BF8005 C5007
RF_AGC 2200pF L5005
R50020 LGIT
LGIT 5 50V
B1[+5V] RF_SW
6 1
C5012 C5014C5016
TU102 NC_1 GAIN_SW
7 2
TDYR-H071F SIF BB
D2.5V 0.01uF 22uF 0.1uF
8 3
Place close to Pin
6 9
VIDEO_OUT
4
B1
L5002 D3.3V
NC_2 AFT 0
10 5 L5004
NC_3 SIF R5004 C5010 C5011
11 6 0.1uF
R50000 22uF
AIF VIDEO C5015 C5017
12 7 0.1uF
22uF
B2[2.5V] LGIT B2
13 8
D1.2V A1[RD]
B3[3.3V] B3 C R5025 330
14 9 A2[GN]
B4[1.2V] B4 L5006
15 10 LD5000
SAM2333
RESET[SYRSTN] RESET 22 R5005 C5020
16 11 C5018
TUNER_RESETb 3:T26 0.1uF
SDA SDA R5006 22uF D3.3V
17 12 22 SAM2333
SDA0_3.3V 3:T26
LD5001
SCL SCL 22 R5007
18 13 SCL0_3.3V R5023
3:T26 A1[RD]
RSEORF RSEORF 1K C
19 14 A2[GN]
SBYTE SBYTE 22 R5008
20 15 TU_SYNC 3:T27
SPBVAL SPBVAL 0 TU_+5.0V
21 16
R5012
5 22
SRDT
SRCK
17
SRDT
SRCK
22
22
R5009
R5010
TU_SDATA 3:T27
L5007
23 18 TU_SCLK 3:T27
24 C5001 C5003
22pF 22pF 19
R5020
R5024
50V 50V
SHIELD SHIELD
12K
470
LGIT LGIT C5021
SHARP R5022 0.01uF
0
TU_SIF 3:T25
OPT
C5019 E
0.01uF
2SA1530A-T112-1R
B Q5000
R5021
C
10K
16V
R5018
FI-C3216-103KJT
56
R5019
R5003
10uF C5009
OPT
OPT
TU_CVBS_IN 3:T25
L5001
4
OPT
56
82
C5004 GND
91pF
50V OPT
3
+5V
L5009
MLB-201209-0120P-N2
GND2
D3.3V
IC5001
KIA78R05F OPT
C5031 C5033 C5035
0.1uF 4.7uF 100uF
6 16V 10V 16V
TU_+5.0V
R5026
100
1 2 3 4 5
L5010
VIN
VC
VOUT
NC
GND1
MLB-201209-0120P-N2
+12V
C5032 C5034 C5036
IC5002 0.1uF 4.7uF 100uF
2 AS7809DTRE1
L5008
MLB-201209-0120P-N2
16V 10V
OPT
16V
INPUT 1 3 OUTPUT
2
GND
C5022 C5023 C5029 C5030
C5026 C5027 C5028
0.1uF 100uF C5024 C5025 0.33uF 0.1uF 47uF 0.1uF 0.01uF
16V 16V 0.1uF 100uF 16V
50V 50V 16V 50V 50V
16V

ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR DO.J.G
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. TUNER 15 15

LCD TV: Service Manual

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LCD TV: Service Manual

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Internal Use Only

North/Latin America http://aic.lgservice.com

MODEL : 32SL80YD 42SL80YD-SA

P/NO : MFL61862414 (0911-REV01) Printed in Korea

PRODUCT SAFETY ..................................................................................3

ADJUSTMENT INSTRUCTION ...............................................................14

TROUBLE SHOOTING ............................................................................17

EXPLODED VIEW .................................................................................. 59

SVC. SHEET ...............................................................................................

IMPORTANT SAFETY NOTICE

General Guidance Leakage Current Hot Check (See below Figure)

always perform an AC leakage current check on the exposed

1. Application range 3. Test method

1) Temperature : 25±5ºC (77±9ºF), CST : 40±5ºC

6. Component Input (Y, CB/PB, CR/PR)

** RGB PC Monitor Range Limits

8. HDMI Input (PC/DTV)

** HDMI Monitor Range Limits

No. Item Con tent Unit Remark

No. Item Con tent Unit Remark

No. Item Con tent Unit Remark

No. Item Con tent Unit Remark

1) Because this is not a hot chassis, it is not necessary to use

* Notice: if you maintain one picture over 20 minutes

3.1 PCB Assembly adjustment

3.2 Set Assembly Adjustment

Order Command Set response

See ADC Adjustment RS232C Protocol_Ver1.0

* If you want more information then see the below Adjustment

5.1 Manual Adjust Component 480i/1080p

O Summary : Adjustment component 480i/1080i and RGB

5.2 EDID (The Extended Display

<Pic.4 Adjustment pattern : 480i / 1080p 60Hz Pattern > O Summary

• EDID data for LJ91D Chassis (Model name = LG TV)

See Workig Guide of you want more information about EDID

• Using HDMI input

wb 00 00 White Balance adjustment start.

• "wb 00 00": Start Auto-adjustment of white balance.

5.4 EYE-Q Function check.

1uF C1122 1uF

470K C1136 R1169

100pF 50V DSUB_DET

27pF 50V BG1608B121F RGB-BEAD

50V 3:T22 PEJ027-01

1uF R1116 100pF 25V

1uF R1117 SHIELD_PLATE

C1106 3:T18 100 R1168 7

0.1uF C1- 3 14 DOUT1

47pF +5V JST1223-001 25V V- DIN1

470K G4;3:T12 R1154 R1160

ZD1145 C1129 0 100K

2 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

C515 C520 C522

+1.8V_AMP DVSS_1 PGND2A_1 DA-8580

6 1000pF 2S 2F 50V 0.1uF 4.7K R529

C504 1000pF C534 1S 1F

R503 AGND_PLL PVDD2B_2 50V 3.3

MCLK SDATA WCK BCK TP is necessory

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

10K must be placed with pin#8,#10 as close as possible.

12:A3;A6;C4;F7;G7;I2;14:B2 R819 AGND EN

Vout = (1+R2/R1)*1.25 FB COMP

S2 D2_2 3.3 C851 D2.5V A2.5V SC4215ISTRT