Vlsi Design

VLSI Design
Course File
Course file contents
1. Cover Page
2. Syllabus copy
3. Vision of the Department
4. Mission of the Department
5. PEOs and POs
6. Course objectives and outcomes
7. Brief Notes
8. Perquisites, If any
9. Instructional Learning Outcomes
10.Course mapping with PEOs and POs
11.Class Time Table
12.Individual Time Table
13.Lecture Schedule with Methodology being used
14.Detailed notes
15.Additional topics
16.University previous Question papers
17.Question Bank
18.Assignment topics
19.Unit wise bits
20.Tutorial class sheets
21.Known gaps
22.Discussion Topics
23.References, Journals, websites and E-links
24.Quality Control Sheets
a. Course end survey
b. Teaching Evaluation
25.Student List
26. Group-Wise students list for discussion topics
GEETHANJALI COLLEGE OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF Electrical and Electronics Engineering
(Name of the Subject / Lab Course) :VLSI Design
(JNTU CODE -- A60432) Programme : UG
Branch: ECE Version No : 01

Year: 3rd Updated on :26/11/2015
Semester: II , No.of pages :95
Classification status (Unrestricted / Restricted )

Distribution List :
Prepared by : 1) Name : G. Sree Lakshmi 1) Name :K.V.S.Nagaraju

2) Sign : 2) Sign :
3) Design : Assoc.professor 3) Design :Assistant Professor
4) Date : 26/11/2015 4) Date : 26/11/2015
Verified by : 1) Name : * For Q.C Only.
2) Sign : 1) Name :
3) Design : 2) Sign :
4) Date : 3) Design :
4) Date :
Approved by : (HOD ) 1) Name :
2) Sign :
3) Date :
2. JNTU Syllabus:
INTRODUCTION : Introduction to IC Technology – MOS, PMOS,

NMOS, CMOS & BiCMOS.
UNIT I BASIC ELECTRICAL PROPERTIES : Basic Electrical Properties of
MOS and BiCMOS Circuits: Ids-Vds relationships, MOS transistor
threshold Voltage, gm, gds, figure of merit ; Pass transistor, NMOS Inverter,
Various pull ups, CMOS Inverter analysis and design, Bi-CMOS Inverters.
VLSI CIRCUIT DESIGN PROCESSES: VLSI Design Flow, MOS

Layers, Stick Diagrams, Design Rules and Layout, 2 _m CMOS Design
UNIT II rules for wires, Contacts and Transistors Layout Diagrams for NMOS and
CMOS Inverters and Gates, Scaling of MOS circuits, Limitations of
Scaling.
GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch
logic, Alternate gate circuits, Basic circuit concepts, Sheet Resistance RS
UNIT III and its concept to MOS, Area Capacitance Units, Calculations Delays,
Driving large Capacitive Loads, Wiring Capacitances, Fan-in and fan-out,
Choice of layers
DATA PATH SUBSYSTEMS: Subsystem Design, Shifters, Adders,
UNIT IV ALUs, Multipliers, Parity generators, Comparators, Zero/One Detectors,
Counters.
Array Subsystems: SRAM, DRAM, ROM, Serial Access Memories,
Semiconductor Integrated Circuit Design: PLAs ,FPGAs, CPLDs,
Standard cells, Programmable Array Logic Design Approach, Parameters
UNIT V
influencing low power design
CMOS TESTING : CMOS Testing, Need for testing, Test Principles,
Design Strategies for test, Chip level Test Techniques.
Books / Material
Text Books
Essentials of VLSI circuits and systems – Kamran Eshraghian, Eshraghian
Text-1.
Dougles and A. Pucknell, PHI,2005 Edition.
Principles of CMOS VLSI Design - Weste and Eshraghian, Pearson Education,
Text-2.
1999.
Suggested / Reference Books

Ref-1. Modern VLSI Design - Wayne Wolf, Pearson Education, 3rd Edition, 1997.
Ref-2. VLSI Technology – S.M. SZE, 2nd Edition, TMH, 2003.

Ref-3. Digital Integrated Circuits - John M. Rabaey, PHI, EEE, 1997.
Web Sites
a. www.cmosedu.com
b. www.wikkipedia.com
c. www.btechadda.com
d. www.wikibooks.org
* For the topics Internal & external Circlips, Gaskets and seals (stationary and rotary)
3. Vision of the Department
To impart quality technical education in Electronics and Communication Engineering
emphasizing analysis, design/synthesis and evaluation of hardware/embedded software
using various Electronic Design Automation (EDA) tools with accent on creativity,
innovation and research thereby producing competent engineers who can meet global
challenges with societal commitment.
4. Mission of the Department

i. To impart quality education in fundamentals of basic sciences, mathematics,
electronics and communication engineering through innovative teaching-learning
processes.
ii. To facilitate Graduates define, design, and solve engineering problems in the field of
Electronics and Communication Engineering using various Electronic Design
Automation (EDA) tools.
iii. To encourage research culture among faculty and students thereby facilitating them to
be creative and innovative through constant interaction with R & D organizations and
Industry.
iv. To inculcate teamwork, imbibe leadership qualities, professional ethics and social
responsibilities in students and faculty.
5. Program Educational Objectives of B. Tech (ECE) Program :
I. To prepare students with excellent comprehension of basic sciences, mathematics

and engineering subjects facilitating them to gain employment or pursue
postgraduate studies with an appreciation for lifelong learning.
II. To train students with problem solving capabilities such as analysis and design
with adequate practical skills wherein they demonstrate creativity and innovation
that would enable them to develop state of the art equipment and technologies of
multidisciplinary nature for societal development.
III. To inculcate positive attitude, professional ethics, effective communication and
interpersonal skills which would facilitate them to succeed in the chosen
profession exhibiting creativity and innovation through research and development
both as team member and as well as leader.
5. Program Outcomes of B.Tech ECE Program:
1. An ability to apply knowledge of Mathematics, Science, and Engineering to solve

complex engineering problems of Electronics and Communication Engineering
systems.
2. An ability to model, simulate and design Electronics and Communication
Engineering systems, conduct experiments, as well as analyze and interpret data
and prepare a report with conclusions.
3. An ability to design an Electronics and Communication Engineering system,
component, or process to meet desired needs within the realistic constraints such
as economic, environmental, social, political, ethical, health and safety,
manufacturability and sustainability.
4. An ability to function on multidisciplinary teams involving interpersonal skills.
5. An ability to identify, formulate and solve engineering problems of
multidisciplinary nature.
6. An understanding of professional and ethical responsibilities involved in the
practice of Electronics and Communication Engineering profession.
7. An ability to communicate effectively with a range of audience on complex
engineering problems of multidisciplinary nature both in oral and written form.
8. The broad education necessary to understand the impact of engineering solutions
in a global, economic, environmental and societal context.
9. A recognition of the need for, and an ability to engage in life-long learning and
acquire the capability for the same.
10. A knowledge of contemporary issues involved in the practice of Electronics and
Communication Engineering profession
11. An ability to use the techniques, skills and modern engineering tools necessary for
engineering practice.
12. An ability to use modern Electronic Design Automation (EDA) tools, software
and electronic equipment to analyze, synthesize and evaluate Electronics and
Communication Engineering systems for multidisciplinary tasks.
6. Course Objective and Outcomes
Course Objectives:
The students should have ability to:
 To understand the steps involved in IC fabrication.

 Ability to demonstrate the fundamentals of IC Technology such as various MOS
fabrication technologies.
 To get the knowledge about basic electrical properties of MOS &BIOS circuits.
 To understand VLSI circuit design processes representations of stick diagram
&layout diagram.
 To develop the gate level design &delays.
 To know different combinational & sequential circuits to design the subsystems
like ALUs, shifters, adders etc.
 To understand the importance of CPLDs and FPGAs for implementing the variety logic
functions.
Course outcomes:
CO 1: Demonstrate the Fabrication of IC using cadence tools.
CO2: Calculate compute electrical properties of MOS circuits.
CO3: Design various gates, adders, Multipliers and Memories using stick diagrams,
layouts.
CO4: Apply design rules to get Layout of IC.
CO5: Demonstrate semiconductor IC design such as PLA’s, PAL, FPGA, CPLDs.
CO6: Design various forms of memories.
CO7: Implement Subsystems with CMOS Technology.
CO8: Design a Logic Circuit with MOS Transistors.
CO9: Demonstrate VHDL synthesis, simulation, design captures tools, design
verification tools.
CO10: Demonstrate differential strategies for testing of IC’s and CMOS testing.
7. Brief note on Important Topics
In this course, we will study the fundamental structures of VLSI Systems at

the lowest levels of system abstraction, namely those associated with the direct
application of VLSI devices to particular problems of interest. At its most basic
level, VLSI design is concerned with the set of principles governing MOS (metal
oxide semiconductor) devices and their behaviours. We start by looking at the
CMOS transistors (n-channel and p-channel) and the ways in which we can use them
to create the most basic structure—the digital switch. We can proceed to build a
range of VLSI structures from this switch, including NAND/NOR gates,
Multiplexers, Latches and Registers. Continuing in a bottom-up fashion, we can
examine the structure of more complex VLSI design components (those at Digital
Logic and Register Transfer levels of abstraction) using these primitives.
While learning how to construct fundamental VLSI systems structures from

primitive circuit structures, we also will learn about the processes associated with
fabricating CMOS devices. Using CMOS as our technology, we examine the circuit
level design rules associated with circuit geometries and their layout according to a
set of process technology-specific design rules. We also look at factors affecting
design: capacitance, clocking, delay and power. These characteristics of a circuit
technology have a profound effect on the circuit's behaviour as we move to ever
smaller geometries. Circuit feature sizes and device densities.
Finally, we will develop a complete picture of the VLSI systems design flow,
starting at the Systems level, proceeding through the Register Transfer Level, to the
Digital Logic, Circuit and the Device Geometry levels—therefore having a complete
picture of the VLSI systems architecture and engineering design process and
associated design methods. We will use VHDL as the medium for describing our
design artefacts, and will likely use gate-level simulation, along with circuit layout
tools, as a means for exploring the knowledge in this domain.
Course Outline:
The course outline is as follows:
1. Introduction to CMOS Design. Rabaey et al., Chapter 1.
2. CMOS Device Fabrication Processes. Rabaey et al., Chapter 2.
3. CMOS Transistor Device Models. Rabaey et al., Chapter 3.
4. CMOS Interconnect Wire Models. Rabaey et al., Chapter 4.
5. CMOS Inverter Model. Rabaey et al., Chapter 5.
6. Combinational and Sequential Design. Rabaey et al., Chapters 6 & 7 (selected

sections).
7. Projects.
8. Prerequisites , If Any
MOSFET concepts, Basics of STLD
9. Instructional Learning Outcomes

UNIT I: Introduction of IC Technology
Students should be able to:

 Know about IC Technology.
 Get the idea on fabricating various MOS transistor on silicon wafer.
 Understand the difference between CMOS and BIPOLAR Technologies.
 Get the knowledge on advantage of BICOS Technology.
 Understand the basic electrical properties of MOS and BICMOS circuits.
 Get the knowledge about Ids-Vds relationships.
 Know the MOS transistor threshold Voltage, gm, gds, figure of merit.
 Know the NMOS Inverter, Various pull ups.
 Understand the CMOS Inverter analysis and design, Bi-CMOS Inverters.
UNIT II: VLSI circuit design processes

After the completion of the unit the students should be able to:
 Know the VLSI Design Flow.
 Understand the MOS layers.
 Draw the stick diagrams and layouts for NMOS and CMOS inverters and
gates.
 Get the knowledge about 2 _m CMOS Design rules for wires, Contacts.
 Know the Scaling of MOS circuits.
UNIT III: Gate level design
After the completion of the unit the student should be able to:
 Develop the Logic Gates and Other complex gates.
 Know about Sheet Resistance RS and its concept to MOS.
 Get the concept of driving large Capacitive Loads.
 Know the Wiring Capacitances.
 Understand the concept of Fan-in and fan-out.
UNIT IV: Data Path Subsystems and Array Subsystems
 Know the knowledge of Shifters, Adders.
 Develop the ALUs, Multipliers.
 Get the knowledge of Parity generators, Comparators.
 Design the various counters.
 Get the knowledge about Zero/One Detectors.
 Get the knowledge about memory architecture.
 Understand the concept of static RAM.
 Get the knowledge of DRAM.
 Know the knowledge of Serial access memory.
UNIT V: Programable Logic Devices and CMOS Testing
 Get the knowledge about PLA and PAL.
 Understand the concept of FPGA and its applications.
 Get the knowledge about CPLD and its applications.
 Know the knowledge about Standard cells.
 Get the knowledge of Programmable Array Logic Design Approach.
 Understand the needs of testing in VLSI design.
 How to apply test principles.
 Know the Chip level Test Techniques.
10. Mapping of Course outcomes to Program Outcomes:
1. An ability to apply knowledge of Mathematics, Science, and Engineering to
solve complex engineering problems of Electronics and Communication
Engineering systems.
2. An ability to model, simulate and design Electronics and Communication
Engineering systems, conduct experiments, as well as analyze and interpret
data and prepare a report with conclusions.
3. An ability to design an Electronics and Communication Engineering system,
component, or process to meet desired needs within the realistic constraints
such as economic, environmental, social, political, ethical, health and safety,
manufacturability and sustainability.
4. An ability to function on multidisciplinary teams involving interpersonal
skills.
5. An ability to identify, formulate and solve engineering problems of
multidisciplinary nature.
6. An understanding of professional and ethical responsibilities involved in the
practice of Electronics and Communication Engineering profession.
7. An ability to communicate effectively with a range of audience on complex
engineering problems of multidisciplinary nature both in oral and written
form.
8. The broad education necessary to understand the impact of engineering
solutions in a global, economic, environmental and societal context.
9. A recognition of the need for, and an ability to engage in life-long learning
and acquire the capability for the same.
10. A knowledge of contemporary issues involved in the practice of Electronics
and Communication Engineering profession
11. An ability to use the techniques, skills and modern engineering tools
necessary for engineering practice.
12. An ability to use modern Electronic Design Automation (EDA) tools,
software and electronic equipment to analyze, synthesize and evaluate
Electronics and Communication Engineering systems for multidisciplinary
tasks.
.
S.No. Course Outcome POs

1 Demonstrate the Fabrication of IC using PO2, PO3,PO8,PO11
cadence tools.
2 Calculate compute electrical properties of MOS PO1,PO2
circuits.
3 Design various gates, adders, Multipliers and PO4
Memories using stick diagrams, layouts.
4 Apply design rules to get Layout of IC. PO5
5 Demonstrate semiconductor IC design such as PO13

PLA’s, PAL, FPGA, CPLDs.
6 Design various forms of memories. PO3,PO4,PO12

7 Implement Subsystems with CMOS PO2,PO3,PO6
Technology.
8 Design a Logic Circuit with MOS Transistors. PO3,PO6,PO8
9 Demonstrate VHDL synthesis, simulation, PO11
design captures tools, design verification tools.
10 Demonstrate differential strategies for testing of PO3
IC’s and CMOS testing.
11. Class Time Table:
12. Individual Time Table
13.Lecture Shedule with methodology being used
GEETHANJALI COLLEGE OF ENGINEERING & TECHNOLOGY
CHEERYAL (V), KEESARA (M), RR District.
Department of Computer science and engineering

Year and Semester to Whom Subject is Offered: IV B.TECH-I Semester
Name of the Subject: VLSI DESIGN
Name of the Faculty: S.Vasu Krishna Designation: Assoc. prof
Department: ECE
Micro Plan:- FOR ECE - 4rd Year
13.1 Micro Plan:-
Subject: VLSI Design Name of the Faculty: G Sreelakshmi

Class: IV ECE-A
Lecture Shedule
Unit Regular / Teaching aids used

S. no DATE Topics to be covered Remarks
No Additional LCD/OHP/BB
1 1 Introduction to VLSI Regular BB
2 Introduction to IC Technology Regular BB
3 MOS Transistor, Enhancement and Depletion Regular BB/OHP
Mode
4 MOS Fabrication Process Regular BB/OHP
5 Fabrication Process :NMOS,PMOS Regular BB/OHP
6 Fabrication Process :CMOS Regular BB/OHP
7 Berkeley n-well Process ,Twin Tub Process Regular BB/OHP
8 Fabrication Process :BICMOS Regular BB/OHP
9 BICMOS Regular BB/OHP
Latch up susceptibility Missing BB
10 Oxidation, Lithography, Diffusion Regular BB
11 Ion implantation, Metallization, Encapsulation Regular BB
12 Probe testing, Integrated Resistors and Regular BB
Capacitors
13 CMOS Nanotecchnology Regular BB
14 Tutorial class on unit 1 -revision Regular BB
15 2 BASIC ELECTRICAL PROPERTIES : Basic Regular BB
Electrical Properties of MOS and BiCMOS
Circuits: Ids-Vds relationships
16 MOS transistor threshold Voltage Regular BB
17 gm, gds, figure of merit ?o; Pass transistor, Regular BB
NMOS Inverter
18 NMOS Inverter Regular BB
19 Various pull ups Regular BB
20 CMOS Inverter analysis and design Regular BB
21 Bi-CMOS Inverters Regular BB
22 Tutorial class on unit 2 -revision Regular

23 3 VLSI CIRCUIT DESIGN PROCESSES : Regular BB
VLSI Design Flow
24 MOS Layers, Stick Diagrams Regular BB
25 Stick Diagrams Regular BB
26 Design Rules and Layout Regular BB
27 2 nm CMOS Design rules for wires Regular BB
28 Contacts and Transistors Layout Diagrams for Regular BB
NMOS and CMOS Inverters and Gates
29 Scaling of MOS circuits Regular BB
30 Tutorial class on unit3 -revision Regular BB
31 4 GATE LEVEL DESIGN : Logic Gates and Regular BB
Other complex gates
32 Switch logic, Alternate gate circuits Regular BB

Gallium Arsenide Devices Additional BB
33 Time Delays Regular BB
34 Driving large Capacitive Loads, Wiring Regular BB
Capacitances, Fan-in and fan-out, Choice of
layers
36 5 SUBSYSTEM DESIGN : Subsystem Design, Regular BB
Shifters
37 Adders, ALUs Regular BB
38 Multipliers, Parity generators Regular BB
39 Comparators, Zero/One Detectors, Counters Regular BB
41 6 Array Subsystems :SRAM,DRAM Regular BB
42 ROM, Serial Access Memories Regular BB
Dynamic Register Element Additional BB
43 Content Addressable Memory Regular BB
45 7 SEMICONDUCTOR INTEGRATED Regular BB
CIRCUIT DESIGN : PLAs
46 FPGAs Regular BB
47 CPLDs Regular BB
48 Standard Cells, Programmable Array Logic Regular BB
System Partioning Missing Missing BB
49 Design Approach Regular BB
50 Parameters influencing low power design Regular BB
52 8 CMOS TESTING : CMOS Testing Regular BB

53 Need for testing Regular BB
54 Test Principles Regular BB
55 Design Strategies for test Regular BB
56 Chip level Test Techniques Regular BB/OHP
57 System-level Test Techniques Regular BB/OHP
58 Layout Design for improved Testability. Regular BB/OHP
and Tutorial class on unit8 -revision
59 Revision of previous papers Regular BB/OHP
Subject: VLSI Design Name of the Faculty: S Vasu Krishna
Class: IV ECE-B
Lecture Shedule

Mode
Capacitors
NMOS Inverter
VLSI Design Flow

Other complex gates

layers
Shifters
46 FPGAs Regular BB
47 CPLDs Regular BB
Subject: VLSI Design Name of the Faculty: M Krishna Chaitanya

Class: IV ECE-C
Lecture Shedule

Mode
Capacitors
NMOS Inverter

VLSI Design Flow

Other complex gates

layers
Shifters
46 FPGAs Regular BB
47 CPLDs Regular BB

13.2. Subject Contents

5.2. 1. Synopsis page for each period (62 pages)
5.2.2. Detailed Lecture notes containing:
1. ppts
2. ohp slides
3. subjective type questions(approximately 5 t0 8 in no)
4.objective type questions(approximately 20 to 30 in no)
5.Any simulations
13.3. Course Review (By the concerned Faculty):
(I)Aims
(II) Sample check
(III) End of the course report by the concerned faculty
GUIDELINES:
Distribution of periods :
No. of classes required to cover JNTU syllabus : 40
No. of classes required to cover Additional topics : 4
No. of classes required to cover Assignment tests (for every 2 units 1 test) : 4
No. of classes required to cover tutorials : 8
No. of classes required to cover Mid tests :
2
No of classes required to solve University : 4
Question papers -------
Total periods 6
14. Detailed notes
UNIT 1
INTRODUCTION
Synthetic detail of an integrated circuit through four layers of planarized copper

interconnect, down to the polysilicon (pink), wells (greyish), and substrate (green).
Integrated circuits were made possible by experimental discoveries which showed that
semiconductor devices could perform the functions of vacuum tubes and by mid-20th-
century technology advancements in semiconductor device fabrication. The integration of
large numbers of tiny transistors into a small chip was an enormous improvement over
the manual assembly of circuits using electronic components. The integrated circuit's
mass production capability, reliability, and building-block approach to circuit design
ensured the rapid adoption of standardized ICs in place of designs using discrete
transistors.
There are two main advantages of ICs over discrete circuits: cost and performance. Cost
is low because the chips, with all their components, are printed as a unit by
photolithography rather than being constructed one transistor at a time. Furthermore,
much less material is used to construct a packaged IC die than a discrete circuit.
Performance is high since the components switch quickly and consume little power
(compared to their discrete counterparts) because the components are small and
positioned close together. As of 2006, chip areas range from a few square millimeters to
around 350 mm2, with up to 1 million transistors per mm
IC Fabrication Process:
An integrated circuit consists of a single crystal chip of
silicon. Containing both active and passive elements, and their interconnection.
The basic structure of an IC consists of four layers of materials, such that:
1.Substrate
2.Epitaxialgrowth
3.Diffusion
4. Metallization
Substrate:
The p-type silicon bottom layer (6 mils thick) and serves where the
Integrated circuit is to be built known as Substrate.
Epitaxial growth:
The second n-type layer (25µm=1mil) where all active and

passive component are built, which is grown as a single crystal extension is called
Epitaxial growth.
Diffusion:
The third layer of IC fabrication is Diffusion process. Active and

passive component are made by diffusing p-type and n-type impurities. The
selective diffusion of impurities is accomplished by using SiO2 as a barrier.
Metallization:
Finally a fourth material (aluminum) Layer is added to supply the necessary
interconnection between components. It provided contact among the components Al is
used for metallization.
Diode Fabrication:
Transistor Fabrication:
CMOS:
Fabrication:
MOSFET Fabrication:
Monolithic IC:
Fabrication process:
IC characteristics / Elimination:
1. Typical value of Resistance 10Ω < R < 30 kΩ & Capacitance <30pf.

2. Poor tolerance typical value is 10% only.
3. High thermal co-efficient & voltage resistive.
4. No transfer & inductor can be fabricated.
5. Higher cost for small scale production.
BASIC ELECTRICAL PROPERTIES

The MOS transistor evolves from the use of a voltage on the gate to induce a charge in
the channel between source and drain, which may then be caused to move from source to
drain under the influence of an electric field created by voltage Vds applied between
drain and source. Since the charge induced is dependent on the gate to source voltage
then Ids is dependent on both Vgs and Vds.
polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.9)
p-type body
MOS structure looks like parallel plate capacitor while operating in inversion
– Gate – oxide – channel
Qchannel = CV
C = Cg = eoxWL/tox = CoxWL
V = Vgc – Vt = (Vgs – Vds/2) – Vt
Charge is carried by e-
Carrier velocity v proportional to lateral E-field between source and drain
v = mE m called mobility
E = Vds/L
Time for carrier to cross channel:
t = L /V
Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross
Qchannel
I ds  W
 = Cox
t
VL
 Cox Vgs  Vt  ds Vds
W
Loff near drain, When Vds
If Vgd < Vt, channel pinches 2 >Vdsat = Vgs – Vt
Now drain voltage no longer increases current
  V  V  VVds V

I    Vgs  V t  2 2 ds
V

dsat

ds gs t dsat

V  V 
2


gs t
2
 0 Vgs  Vt cutoff


I    V  V  ds V V  V
V
linear
Characteristics of nMOS transistor:
2.5
Vgs = 5
1.5 Vgs = 4
Ids (mA)
1
Vgs = 3
0.5
Vgs = 2
Vgs = 1
0
0 1 2 3 4 5
Vds
MOS Transistor threshold voltage:
The threshold voltage of a MOSFET is usually defined as the gate voltage where an
inversion layer forms at the interface between the insulating layer (oxide) and the
substrate (body) of the transistor. The purpose of the inversion layer's forming is to allow
the flow of electrons through the gate-source junction.
FIGURE OF MERIT:
A figure of merit is a quantity used to characterize the performance of a device, system

or method, relative to its alternatives. In engineering, figures of merit are often defined
for particular materials or devices in order to determine their relative utility for an
application. In commerce, such figures are often used as a marketing tool to convince
consumers to choose a particular brand.
CMOS INVERTER:
This is a CMOS inverter, a logic gate which converts a high input to low and low to high.
Click on the input at left to change its state. When the input is high, the n-MOSFET on
the bottom switches on, pulling the output to ground. The p-MOSFET on top switches
off. When the input is low, the gate-source voltage on the n-MOSFET is below its
threshold, so it switches off, and the p-MOSFET switches on to pull the output high
Inverting Amplifier :
Push-pull inverter
Large signal analysis
VTC and Inversion voltage.
Compare with the earlier VTC.
Small signal analysis
Gain = Vout/Vin= - (gm1+ gm2)/(gds1 + gds2)
Rout = Vout/Iout|Vin=0  1/(gds1 + gds2)
CMOS Inverter analysis :
Inverter Threshold (midpoint, inversion) Voltage(VI) :
point of intersection of VTC and unity gain line.
Inverter design 1: DC Design :

 To design the value of VI for a particular VTC
Compute the design parameter from the expression of VI.
Calculate the value of VI for inverter having same aspect ratio (W/L)n = (W/L)p
Inverter design 2: Transient Design :

The transient response should be symmetrical with tLH=tHL.
but once (W/L)n and (W/L)p are decided the time constants are also determined.
DC design sets the general shape of the switching waveforms
High performance design
To achieve smaller time delays in digital signal path
Cout= Cint + CL,
Cint : internal MOSFET capacitance and is dependent on
device aspect ratio.
CL: external load capacitance due to large no of fan-out.
Large aspect ratio (W/L) is to be chosen for design to achieve fast charging and discharging
of Cout..
Trans conductance:
Transconductance, also known as mutual conductance, is a property of certain

electronic components. Conductance is the reciprocal of resistance; transconductance,
meanwhile, is the ratio of the current change at the output port to the voltage change at
the input port. It is written as gm. For direct current, transconductance is defined as
follows:
PASS TRANSISTOR:
In electronics, pass transistor logic (PTL) describes several logic families used in the
design of integrated circuits. It reduces the count of transistors used to make different
logic gates, by eliminating redundant transistors. Transistors are used as switches to pass
logic levels between nodes of a circuit, instead of as switches connected directly to
supply voltages. This reduces the number of active devices, but has the disadvantage that
output levels can be no higher than the input level. Each transistor in series has a lower
voltage at its output than at its input. If several devices are chained in series in a logic
path, a conventionally-constructed gate may be required to restore the signal voltage to
the full value. By contrast, conventional CMOS logic always switches transistors to the
power supply rails, so logic voltage levels in a sequential chain do not decrease.
BICMOS INVERTER:
BiCMOS is an evolved semiconductor technology that integrates two formerly separate

semiconductor technologies - those of the analog bipolar junction transistor and the
digital CMOS transistor - in a single integrated circuit device.
Two bipolar transistors (T3 and T4), one nMOS and one pMOS transistor (both
enhancement-type devices, OFF at Vin=0V)
The MOS switches perform the logic function & bipolar transistors drive output loads
Vdd
Vin T2
T4
Vout
T1
T3
CL
UNIT 2
VLSI CIRCIUT DESIGN PROCESSES
MOS design is aimed at specification into masks for processing silicon to meet the
specification .MOS circuits are formed on four basic layers –n-diffusion, p-diffusion,
polysilicon and metal, which are isolated from one another by thick or thin(thinox)silicon
dioxide insulating layers. The thin oxide (thinox) mask includes n=diffusion, p-diffusion
and transistor channels.
STICK DIAGRAM:
Stick diagrams are used yo convey the information through the use of a color code .the
below table shows the color code
Metal
poly
ndiff
pdiff
• Allow translation of circuits (usually in stick diagram or symbolic form) into actual
geometry in silicon
• Interface between circuit designer and fabrication engineer
• Compromise
– designer - tighter, smaller
– fabricator - controllable, reproducible
Lambda Based Design Rules :

Design rules based on single parameter, λ
• Simple for the designer
• Wide acceptance
• Provide feature size independent way of setting out mask
• If design rules are obeyed, masks will produce working circuits
• Minimum feature size is defined as 2 λ
• Used to preserve topological features on a chip
• Prevents shorting, opens, contacts from slipping out of area to be contacted
Wiring:
wiring is the space required for a wire

4  width, 4  spacing from neighbor = 8  pitch
Transistors also consume one wiring track
Design Rules :
• Manufacturing processes have inherent limitations in accuracy and repeatability

• Design rules specify geometry of masks that provide reasonable yield
• Design rules are determined by experience
Nmos stick diagram:
Layout of CMOS NAND and NOR Gates:
The mask layout designs of CMOS NAND and NOR gates follow the general principles
examined earlier for the CMOS inverter layout. Figure 3.7 shows the sample layouts of a
two- input NOR gate and a
two- input NAND gate,
using single-layer
polysilicon and
single- layer meta.
CMOS Layout Design Rules:
The layout designer must follow these rules in order to guarantee a certain yield for the
finished product, i.e., a certain ratio of acceptable chips out of a fabrication batch. A
design which violates some of the layout design rules may still result in a functional chip,
but the yield is expected to be lower because of random process variations.The design
rules below are given in terms of scaleable lambda-rules. Note that while the concept of
scaleable design rules is very convenient for defining a technology-independent mask
layout and for memorizing the basic constraints, most of the rules do not scale linearly,
especially for sub-micron technologies. This fact is illustrated in the right column, where
a representative rule set is given in real micron dimensions. A simple comparison with
the lambda- based rules shows that there are significant differences. Therefore, lambda-
based design rules are simply not useful for sub-micron CMOS technologies.
CMOS Design Rules:

Figure 2.11 defines the design rules for a CMOS process using pictures. Arrows between
objects denote a minimum spacing, and arrows showing the size of an object denote a
minimum width. Rule 3.1, for example, is the minimum width of poly (2 l ). Each of the
rule numbers may have different values for different manufacturers—there are no
standards for design rules.
UNIT 3
GATE LEVEL DESIGN
Logic gate is an idealized or physical device implementing a Boolean function, that is, it
performs a logical operation on one or more logic inputs and produces a single logic
output. Depending on the context, the term may refer to an ideal logic gate, one that has
for instance zero rise time and unlimited fan-out, or it may refer to a non-ideal physical
device.
Switch logic:
Switch logic is based on the pass transistor or on transmission gates. This approach is
fast for small arrays and takes no static current from the supply rails. Thus, power
dissipation of such arrays is small since current inly fows on switching.
(figure shows transmission gates)
Pass transistors and Transmission gates:

Switches and switch logic ay be formed from simple n or p-pass transistors or from
transmission gates comprising an n-pass and a p-pass transistor in parallel the reason for
adopting the apparent complexity of the transmission gate, rather than using a simple n-
switch or p-switch in most CMOS applications, is to eliminate the undesirable threshold
voltage effects which give rise to the loss of logic levels in pass transistors
Other forms of CMOS logic:
Clocked CMOS Logic (C2MOS):
Clocked CMOS logic has been used for very low power CMOS and/or for minimizing
hot electron effect problems in N-FET devices .Clocking transistors allow valid logic
output only when clk is high. Clocking transistors may be at output end of logic trees
(maximum performance) or at power supply end of logic trees (maximum protection
from hot electrons)
Pseudo-noms logic:
Using a PMOS transistor simply as a pull-up device for an n-block is called pseudo-
NMOS logic. Note, that this type of logic is no longer ratio-less, i.e., the transistor
widths must be chosen properly, i.e., The pull-up transistor must be chosen wide enough
to conduct a multiple of the n-block's leakage and narrow enough so that the n-block can
still pull down the output safely.
Dynamic CMOS logic:

The actual logic is implemented in the inherently faster nmos logic, a p-transistor is used
for the non-time-critical precharging of the output line so that the output capacitance is
charged to Vdd during the of period of the clock signal.
Domino CMOS logic
Domino logic is a CMOS-based evolution of the dynamic logic techniques which were
based on either PMOS or NMOS transistors. It allows a rail-to-rail logic swing. It was
developed to speed up circuits.
In Dynamic Logic, a problem arises when cascading one gate to the next. The precharge
"1" state of the first gate may cause the second gate to discharge prematurely, before the
first gate has reached its correct state. This uses up the "precharge" of the second gate,
which cannot be restored until the next clock cycle, so there is no recovery from this
error.
Sheet Resistance:
• Resistance of a square slab of material

• RAB = ρL/A
• => R = ρL/t*W
• Let L = W (square slab)
• => RAB = ρ/t = Rs ohm / square
Typical sheet resistance values for materials are very well

characterized
Layer Rs (Ohm / Sq
Aluminium 0.03
N Diffusion 10 – 50
Silicide 2–4
Polysilicon 15 - 100
N-transistor Channel 104
P-transistor Channel 2.5 x 104

N-type Minimum Feature Device:
R = 1sq x Rs = Rs = 104 Ώ
2λ
Capacitance:
Standard unit for a technology node is the gate - channel capacitance of the minimum sized
transistor (2λ x 2λ), given as •Cg .This is a ‘technology specific’ value.
Delay Unit:
• For a feature size square gate, τ = Rs x •Cg

• i.e. for 5µm technology, τ = 104 ohm/sq x 0.01pF = 0.1ns
• Because of effects of parasitic which we have not considered in our model, delay is
typically of the order of 0.2 - 0.3 ns
• Note that τ is very similar to channel transit time τsd .
CMOS Inverter Delay:
• Pull-down delay = Rpd x 2 •Cg

• Pull-up delay = Rpu x 2•Cg
• Asymmetry in rise and fall due to resistance difference between pull-up and pull-
down (factor of 2.5) (due to mobilities of carriers)
• Delay through a pair of inverters is 2 τ (fall time) + 5 τ (rise time)
• Delay through a pair of CMOS inverters is therefore 7 τ.
CMOS Inverter Rise and Fall Time Estimation:
• Tf ~ 3CL / βVDD
• Τr ~ 3CL / βVDD
• (Derivations for the above are in Pucknell and Eshraghian Pages 105 - 107)
• So, τ r/ τf = βn/βp
• Given that (due to motilities) βn = 2.5 βp, rise time is slower by a factor of 2.5 when
using minimum dimensions of n and p transistors.
Super Buffers:
The symmetry of the conventional inverter is clearly undesirable, and gives rise to significant
delay problems when an inverter is used to drive more significant capacitive loads. Other
NMOS arrangements such as those based on the native transistor, and known as native super
buffers, may be used.
Unit 4:
DATA PATH SUBSYSTEMS
Large systems are composed of sub-systems, known as Leaf-Cell .The most basic leaf cell is
the common logic gate (inverter, and, ..Etc). Structured Design-High regularity-Leaf cells
replicated many times and interconnected to form the system. Logical and systematic
approach to VLSI design is essential.
SHIFTER:
A Shifter is most widely used for arithmetic operations. usually shifting is equivalent to
multiplication by powers of two. Shifting is required during floating-point arithmetic. The
shit register is simplest shifters that can shift by one position per clock cycle.
BARREL SHIFTER:
Barrel shifter produces n output bits and accepts 2n data bits , n control signals . The Barrel
shifter shifts by transmitting a n-bits slice of the 2n data bits to the output.
Adders
The adder is probably the most studied digital circuit. There are a great many ways to
perform binary addition, each with its own area/delay trade-offs. A great many tricks
have been used to speed up addition: encoding, replication of common factors and
precharging are just some of them. The origins of some of these methods are lost in the
mists of antiquity. Since advanced circuits are used in conjunction with advanced logic,
we need to study some higher-level addition methods before covering circuits for
addition.
Serial adder:
Serial adder may require many clock cycles to add two n-bit numbers, but with a very
short cycle time. Usually, they can work on nibbles or on bytes. The most extreme form
of the serial adder is a bit serial adder. When current data bits are the least significant bits
of the addends then a n LSB signal is high.
The addends appear LSB first and can be of arbitrary length the end of a pair of numbers
is signaled by the LSB bit for the next pair.
CARRY SELECT ADDER:
It comprises two versions of the
addition whose carry –ins are
different, then selects the right
one.
ALU:
An ALU is a Arithmetic Logic Unit that requires Arithmetic operations and Boolean
operations. Basically arithmetic operations are addition and subtraction. one may either
multiplex between an adder and a Boolean unit or merge the Boolean unit into the adder as in
tha classic transistor-transistor logic.
MULTIPLIERS:
The above figure shown is booth recoded multiplier. The multiplier is divided into two parts
namely, Both-array and carry propagate adder (CPA). By ascending the 16-bit inputs, the
booth array feeds the result of the multiplier is divided by the floor plan according hierarchy
using an array block and a CPA block.
This array section of multiplier consists of 8 ranks of adders each 17 -bits wide. The
schematic which can be used to represent the first rank and remaining ranks are different. A
Booth decode cell which observes 3-bits of the multiplier(MIER) and procedures the control
signals used in the array adders, can be used by both the above ranks.
A Booth multiplier for multiplying a first number with a second number to produce product
thtat has an array of array cells arranged in a plurality of rows of adder cells and is provided
with input circuitry that reduces the power consumption of the multipliers. This input
circuitry includes a plurality of Booth recoding logic cells that control signals to mulipilexers
in the adder cells in the array. the below example shows the booth recoded multiplier.
0 0 1 0 1 1
0 1 0 0 1 1
0 0 1 0 1 1
0 0 1 0 1 1
0 0 0 0 0 0
0 0 0 0 0 0
0 0 1 0 1 1
0 0 1 1 0 1 0 0 0 1
ARRAY MULTIPLIERS:
Array multipliers is a structure well suited to VLSI implementation .figure shows the
structure of an array multiplier for unsigned numbers. When multiplying the multiplicand and
multiplier by hand, partial products are formed in rows and accumulate in columns, with
partial products shifted by the appropriate amount. In layout, the a bits generally would be
distributed with horizontal wires since each row exactly one a-bits
PARITY GENERATORS:
Parity generators is a function related to binary
addition .Parity generator detects whether the
number of ones in an input word is even or odd. Parity
generator is most widely used to generate the parity
of 16-bits or 32-bit word.
COMPARATOR:
The magnitude of two binary numbers is compared by a magnitude comparator. Basically a
comparator is build with an adder and an inverter.
A<B or A>B may be generated by logical combinations of these signals. Whenever quality
comparisons requires, XNOR gates and AND gates and all that is required.
DYNAMIC RAM:
Dynamic random-access memory (DRAM) is a type of random-access memory that
stores each bit of data in a separate capacitor within an integrated circuit. The capacitor
can be either charged or discharged; these two states are taken to represent the two values
of a bit, conventionally called 0 and 1. Since capacitors leak charge, the information
eventually fades unless the capacitor charge is refreshed periodically. Because of this
refresh requirement, it is a dynamic memory as opposed to SRAM and other static
memory.
STATIC RAM:
Static random-access memory (SRAM) is a type of semiconductor memory where the

word static indicates that, unlike dynamic RAM (DRAM), it does not need to be
periodically refreshed, as SRAM uses bistable latching circuitry to store each bit.
Unit 5:Programmable logic devices

A programmable logic device or PLD is an electronic component used to build
reconfigurable digital circuits. Unlike a logic gate, which has a fixed function, a PLD has
an undefined function at the time of manufacture. Before the PLD can be used in a circuit
it must be programmed, that is, reconfigured.
PLA s:
Combinational circuit elements are an important part of any digital design. Three
common methods of implementing a combinational block are random logic, read-only
memory (ROM), and programmable logic array (PLA). In random-logic designs, the
logic description of the circuit is directly translated into hardware structures such as AND
and OR gates. The difficulty in this method is that the placement and interconnection cost
is high. In a large system, this cost could be prohibitive. The ROM is useful for tabular
data that has little regularity, but it is very wasteful of space for data that could be
algorithmically derived. The PLA combines features of both other methods by allowing
the designer to realize combinational design with programming taps on a logic array.
The PLA is made up of an AND plane and an OR plane. The AND plane produces product
terms of input variables selected by the programming taps and the OR plane produces the
sums of these product terms selected by a different set of programming taps. The symbolic
representation of the places where the programming taps are placed is known as the
personality matrix of the PLA. Figure 4.1 shows the generic structure of a PLA that
programs these logic functions:
PLA s are popular because their generation can be automated, which frees the designer
from spending valuable time creating random-logic gates. Since the PLA generator fixes
the physical structure of the PLA, there arises the problem of accommodating the
designer's special requirements, if any. The first requirement would be to reduce the area
occupied by the PLA. Usually the personality matrix is so sparse that a straightforward
mapping of the matrix to the silicon will result in wasted silicon area. Instead, the PLA is
folded to reduce the area required for the physical implementation. Instead of having one
AND plane and one OR plane, the PLA can be split into many more AND and OR
planes. Also, the input and output columns can be moved and folded such that there are
two to a column instead of the usual one. The rows can be similarly moved and folded.
Gate-Arrays:
The gate-array is a popular technique used to design IC chips. Like the PLA, it
contains a fixed mesh of unfinished layout that must be customized to yield the
final circuit. Gate-arrays are more powerful, however, because the contents of
the mesh are less structured so the interconnection options are more flexible.
Typical gate-array is built from blocks that contain unconnected transistor pairs, although
any simple component will do. An array of these blocks combined with I/O pads forms a
complete integrated circuit and offers a wide range of digital electronic options (as shown
in above figure). These blocks are internally customized by connecting the components to
form various logical operators such as AND, OR, NOT, and so on. The blocks are also
externally connected to produce the overall chip.
VLSI Design Styles:
Full Custom
 ASIC - Application-Specific Integrated Circuit
 PLD, FPGA - Programmable Logic
 So C - System-on-a-Chip
Full Custom Design Style:
Pre-manufactured components with programmable interconnect wired by CAD tools
Tradeoffs
 High Design Costs (huge effort!)
 High NRE Cost
 High Performance
 Low Unit Cost (good for high volume products!)
Examples
Analog and Mixed-Signal
 Microprocessor
ASIC Design Style:
Pre-designed (or pre-manufactured) components that are assembled and wired by CAD tools.
 Standard cell (pre-designed cells)
 Gate array (pre-manufactured cells - just add wiring)
 Structured ASIC (complex function customized by wiring)
Tradeoffs
 Low Design Cost
 High NRE Cost (lower in Gate Array / Structured ASIC)
 Medium Unit Cost
 Medium Performance
Examples:
 Control chip for cell phone
 Graphics chips for desktop computers (e.g. nVidia, ATI)
CPLD:
As the technology surrounding programmable devices improved, new devices were

developed which combined several PLD s together on a single integrated circuit to form
complex programmable logic devices, CPLD s. The concept is to have a few PLD blocks
or macro cells on a single device with a general-purpose interconnect in-between.
Basically, a CPLD consists of several blocks, each of which is a PLD, which are
connected together. I/Os of each of the PLD blocks are connected by a global
interconnect array. Each logic block contains 4 to 16 macro cells depending on the
vendor and the architecture. A macro cell on most modern CPLD s contains a sum-of-
products combinatorial logic function and an optional flip-flop. The combinatorial logic
function typically supports four to 16 product terms with wide fan-in. In other words, a
macro cell function can have many inputs, but the complexity of the logic function is
limited. CPLD s are generally best for control- oriented designs due in part to their fast
pin-to-pin performance. The wide fan-in of their macro cells makes them well-suited to
complex, high-performance state machines. CPLD has less flexible internal architecture
and the delay through a CPLD (measured in nanoseconds) is more predictable and
usually shorter. The below figure shows CPLD architecture.
FPGA:
At the beginning of 1980, there were programmable logic devices, which had fast design,
highly configurable and reprogrammable, but they were support only small functions.An
FPGA have bunch of programmable logic blocks in an array with programmable
switches. FPGA s are approximately 10 times less dense.
FPGA has two levels of programmability, each logic block can be programmed
individually to perform simple logic functions and then, switches can be programmed to
implement desire logic function. The key element in programmable logics are 3-input
Look Up Table (LUT), multiplexer and flip-flop. The 3-input LUT is similar to PAL,
used to implement combinational or Boolean equations. FPGA s contain programmable
logic components called "logic blocks", and a hierarchy of reconfigurable interconnects
that allow the blocks to be "wired together"—somewhat like many (changeable) logic
gates that can be inter-wired in (many) different configurations. Logic blocks can be
configured to perform complex combinational functions, or merely simple logic gates
like AND and XOR. In most FPGA s, the logic blocks also include memory elements,
which may be simple flip-flops or more complete blocks of memory.
PAL -
Programming Array Logic:

PALs were introduced in late 1970 to address speed problem shown by PLA devices. A
PAL is opposite to PROM, where AND array is programmable but OR array is fixed.
This led PAL faster than PLA devices. PAL s usually contain flip-flops connected to the
OR-gate outputs to implement sequential circuits. Registered or combinational output
functions are modeled in a sum of product form. Each output is a sum (logical or) of a
fixed number of products (logical and) of the input signals. PAL architecture has
feedback terms. The outputs of the fixed "or" array are fed back to some of the inputs of
the "and" array.
AND Plane OR Plane
PLA Schematic :
bc
ac
ab
abc
abc
abc
abc
a b c
s cout
Standard cell:
In semiconductor design, standard cell methodology is a method of designing
application-specific integrated circuits (ASICs) with mostly digital-logic features.
Standard cell methodology is an example of design abstraction, whereby a low-level
very-large-scale integration (VLSI) layout is encapsulated into an abstract logic
representation (such as a NAND gate). Cell-based methodology (the general class to
which standard cells belong) makes it possible for one designer to focus on the high-level
(logical function) aspect of digital design, while another designer focuses on the
implementation (physical) aspect. Along with semiconductor manufacturing advances,
standard cell methodology has helped designers scale ASICs from comparatively simple
single-function ICs (of several thousand gates), to complex multi-million gate system-on-
a-chip (SoC) devices.
Application of standard cell:
2-input NAND or NOR function is sufficient to form any arbitrary boolean function set.
But in modern ASIC design, standard cell methodology is practiced with a sizeable
library (or libraries) of cells. The library usually contains multiple implementations of the
same logic function, differing in area and speed. This variety enhances the efficiency of
automated synthesis, place and route (SPR) tools. Indirectly, it also gives the designer
greater freedom to perform implementation tradeoffs (area vs. speed vs. power
consumption.) A complete group of standard cell descriptions is commonly called a
technology library.
IC Design Steps:
Specifications
High-level Functional
Description Description
HLS
Placed
& Routed Gate-level Logic
Design Design Description
DESIGN STEPS:
Step 1: Prepare an Requirement Specification
Step 2: Create an Micro-Architecture Document.
Step 3: RTL Design & Development of IP's
Step 4: Functional verification all the IP's/Check whether the RTL is free from Linting
Errors/Analyze whether the RTL is Synthesis friendly.
Step 4a: Perform Cycle-based verification (Functional) to verify the protocol behaviour
of the RTL
Step 4b: Perform Property Checking , to verify the RTL implementation and the
specification understanding is matching.
Step 5: Prepare the Design Constraints file (clock

definitions(frequency/uncertainity/jitter),I/O delay definitions, Output pad load
definition, Design False/Multicycle-paths) to perform Synthesis, usually called as an
SDC synopsys_constraints, specific to synopsys synthesis Tool (design-compiler)
Step 6: To Perform Synthesis for the IP, the inputs to the tool are (library file(for which
synthesis needs to be targeted for, which has the functional/timing information available
for the standard-cell library and the wire-load models for the wires based on the fan-out
length of the connectivity), RTL files and the Design Constraint files, So that the
Synthesis tool can perform the synthesis of the RTL files and map and optimize to meet
the design-constraints requirements. After performing synthesis, as a part of the synthesis
flow, need to build scan-chain connectivity based on the DFT(Design for Test)
requirement, the synthesis tool (Test-compiler), builds the scan-chain.
7: Check whether the Design is meeting the requirements

(Functional/Timing/Area/Power/DFT) after synthesis.
Step 7a: Perform the Netlist-level Power Analysis, to know whether the design is meeting
the power targets.
Step 7b: Perform Gate-level Simulation with the Synthesized Netlist to check whether the
design is meeting the functional requirements.
Step 7c: Perform Formal-verification between RTL vs Synthesized Netlist to confirm that
the synthesis Tool has not altered the functionality.
Step 7d: Perform STA (Static Timing Analysis) with the SDF(Standard Delay Format)
file and synthesized netlist file, to check whether the Design is meeting the timing-
requirements.
Step 7e: Perform Scan-Tracin , in the DFT tool, to check whether the scan-chain is built
based on the DFT requirement.
Step 8: Once the synthesis is performed the synthesized netlist file(VHDL/Verilog

format) and the SDC (constraints file) is passed as input files to the Placement and
Routing Tool to perform the back-end Actitivities.
Step 9: The next step is the Floor-planning, which means placing the IP's based on the
connectivity,placing the memories, Create the Pad-ring, placing the
Pads(Signal/power/transfer-cells(to switch voltage domains/Corner pads(proper
accessibility for Package routing), meeting the SSN requirements(Simultaneous
Switching Noise) that when the high-speed bus is switching that it doesn't create any
noise related activities, creating an optimized floor plan, where the design meets the
utilization targets of the chip.
Step 9a : Release the floor-planned information to the package team, to perform the
package feasibility analysis for the pad-ring .
Step 9b: To the placement tool, rows are cut, blockages are created where the tool is
prevented from placing the cells, then the physical placement of the cells is performed
based on the timing/area requirements. The power-grid is built to meet the power-target
of the Chip.
Step 10: The next step is to perform the Routing, at first the Global routing and Detailed
routing, meeting the DRC (Design Rule Check) requirement as per the fabrication
requirement.
Step 11: After performing Routing then the routed Verilog netlist, standard-cells
LEF/DEF file is taken to the Extraction tool (to extract the parasitics(RLC) values of the
chip in the SPEF format(Standard parasitics Exchange Format), and the SPEF file is
generated.
Step 12: Check whether the Design is meeting the requirements

(Functional/Timing/Area/Power/DFT/DRC/LVS/ERC/ESD/SI/IR-Drop) after Placement
and Routing step.
Step 12a: Perform the Routed Netlist-level Power Analysis, to know whether the design
has met the power targets.
Step 12b: Perform Gate-level Simulation with the routed Netlist to check whether the
design is meeting the functional requirement.
Step 12c: Perform Formal-verification between RTL vs. routed Netlist to confirm that the
place & route Tool has not altered the functionality.
Step 12d: Perform STA (Static Timing Analysis) with the SPEF file and routed net list
file, to check whether the Design is meeting the timing-requirements.
Step 12e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain is
built based on the DFT requirement, Perform the Fault-coverage with the DFT tool and
Generate the ATPG test-vectors.
Step 12f: Convert the ATPG test-vector to a tester understandable format(WGL)
Step 12g: Perform DRC(Design Rule Check) verification called as Physical-verification,

to confirm that the design is meeting the Fabrication requirements.
Step 12h: Perform LVS(layout vs. Spice) check, a part of the verification which takes a
routed net list converts to spice (call it SPICE-R) and convert the Synthesized net list(call
it SPICE-S) and compare that the two are matching.
Step 12i : Perform the ERC(Electrical Rule Checking) check, to know that the design is
meeting the ERC requirement.
Step 12j: Perform the ESD Check, so that the proper back-to-back diodes are placed and
proper guarding is there in case if we have both analog and digital portions in our Chip.
We have separate Power and Grounds for both Digital and Analog Portions, to reduce the
Substrate-noise.
Step 12k: Perform separate STA(Static Timing Analysis) , to verify that the Signal-
integrity of our Chip. To perform this to the STA tool, the routed net list and SPEF
file(parasitic including coupling capacitances values), are fed to the tool. This check is
important as the signal-integrity effect can cause cross-talk delay and cross-talk noise
effects, and hinder in the functionality/timing aspects of the design.
Step 12l: Perform IR Drop analysis that the Power-grid is so robust enough to with-stand
the static and dynamic power-drops with in the design and the IR-drop is with-in the
target limits.
Step 13: Once the routed design is verified for the design constraints, then now the next
step is chip-finishing activities (like metal-slotting, placing de-coupling caps).
Step 14: Now the Chip Design is ready to go to the Fabrication unit, release files which
the fab can understand, GDS file.
Step 15: After the GDS file is released , perform the LAPO check so that the database
released to the fab is correct.
Step 16: Perform the Package wire-bonding, which connects the chip to the Package.
CMOS TESTING
Testing is one of the most expensive parts of chips
– Logic verification accounts for > 50% of design effort for many chips
– Debug time after fabrication has enormous opportunity cost
– Shipping defective parts can sink a company
NEED FOR TESTING:
The need of testing is to find out errors in the
application.
The good reasons of testing are
1) Quality Assurance.
2) Verification and validating the product/application
before it goes live in the market.
3) Defect free and user friendly.
4) Meets the requirements.
Logic Verification:
 Does the chip simulate correctly?

– Usually done at HDL level
– Verification engineers write test bench for HDL
• Can’t test all cases
• Look for corner cases
• Try to break logic design
 Ex: 32-bit adder
– Test all combinations of corner cases as inputs:
• 0, 1, 2, 231-1, -1, -231, a few random numbers
 Good tests require ingenuity.
Manufacturing Test:
 A speck of dust on a wafer is sufficient to kill chip
 Yield of any chip is < 100%
– Must test chips after manufacturing before delivery to customers to only
ship good parts
 Manufacturing testers are
very expensive
– Minimize time on tester
– Careful selection of test vectors
Observability & Controllability:
 Observability: ease of observing a node by watching external output pins of the

chip
 Controllability: ease of forcing a node to 0 or 1 by driving input pins of the chip
 Combinational logic is usually easy to observe and control

 Finite state machines can be very difficult, requiring many cycles to enter desired
state
– Especially if state transition diagram is not known to the test engineer.
Test Pattern Generation:
 Manufacturing test ideally would check every node in the circuit to prove it is not
stuck.
 Apply the smallest sequence of test vectors necessary to prove each node is not
stuck.
 Good observability and controllability reduces number of test vectors required for
manufacturing test.
– Reduces the cost of testing
– Motivates design-for-test.
Design for Test:
 Design the chip to increase observability and controllability
 If each register could be observed and controlled, test problem reduces to testing
combinational logic between registers.
 Better yet, logic blocks could enter test mode where they generate test patterns
and report the results automatically.
Scan:
 Convert each flip-flop to a scan register CLK
– Only costs one extra multiplexer
 Normal mode: flip-flops behave as usual SCAN
 Scan mode: flip-flops behave as shift register
Flop

SI
Contents of flops can be scanned out and new values scanned in. Q
D
scan-in
Flop
Flop
Flop
Flop
Flop
Flop
Logic Logic
inputs Cloud Cloud outputs
Flop
Flop
Flop
Flop
Flop
Flop
scanout
Built-in Self-test:
 Built-in self-test lets blocks test themselves

– Generate pseudo-random inputs to comb. logic
– Combine outputs into a syndrome
– With high probability, block is fault-free if it produces the expected
syndrome
.
PRSG:
 Linear Feedback Shift Register
– Shift register with input taken from XOR of state
_ pseudo-Random sequence generator.
CLK
Q[0] Q[1] Q[2]
Flop
Flop
Flop
D D D
BILBO:
Built-in Logic Block Observer
– Combine scan with PRSG & signature analysis.
D[0] D[1] D[2]
C[0]
C[1]
Q[2] / SO
Flop
Flop
Flop
SI 1
0 Q[0]
Q[1]
MODE C[1] C[0]

Scan 0 0
Logic Signature
PRSG Test 0 1
Cloud Analyzer
Reset 1 0
Normal 1 1
Boundary Scan:
 Testing boards is also difficult

– Need to verify solder joints are good
• Drive a pin to 0, then to 1
• Check that all connected pins get the values
 Through-hold boards used “bed of nails”
 SMT and BGA boards cannot easily contact pins
 Build capability of observing and controlling pins into each chip to make board
test easier.
Boundary Scan Interface:
Boundary scan is accessed through five pins
– TCK: test clock
– TMS: test mode select
– TDI: test data in
– TDO: test data out
– TRST*: test reset (optional)
 Chips with internal scan chains can access the chains through boundary scan for
unified test strategy.
Boundary Scan Example:
PackageInterconnect
CHIP B CHIP C
Serial Data Out
CHIP A CHIP D
IO pad and Boundary Scan

15. JNTU Syllabus with Additional Topics
S.n UNIT Topic Additional Topics

o NO
1 1 Introduction to IC Technology – MOS, PMOS,
NMOS
2 CMOS & BiCMOS technologies
3 Oxidation, Lithography
4 Diffusion, Ion
implantation,
Metallization,
Encapsulation
6 Basic Electrical Properties of MOS and
BiCMOS Circuits: Ids-Vds relationships
7 MOS transistor threshold Voltage, gm, gds,
8 Latch up susceptibility
Inverter
9 Various pull ups
10 CMOS Inverter analysis and design, Bi-
CMOS Inverters.
11 2 VLSI Design Flow, MOS Layers, Stick
Diagrams
12 Design Rules and Layout
13 sign rules for wires
14 Contacts and Transistors Layout Diagrams for
15 Scaling of MOS circuits, Limitations of
Scaling.
16 3 Logic Gates and Other complex gates, Switch
logic
17 Alternate gate circuits, Basic circuit concepts
18 Sheet Resistance RS and its concept to MOS
19 Area Capacitance Units, Calculations – - Dynamic register
Delays, Driving large Capacitive Loads element
20 Wiring Capacitances, Fan-in and fan-out,
Choice of layers
21 4 Subsystem Design, Shifters, Adders
22 ALUs, Multipliers, Parity generators
23 Comparators, Zero/One Detectors
24 Counters
25 High Density Memory Elements
26 PLAs
27 FPGAs
28 CPLDs
29 Standard Cells
30 Programmable Array Logic, Design Approach System partitioning
31 5 VHDL Synthesis, Circuit Design Flow
32 Circuit Synthesis, Simulation
33 Layout, Design capture tools
34 Design Verification Tools
35 Test Principles
36 CMOS Testing, Need for testing
37 Test Principles, Design Strategies for test
38 Chip level Test Techniques Gallium arsenide
devices
15.1. Sources of Information

10.1.1. Text books:-
1. Essentials of VLSI circuits and systems – Kamran Eshraghian, Eshraghian Douglas and A.
Puck Nell, PHI, 2005 Edition.
2. Principles of CMOS VLSI Design – Weste and Eshraghian, Pearson Education, 1999.
15.1.2. Reference Text Books:-

1. Chip Design for Submicron VLSI: CMOS Layout & Simulation, – John P.
Uyemura, Thomson Learning.
2. Introduction to VLSI Circuits and Systems – John .P. Uyemura, John Wiley,
2003.
3. Digital Integrated Circuits – John M. Rabaey, PHI, EEE, 1997.
4. Modern VLSI Design – Wayne Wolf, Pearson Education, 3rd Edition, 1997.
5. VLSI Technology – S.M. SZE, 2nd Edition, TMH, 2003.
collected by Stat press SEOlution (blogcraft).
15.2. Unit wise Summary:
S. Unit Total Topics to be covered Reg/Additio Teaching Rema

L No no of nal aids used rks
no Period LCD/OHP
s /BB
1 I 06 Introduction to IC Technology – MOS, Regular OHP,BB
PMOS, NMOS
2 CMOS & BiCMOS technologies Regular OHP,BB
3 Oxidation, Lithography Regular OHP,BB
4 Diffusion, Ion implantation, Metallization, Regular OHP,BB
Encapsulation
Capacitors.
6 Tutorial class-1 BB
7 II 09 Basic Electrical Properties of MOS and Regular OHP,BB
BiCMOS Circuits: Ids-Vds relationships
8 MOS transistor threshold Voltage, gm, Regular BB
gds,
9 figure of mer Regular OHP,BB
NMOS Inverter
11 CMOS Inverter analysis and design, Bi- Regular BB
CMOS Inverters.
12 Latch up susceptibility Additional OHP,BB
13 Tutorial Class-2 BB
14 Solving University papers BB
15 Assignment test-1
16 III 06 VLSI Design Flow, MOS Layers, Stick Regular OHP,BB
Diagrams
17 Design Rules and Layout Regular OHP,BB
18 Regular BB
19 Contacts and Transistors Layout Regular BB
Diagrams for NMOS and CMOS
Inverters and Gates
20 Scaling of MOS circuits, Limitations of Regular OHP,BB
Scaling.
21 Tutorial class-3 BB
22 IV 09 Logic Gates and Other complex gates, Regular OHP,BB
Switch logic
23 Alternate gate circuits, Basic circuit Regular BB
concepts
24 Sheet Resistance RS and its concept to Regular LCD,OHP,B
MOS B
25 Area Capacitance Units, Calculations – Regular OHP,BB
- Delays, Driving large Capacitive
Loads
26 Wiring Capacitances, Fan-in and fan-out, Regular BB
Choice of layers
27 Dynamic register element Additional OHP,BB
31 V 06 Subsystem Design, Shifters, Adders Regular OHP,BB
32 ALUs, Multipliers, Parity generators Regular OHPBB
33 Comparators, Zero/One Detectors Regular OHP,BB
34 Counters Regular OHP,BB
35 High Density Memory Elements Regular BB
37 VI 09 PLAs Regular OHP,BB
38 FPGAs Regular OHP,BB
39 CPLDs Regular OHP,BB
40 Standard Cells Regular OHP,BB
41 Programmable Array Logic, Design Regular BB
Approach
42 System partitioning Additional BB
46 VII 06 VHDL Synthesis, Circuit Design Flow Regular OHP,BB
47 Circuit Synthesis, Simulation Regular OHP,BB
48 Layout, Design capture tools Regular OHP,BB
49 Design Verification Tools Regular OHP,BB
52 VIII 09 CMOS Testing, Need for testing Regular OHP,BB
53 Test Principles, Design Strategies for Regular OHP,BB
test
54 Chip level Test Techniques Regular BB
55 System-level Test Techniques Regular BB
56 Layout Design for improved Testability. Regular BB
57 Gallium arsenide devices Additional OHP,BB
16. University previous Question papers
IV B.TECH – I SEM EXAMINATIONS, NOVEMBER - 2010

VLSI SYSTEMS DESIGN
(COMMON TO CSE, IT, CSS, ECC)
Time: 3hours Max.Marks:80
Answer any FIVE questions
All questions carry equal marks
---
1. a) Explain why CMOS technology is most suitable for VLSI ICs?
b) List the advantages and disadvantages of CMOS technology over bipolar technology.
[8+8]
2. a) Define the following terms:
i) Fan – out
ii) Logic levels
iii) Propagation delay
iv) Noise margin
b) Draw a stick diagram CMOS 2-input NAND gate. [8+8]
3. a) Draw a layout for CMOS 2-input NOR gate.

b) Implement 2-input AND gate using static complementary logic. [8+8]
4. a) Compare dynamic and re-circulating latches.

b) With example, explain what do you mean by transistor sizing? [8+8]
5. a) Explain the path-delay measurement of combinational logic circuits.

b) Explain the design principles of pipelining. [8+8]
6. Explain about power distribution and clock distribution of routing procedure. [16]
7. Explain any one routing algorithm with suitable example. [16]
8. Write short notes on any TWO:

i) FPGA
ii) Hardware / software co – design
iii) Architectural testing. [5+5+6] SET-1
*****
VLSI SYSTEMS DESIGN
---



i) FPGA
iii) Architectural testing. [5+5+6]

[8+8]

i) Fan – out
ii) Logic levels
iv) Noise margin
*****
SET-2
VLSI SYSTEMS DESIGN
---

i) FPGA

[8+8]

i) Fan – out
ii) Logic levels
iv) Noise margin


*****
SET-3
VLSI SYSTEMS DESIGN
---

i) FPGA

[8+8]

i) Fan – out
ii) Logic levels
iv) Noise margin



*****
SET-4
17. Question Bank
UNIT 1
1. With neat sketch explain how NPN transistors are fabricated in bipolar process.
2. Write in detail about integrated passive components.
3. Compare CMOS and Bipolar technologies.
4. Explain about following two oxidation methods.
a. High pressure Oxidation
b. Plasma oxidation.
5. Clearly explain various diffusion effects in silicon with emphasis on VLSI
6. application.
7. Explain the following,
a. Thermal oxidation technique
b. Kinetics of thermal oxidation.
8. With neat sketch explain the Ion-lithography process.
9. Explain how diodes and resistor are fabricated in Bipolar process.
10. Explain the NMOS fabrication procedure.
11. Explain CMOS fabrication using n-well process.
12. With neat sketch explain how resistor and capacitor are fabricated in p-well
process.
13. Explain how resistors and diodes are fabricated in CMOS process.
14. Explain in detail the IC fabrication steps. What is the size of silicon wafer used
for manufacturing state-of-the art VLSI ICs.
15. What are the different VLSI technologies available compare their speed/power
performance?
16. Draw the cross sectional view of CMOS p-well process.
17. With neat sketch explain BICMOS fabrication in an n-well process.
18. What is lithography? Explain.
19. Clearly explain about ION-IMPLANTATION step in IC fabrication.
i. Derive an equation for Ids of an n-channel enhancement MOSFET

operating in
20. Saturation region.
21. Define threshold voltage of a MOS device and explain its significance.
22. Explain the effect of threshold voltage of MOSFET current equation.
23. With neat sketch, explain drain characteristics of an n-channel enhancement
MOSFET.
24. Explain about body effect of MOSFET.
25. Explain the operation of BICOMS inverter.
26. Explain various regions of CMOS inverter transfer characteristics.
27. Derive an equation for Rds of an n-channel enhancement MOSFET in linear
region.
28. Explain latch-up problem in CMOS circuit.
29. Derive an equation for transconductance of an n-channel enhancement MOSFET
30. operation.
31. Explain channel length modulation of the MOSFET.
32. Explain how the BICOMS inverter performance can be improved.
33. Determine pull-up to pull-down ratio of an NMOS inverter driven by another
NMOS
34. transistor.
35. Determine pull-up to pull-down ratio of an NMOS inverter when driven through
36. one or more.
37. Explain different forms of pull-ups used as load in CMOS and in enhancement
and
38. depletion modes of NMOS.
UNIT 2
1. What is stick diagram and explain about different symbols used for components in
Stick diagram
2. Discuss in detail the NMOS design style.
3. Design a stick diagram for NMOS EX-OR gate.
4. Discuss CMOS design style. Compare with NMOS design style.
5. What are the effects of scaling on Vt?
6. Explain about layers in integrated circuits.
7. Why is VLSI design process presented in NMOS only?
8. Design a stick diagram for the CMOS logic shown y = (AB+CD).
9. What are design rules?
10. Explain lambda based design rules, contact cuts and double metal process rules.
UNIT 3
1. Explain the requirement and operation of pass transistor and transmission gates.
2. Explain clocked CMOS logic, domino logic and n-p CMOS logic.
3. Explain constructional features and performance characteristics of pseudo NMOS logic
4. Define the following
a) Sheet resistance concept applied to MOS transistor and inverters.
b) Standard unit of capacitance.
5. Describe the following briefly,
a) Cascaded inverters as drivers
b) Super buffers
c) BICMOS drivers.
6. What do you mean by inverter delay? Explain.
7. What is the problem of driving large capacitive loads? Explain a method to drive such
load.
8. Describe three source of wiring capacitance.
9. Define fan-in and fan-out. Explain their effects on propagation delay.
10. Explain rise time and fall-time and their characteristics
UNIT 4
1. Draw and explain the structure of a carry look ahead adder.

2. Why is static 6-transistor cell used for average CMOS system design?
3. Write short notes on the following,
a) Manchester carry chain
b) Ripple-carry adder
c) Full adder.
4. Design a schematic for an 8-word * 2-bit NAND ROM that serves a lookup table to
Implement a full adder.
5. Write short notes on ALU S
6. Draw the structure of a serial-parallel multiplier and explain it.
7. Explain how a Booth recoded multiplier reduces the number of adders.
8. Describe in detail about parity generators.
9. Draw and explain the basic memory chip architecture.
10. Explain the trade offs between open, closed, and twisted bit lines in a dynamic RAM
array.
11. Draw circuit diagram of a one transistor with transistor capacitor dynamic RAM and
also draw its layout.
12. Briefly describe the three transistor dynamic RAM.
13. Draw the schematic for tiny XOR gate and explain its operation.
14. Classify binary counters and explain each in detail.
UNIT 5
1.Draw the typical architecture of PAL and explain the operation of it.
Implement JK flip-flop using PROM.
2Write briefly about channel-less gate arrays with neat sketches.
3Write about channeled gate arrays.
4What are advantages and disadvantages of the reconfiguration?
5Explain any one chip architecture that used the anti fuse and give its advantages.
6Draw and explain the FPGA chip architecture.
7Clearly explain each step of high level design flow of an ASIC.
8What is CPLD? Draw its basic structure and give its applications.
9Implement 2-bit comparator using PROM.
10.Draw the typical standard cell structure showing regular power cell and explain.
11.What are the characteristics of 22v10PAL CMOS device and draw its I/O structure.
12. Explain the methods of programming of PAL CMOS device.
13. Explain the function of 4:1 multiplexer in PAL CMOS device with the help of I/O
pads.
14.With a neat sketch clearly explain the architecture of a PLA.
15. Explain in detail the need for testing and the two groups of testing.
16. What are the reasons of malfunctioning of chip? What are the different levels of
testing?
17. What is meant by short circuit and open circuit faults?
18. Draw the basic structure of parallel scan and explain how it reduces the long scan
chains.
19. What is ATPG? Explain a method of generation of test vector.
20. Explain in detail the concurrent fault simulation
21. Explain the self-test technique ‘Signature Analysis and BILBO’.
22. How IDDQ testing is used to test the bridge faults?
23. What is the design for autonomous test and what is the basic device used in this?
24. Explain the gate level and function level of testing.
25. What type of testing technique are suitable for the following,
a. Memories
b. Random logic
c. Data path.
26. What is boundary scan test? Explain.
27. Draw the state diagram of TAP controller and explain how it provides the
control signals for test data and instruction register.
28. What type of faults can be reduced by improving layout design?
29. A sequential circuit with ‘n’ inputs and ‘m’ storage devices. To test this circuit
how many test vectors are required?
18. ASSIGNMENT TOPICS
UNIT 1:
WEEK 1:
1. Fabrication process.
2. PMOS fabrication.
3. CMOS fabrication.
WEEK 2:
1. NMOS enhancement mode transistor action.

2. BICMOS fabrication.
3. Difference b/w CMOS technology and Bipolar technology
UNIT 2:
WEEK 3:
1. IDS-VDS relation
2. Various pull-ups
3. CMOS inverter analysis.
WEEK 4:
1. Trans conductance (gm) & Figure of merit(w0).

2. NMOS Inverter.
3. Pass transistor
UNIT 3:
WEEK 5:
1. Stick diagram
2. Scaling of MOS circuit
3. NMOS and CMOS contacts.
WEEK 6:
1. Design rules and layout.

2. Scaling of MOS circuits
3. To design CMOS nand gate.
UNIT 4:
WEEK 7:
1. Switch logic
2. Driving large capacitance
3. Sheet resistance
WEEK 8:
1. Fan-in and fan-out.

2. Logic Gates and Other complex gates.
3. Wiring Capacitances.
UNIT 5:
WEEK 9:
1. Shifters.
2. ALU
3. Counters.
WEEK 10:
1. Adders.
2. Multiplier’s.
3. Comparators.
UNIT-6:
WEEK 11:
1. CPLD.
2. FPGA
3. Programmable array logic
WEEK 12:
1. Standard cell.
2. Programmable array logic.
3. PLA’S
UNIT 7:
WEEK 13:
1. Circuit design flow

2. Design capture tools
3. Test principles.
WEEK 14:
1. VHDL synthesis.
2. Simulation.
3. Layout design.
UNIT 8:
WEEK 15:
1. Chip-level test
2. System –level test
3. CMOS testing.
WEEK 16:
1. Need for testing.

2. Test principles
3. Layout design for improved test ability
19. Unit wise Objective type & mid questions
INTERNAL - I
ANSWER ANY FOUR OUT OF SIX QUESTIONS:
1. With neat sketches explain CMOS fabrication using p-well process.

2. a) Define threshold voltage of a MOS device and explain its significance.
b) Explain the effect of threshold voltage on MOSFET current equation
3. Design a stick diagram for NMOS EX-OR gate.
4. Draw the stick diagram and mask layout for a CMOS two input NOR gate and
stick diagram of two input NAND gate
5. Explain clocked CMOS logic, domino logic and n-p CMOS logic.
6. Describe constructural features and performance characteristics of pseudo-NMOS
logic.
OBJECTIVE (FIRST-MID)
1. Load capacitance affects

a) Power consumption
b) Efficiency
c) Output voltage
d) Transconductance.
2. With reference to Lambda based rules for wires polysilicon to polysilicon separation is
a) 4Lambda
b) 3lambda
c) 2lambda
d) 1lambda
3. The number of signals terminals of package inputs request for logic devices can be
estimated as number of inputs=
a) alpha
b) Lambda
c) Beta
d) Gate
4. The area capacitance as per 5 micrometer process technology for metal to substrate is
a) 2
b) 1
c) 3
d) 5
5. The sheet resistance as per 5µ m process technology foe n-diffusion is
a) 20 to 30
b) 10 to 20
c) 5 to 10
d) 15 to 20
6. Channel resistance is scaled by
a) 2
b) 3
c) 8
d) 1
7. Parasitic capacitance is scaled by
a) 10
b) 15
c) 3
d) 12
8. In NMOS inverter, the depletion mode device is called
a) Pull-up transistor
b) pull-down transistor
c) both
d) none
9. With reference to lambda based rules minimum width of metal is
a) 2lambda
b) 1lambda
c) 3lambda
d) 4lambda
10. Common type of silicides used for polycide is
11. Regardless of supply voltage, maximum drift velocity in MOS is
12. Switch logic is based on
13 time is most affected by count capacitance in CMOS logic gate delays
14. may be used to convey layer information through the use of a color code
15. A transistor is formed whenever polysilicon crosses
16. Dynamic logic arrangement, in which n and p logic blocks are in cascade
Cascaded Structure..
17. The source and drain n-diffusion regions form junctions with the
18. In NMOS inverter, the enhancement mode device is called
19. The deficiency of MOS technology lies in the driving capabilities of MOS
20. For modern NMOS technology gate material is
KEY:
1. a
2. c
3. a
4. c
5. b
6. d
7. d
8. a
9. d
10. Heavily doped n type polysilicon.
11. Mosi2
12. Saturation velocity.
13. Pass transistor or transmission gate.
14. Transition
15. Stick diagram
16. n-diffusion or p-diffusion
17. n-p CMOS logic.
18. p-substrate or p-well
19. Pull-down transistor.
20. Limited load
SECOND MID SUBJECTIVE
1. Implement the comparators in VLSI subsystem design?
2. What id DRAM? Operation of DRAM and transistor DRAM cell?
3. Explain FPGA and their advantages? Also compare CPLD and FPGA?
4. What is layout VHDL? Describe placement and routing in VHDL layout?
5. Describe the VHDL synthesis process with neat block diagram?
6. Explain full scan and partial scan in CMOS testing?
OBJECTIVE (MID-II)
1. For a four bit word, a one-bit shift right is equivalent to a

a) two bit shift left
b) three bit shift left
c) one bit shift left
d) four bit shift
2. The heart of ALU is
a) Register
b) Adder
c) Control bus
d) I/O port
3. The type of switch used in shifters is
a) Line switch
b) Transistor type switch
c) Crossbar switch
d) gate switch
4. The carry chain in adder is consist with
a) Cross bar switch
b) Trnasmision type switch
c) Bus interconnection
d) Pass transistor
5. The subsystem level is classified as
a) First level
b) Top level
c) Bottom level
d) Leaf cell level
6. A MOS PLA is realized by using the gate of
a) NOR
b) XOR
c) AND
D) NOR
7. A macro cell in CPLD is composed of
a) J-K flip-flop
b) R-S-Flip-flop
c) T –flip-flop
d) D-flip-flop
8. The CPLD can be rewritable in about
a) <10TIMES
b) <100TIMES
c) <1000TIMES
d) >1000TIMES
9. Logic gates are placed in rows of standard cells of
a) Equal height
b) Equal width
c) Variable height
d) constant width
10. Correct operation of a design must not be dependent on
a) Rise time or fall time
b) Short circuits in diffusion
c) Layout
d) Short and open circuits in metal layer.
11. The advantage of facility in the design is testing procedure from known
condition.
12. In testing the corresponding mode is linear shift mode.
13. used to simulate the cell
14. is tested by using design rule checker.
15. Generally are tested by self test.
16. The IEEE 1149 boundary is used for
17. The test that are generally carried after chip is manufactured are called
18. Functionality test seek to verify of a chip.
19. Random logic is probably best tested by
20. In layout synthesis generally two phases are required they are
KEY:
1. B
2. B
3. C
4. D
5. D
6. A
7. D
8. D
9. A
10. A
11. Reset
12. BILBO
13. Probe
14. Layout
15. Memories
16. System level testing
17. Manufacturing test
18. Function
19. Full serial scan or parallel scan
20. Placement and routing.
OBJECTIVE
1. A CMOS transistor can be implemented using _________ [ ]

A) 2-nmos
B) 2-pmos
C) 1-nmos, 1-pmos
D) all
2. Major design challenges in IC’s is ______________ [ ]
A) Power density
B) Power dissipation
C) Both
D) None
3. Advantage of IC technology ____________ [ ]
A) High package density
B) high circuit speed
C) reduced size
D) all
4. MOS technology circuit can be realized as ____________ [ ]

A) nMOS
B) pMOS
C) CMOS
D) all
5. ____________ are the approaches for CMOS fabrication [ ]
A) P – well process
B) n – well process
C) Twin – tub process
D) all
6. Transistors are fabricated within the regions called____________ [ ]
A) Tubs
B) wells
C) both
D) none
7. A CMOS transistor can be operated in _____________ mode [ ]
A) Cut-off
B) Linear
C) saturation
D) all
8. Different MOS capacitance models are _________ [ ]
A) Simple MOS capacitance
B) detailed MOS gate capacitance
C) both
D) none
9. Different types of digital design methodologies are ______________ [ ]
A) Top-down design
B) bottom-up design
C) both
D) none
10. High impedance condition exist when both pull-up and pull-down networks are____[
]
A) ON
B) OFF
C) either ON or OF
D) none
11. The technique to increase number of devices per chip is called
___________________.
12. For MOS transistor the voltage applied between gate and source bellow which the
drain and sourcecurrent effectively drops to zero is known as __________________
13. The transit time for travel of electron or hole from source to drain in given by
____________.
14. The parasitic capacitance arises from reverse biased p-n junction and are called as
__________.
15. Scaling improves _________________ by shrinking the dimensions of transistor and
interconnection between them
16. A parallel combination of MOSFET is known as ____________ gate.
17. A two input NAND consists of two series _________ transistors and two parallel
___________
transistors.
18. A pMOS or nMOS transistor alone is called as ______________ transistor
19. A parallel combination of pMOS and nMOS transistors is called a ____________
gate.
20. Gate capacitance has two components known as __________________ and
___________
KEY
1. C
2. C
3. D
4. D
5. D
6. C
7. D
8. C
9. C
10. B
11. Level of Integration
12. THRESHOLD VOLTAGE
13. tsd = L2 / μVDS
14. Diffusion Capacitance
15. Figure of Merit
16. Transmission
17. Nmos, pmos
18. Pass
19. Transmission
20. Intrinsic capacitance, overlap capacitance
20.Tutorial Problems
UNIT 1
INTRODUCTION
Synthetic detail of an integrated circuit through four layers of planarized copper

interconnect, down to the polysilicon (pink), wells (greyish), and substrate (green).
Integrated circuits were made possible by experimental discoveries which showed that
semiconductor devices could perform the functions of vacuum tubes and by mid-20th-
century technology advancements in semiconductor device fabrication. The integration of
large numbers of tiny transistors into a small chip was an enormous improvement over
the manual assembly of circuits using electronic components. The integrated circuit's
mass production capability, reliability, and building-block approach to circuit design
ensured the rapid adoption of standardized ICs in place of designs using discrete
transistors.
There are two main advantages of ICs over discrete circuits: cost and performance. Cost
is low because the chips, with all their components, are printed as a unit by
photolithography rather than being constructed one transistor at a time. Furthermore,
much less material is used to construct a packaged IC die than a discrete circuit.
Performance is high since the components switch quickly and consume little power
(compared to their discrete counterparts) because the components are small and
positioned close together. As of 2006, chip areas range from a few square millimeters to
around 350 mm2, with up to 1 million transistors per mm
IC Fabrication Process:
An integrated circuit consists of a single crystal chip of
silicon. Containing both active and passive elements, and their interconnection.
The basic structure of an IC consists of four layers of materials, such that:
1.Substrate
2.Epitaxialgrowth
3.Diffusion
4. Metallization
Substrate:
The p-type silicon bottom layer (6 mils thick) and serves where the
Integrated circuit is to be built known as Substrate.
Epitaxial growth:
The second n-type layer (25µm=1mil)where all active and

passive component are built, which is grown as a single crystal extension is called
Epitaxial growth.
Diffusion:
The third layer of IC fabrication is Diffusion process. Active and

passive component are made by diffusing p-type and n-type impurities. The
selective diffusion of impurities is accomplished by using SiO2 as a barrier.
Metallization:
Finally a fourth material (aluminum) Layer is added to supply the necessary
interconnection between components. It provided contact among the components Al is
used for metallization.
Diode Fabrication:
Transistor Fabrication:
UNIT 2
BASIC ELECTRICAL PROPERTIES
The MOS transistor evolves from the use of a voltage on the gate to induce a charge in
the channel between source and drain, which may then be caused to move from source to
drain under the influence of an electric field created by voltage Vds applied between
drain and source. Since the charge induced is dependent on the gate to source voltage
then Ids is dependent on both Vgs and Vds.
polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.9)
p-type body
MOS structure looks like parallel plate capacitor while operating in inversion
– Gate – oxide – channel
Qchannel = CV
C = Cg = eoxWL/tox = CoxWL
V = Vgc – Vt = (Vgs – Vds/2) – Vt
Charge is carried by e-
Carrier velocity v proportional to lateral E-field between source and drain
v = mE m called mobility
E = Vds/L
Time for carrier to cross channel:
t = L /V
Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross
W
 = Cox
L
If Vgd < Vt, channel pinches off near drain, When Vds > Vdsat = Vgs – Vt
Now drain voltage no longer increases current
I ds    
V
 Vgs  Vt  dsat 2  Vdsat
 

V 
2
 gs  Vt
2

 0 Vgs  Vt cutoff


I ds    Vgs  Vt  ds Vds Vds  Vdsat
V
linear
  
2
 
 t
2
 V gs  V Vds  Vdsat saturation
2
Characteristics of nMOS transistor:
2.5
Vgs = 5
1.5 Vgs = 4
Ids (mA)
1
Vgs = 3
0.5
Vgs = 2
Vgs = 1
0
0 1 2 3 4 5
Vds
The threshold voltage of a MOSFET is usually defined as the gate voltage where an
inversion layer forms at the interface between the insulating layer (oxide) and the
substrate (body) of the transistor. The purpose of the inversion layer's forming is to allow
the flow of electrons through the gate-source junction.
UNIT 3
VLSI CIRCIUT DESIGN PROCESSES
MOS design is aimed at specification into masks for processing silicon to meet the
specification .MOS circuits are formed on four basic layers –n-diffusion, p-diffusion,
polysilicon and metal, which are isolated from one another by thick or thin(thinox)silicon
dioxide insulating layers. The thin oxide (thinox) mask includes n=diffusion, p-diffusion
and transistor channels.
STICK DIAGRAM:
Stick diagrams are used to convey the information through the use of a color code .the
below table shows the color code
• Allow translation of circuits (usually in stick diagram or symbolic form) into actual
geometry in silicon
• Interface between circuit designer and fabrication engineer
• Compromise
– designer - tighter, smaller
– fabricator - controllable, reproducible
Lambda Based Design Rules :

Design rules based on single parameter, λ
• Simple for the designer
• Wide acceptance
• Provide feature size independent way of setting out mask
• If design rules are obeyed, masks will produce working circuits
• Minimum feature size is defined as 2 λ
• Used to preserve topological features on a chip
• Prevents shorting, opens, contacts from slipping out of area to be contacted
Wiring:
wiring is the space required for a wire

4  width, 4  spacing from neighbor = 8  pitch
Transistors also consume one wiring track
Layout of CMOS NAND and NOR Gates:
The mask layout designs of CMOS NAND and NOR gates follow the general principles
examined earlier for the CMOS inverter layout. Figure 3.7 shows the sample layouts of a
two- input NOR gate and a two-input NAND gate, using single-layer polysilicon and
single-layer meta.
CMOS Layout Design Rules:
The layout designer must follow these rules in order to guarantee a certain yield for the
finished product, i.e., a certain ratio of acceptable chips out of a fabrication batch. A
design which violates some of the layout design rules may still result in a functional chip,
but the yield is expected to be lower because of random process variations. The design
rules below are given in terms of scaleable lambda-rules. Note that while the concept of
scaleable design rules is very convenient for defining a technology-independent mask
layout and for memorizing the basic constraints, most of the rules do not scale linearly,
UNIT 4
GATE LEVEL DESIGN

logic gate is an idealized or physical device implementing a Boolean function, that is, it
performs a logical operation on one or more logic inputs and produces a single logic
output. Depending on the context, the term may refer to an ideal logic gate, one that has
for instance zero rise time and unlimited fan-out, or it may refer to a non-ideal physical
device.
Switch logic:
Switch logic is based on the pass transistor or on transmission gates. This approach is
fast for small arrays and takes no static current from the supply rails. Thus, power
dissipation of such arrays is small since current in flows on switching.
(figure shows transmission gates)
Pass transistors and Transmission gates:

Switches and switch logic ay be formed from simple n or p-pass transistors or from
transmission gates comprising an n-pass and a p-pass transistor in parallel the reason for
adopting the apparent complexity of the transmission gate, rather than using a simple n-
switch or p-switch in most CMOS applications, is to eliminate the undesirable threshold
voltage effects which give rise to the loss of logic levels in pass transistors
Other forms of CMOS logic:
Clocked CMOS Logic (C2MOS):
Clocked CMOS logic has been used for very low power CMOS and/or for minimizing
hot electron effect problems in N-FET devices .Clocking transistors allow valid logic
output only when clk is high. Clocking transistors may be at output end of logic trees
(maximum performance) or at power supply end of logic trees (maximum protection
from hot electrons)
Pseudo-nmos logic:
Using a PMOS transistor simply as a pull-up device for an n-block is called pseudo-
NMOS logic. A.3 Note, that this type of logic is no longer ratio-less, i.e., the transistor
widths must be chosen properly, i.e., The pull-up transistor must be chosen wide enough
to conduct a multiple of the n-block's leakage and narrow enough so that the n-block can
still pull down the output safely.
Dynamic CMOS logic:

The actual logic is implemented in the inherently faster nmos logic ,a p-transistor is used
for the non-time-critical precharging of the output line so that the output capacitance is
charged to vdd during the of period of the clock signal.
UNIT 5
SUBSYSTEM DESIGN
Large systems are composed of sub-systems, known as Leaf-Cell .The most basic leaf cell is
the common logic gate (inverter, nand, ..Etc). Structured Design-High regularity-Leaf cells
replicated many times and interconnected to form the system. Logical and systematic
approach to VLSI design is essential.
SHIFTER:
A Shifter is most widely used for arithmetic operations. usually shifting is equivalent to
multiplication by powers of two. Shifting is required during floating-point arithmetic. The
shit register is simplest shifters that can shift by one position per clock cycle.
BARREL SHIFTER:
Barrel shifter produces n output bits and accepts 2n data bits , n control signals . The Barrel
shifter shifts by transmitting a n-bits slice of the 2n data bits to the output.
Adders:
The adder is probably the most studied digital circuit. There are a great many ways to
perform binary addition, each with its own area/delay trade-offs. A great many tricks
have been used to speed up addition: encoding, replication of common factors, and
precharging are just some of them. The origins of some of these methods are lost in the
mists of antiquity. Since advanced circuits are used in conjunction with advanced logic,
we need to study some higher-level addition methods before covering circuits for
addition.
Serial adder:
Serial adder may require many clock cycles to add two n-bit numbers, but with a very
short cycle time. Usually, they can work on nibbles or on bytes. The most extreme form
of the serial adder is a bit serial adder. When current data bits are the least significant bits
of the addends then a n LSB signal is high.
The addends appear LSB first and can be of arbitrary length the end of a pair of numbers
is signaled by the LSB bit for the next pair.
CARRY SELECT ADDER:
It comprises two versions of the addition whose carry –ins are different, then selects the right
one.
ALU:
An ALU is a Arithmetic Logic Unit that requires Arithmetic operations and Boolean
operations. Basically arithmetic operations are addition and subtraction. one may either
multiplex between an adder and a Boolean unit or merge the Boolean unit into the adder as in
the classic transistor-transistor logic.
MULTIPLIERS:
The multiplier is divided into two parts namely, Both-array and carry propagate adder (CPA).
By ascending the 16-bit inputs, the booth array feeds the result of the multiplier is divided by
the floor plan according hierarchy using an array block and a CPA block.
UNIT 6
SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN

Programmable logic device:
A programmable logic device or PLD is an electronic component used to build
reconfigurable digital circuits. Unlike a logic gate, which has a fixed function, a PLD has
an undefined function at the time of manufacture. Before the PLD can be used in a circuit
it must be programmed, that is, reconfigured.
PLA s:
Combinational circuit elements are an important part of any digital design. Three
common methods of implementing a combinational block are random logic, read-only
memory (ROM), and programmable logic array (PLA). In random-logic designs, the
logic description of the circuit is directly translated into hardware structures such as AND
and OR gates. The difficulty in this method is that the placement and interconnection cost
is high. In a large system, this cost could be prohibitive. The ROM is useful for tabular
data that has little regularity, but it is very wasteful of space for data that could be
algorithmically derived. The PLA combines features of both other methods by allowing
the designer to realize combinational design with programming taps on a logic array.
The PLA is made up of an AND plane and an OR plane. The AND plane produces product
terms of input variables selected by the programming taps and the OR plane produces the
sums of these product terms selected by a different set of programming taps. The symbolic
representation of the places where the programming taps are placed is known as the
personality matrix of the PLA. Figure 4.1 shows the generic structure of a PLA that
programs these logic functions:
PLA s are popular because their generation can be automated, which frees the designer
from spending valuable time creating random-logic gates. Since the PLA generator fixes
the physical structure of the PLA, there arises the problem of accommodating the
designer's special requirements, if any. The first requirement would be to reduce the area
occupied by the PLA. Usually the personality matrix is so sparse that a straightforward
mapping of the matrix to the silicon will result in wasted silicon area. Instead, the PLA is
folded to reduce the area required for the physical implementation. Instead of having one
AND plane and one OR plane, the PLA can be split into many more AND and OR
planes. Also, the input and output columns can be moved and folded such that there are
two to a column instead of the usual one. The rows can be similarly moved and folded.
Gate-Arrays:
The gate-array is a popular technique used to design IC chips. Like the PLA, it
contains a fixed mesh of unfinished layout that must be customized to yield the
final circuit. Gate-arrays are more powerful, however, because the contents of
the mesh is less structured so the interconnection options are more flexible.
Typical gate-array is built from blocks that contain unconnected transistor pairs, although
any simple component will do. An array of these blocks combined with I/O pads forms a
complete integrated circuit and offers a wide range of digital electronic options (as shown
in above figure). These blocks are internally customized by connecting the components to
form various logical operators such as AND, OR, NOT, and so on. The blocks are also
externally connected to produce the overall chip.
VLSI Design Styles:
Full Custom
 ASIC - Application-Specific Integrated Circuit
 PLD, FPGA - Programmable Logic
 So C - System-on-a-Chip
Full Custom Design Style:

Pre-manufactured components with programmable interconnect wired by CAD tools
Tradeoffs
 High Design Costs (huge effort!)
UNIT 7
VHDL SYNTHESIS
Design flow in VHDL synthesis
VHDL is a hardware description language used in electronic design automation to

describe digital and mixed-signal systems such as field-programmable gate arrays and
integrated circuits.
VHDL is commonly used to write text models that describe a logic circuit. Such a model
is processed by a synthesis program, only if it is part of the logic design. A simulation
program is used to test the logic design using simulation models to represent the logic
circuits that interface to the design. This collection of simulation models is commonly
called a testbench.
One of the main applications of VHDL is the synthesis of electronic circuits. Circuit
Synthesis with VHDL is an introduction to the use of VHDL logic (RTL) synthesis tools
in circuit design. The modeling styles proposed are independent of specific market tools
and focus on constructs widely recognized as synthesizable by synthesis tools.
A statement of the prerequisites for synthesis is followed by a short introduction to the
VHDL concepts used in synthesis. Circuit Synthesis with VHDL presents two possible
approaches to synthesis: the first starts with VHDL features and derives hardware
counterparts; the second starts from a given hardware component and derives several
description styles. The book also describes how to introduce the synthesis design cycle
into existing design methodologies and the standard synthesis environment.
Circuit Synthesis with VHDL concludes with a case study providing a realistic example of
the design flow from behavioral description down to the synthesized level.
Circuit Synthesis with VHDL is essential reading for all students, researchers, design
engineers and managers working with VHDL in a synthesis environment.
Elements of VHDL :
Language elements
Entity
Architecture
Sequential statements
Concurrent Statements
Component Instantiation
Packages and Libraries
Configuration and Generics
Attributes.
Level of Abstraction:
Different styles are adopted for writing VHDL code and many levels of abstraction are used
for describing electronic hardware.Any abstraction defines degree of detailness about design
specified in a particular description.There are three levels of abstraction-Algorithm-Register
Transfer level-Gate level.
Algorithm is nothing but set of instructions executed in sequence for performing some task.It
doesnot contain any clock or delay. Synthesis tols,like behavioural synthesis are available
which take algorithmic VHDL code as input.
DESIGN STEPS:
Step 1: Prepare an Requirement Specification
Step 2: Create an Micro-Architecture Document.
Step 3: RTL Design & Development of IP's

Step 4: Functional verification all the IP's/Check whether the RTL is free from Linting
Errors/Analyze whether the RTL is Synthesis friendly.
Step 4a: Perform Cycle-based verification(Functional) to verify the protocol behaviour of

the RTL
Step 4b: Perform Property Checking , to verify the RTL implementation and the
specification understanding is matching.
Step 5: Prepare the Design Constraints file (clock

definitions(frequency/uncertainity/jitter),I/O delay definitions, Output pad load
definition, Design False/Multicycle-paths) to perform Synthesis, usually called as an
SDC synopsys_constraints, specific to synopsys synthesis Tool (design-compiler)
Step 6: To Perform Synthesis for the IP, the inputs to the tool are (library file(for which
synthesis needs to be targeted for, which has the functional/timing information available
for the standard-cell library and the wire-load models for the wires based on the fanout
length of the connectivity), RTL files and the Design Constraint files, So that the
Synthesis tool can perform the synthesis of the RTL files and map and optimize to meet
the design-constraints requirements. After performing synthesis, as a part of the synthesis
flow, need to build scan-chain connectivity based on the DFT(Design for Test)
requirement, the synthesis tool (Test-compiler), builds the scan-chain.
UNIT 8
CMOS TESTING
Testing is one of the most expensive parts of chips

– Logic verification accounts for > 50% of design effort for many chips
– Debug time after fabrication has enormous opportunity cost
– Shipping defective parts can sink a company
NEED FOR TESTING:
The need of testing is to find out errors in the
application.
The good reasons of testing are
1) Quality Assurance.
2) Verification and validating the product/application
before it goes live in the market.
3) Defect free and user friendly.
4) Meets the requirements.
Logic Verification:
 Does the chip simulate correctly?

– Usually done at HDL level
– Verification engineers write test bench for HDL
• Can’t test all cases
• Look for corner cases
• Try to break logic design
 Ex: 32-bit adder
– Test all combinations of corner cases as inputs:
• 0, 1, 2, 231-1, -1, -231, a few random numbers
 Good tests require ingenuity.
Manufacturing Test:
 A speck of dust on a wafer is sufficient to kill chip
 Yield of any chip is < 100%
– Must test chips after manufacturing before delivery to customers to only
ship good parts
 Manufacturing testers are
very expensive
– Minimize time on tester
– Careful selection of test vectors
Observability & Controllability:
 Observability: ease of observing a node by watching external output pins of the

chip
 Controllability: ease of forcing a node to 0 or 1 by driving input pins of the chip
 Combinational logic is usually easy to observe and control

 Finite state machines can be very difficult, requiring many cycles to enter desired
state
– Especially if state transition diagram is not known to the test engineer.
Test Pattern Generation:
 Manufacturing test ideally would check every node in the circuit to prove it is not
stuck.
 Apply the smallest sequence of test vectors necessary to prove each node is not
stuck.
 Good observability and controllability reduces number of test vectors required for
manufacturing test.
– Reduces the cost of testing
– Motivates design-for-test.
Design for Test:
 Design the chip to increase observability and controllability
 If each register could be observed and controlled, test problem reduces to testing
combinational logic between registers.
 Better yet, logic blocks could enter test mode where they generate test patterns
and report the results automatically.
Scan:
CLK
 Convert each flip-flop to a scan register SCAN
Flop
SI Q
D
21. Known Gaps, If any
None
22. Discussion topics

UNIT 1:
WEEK 1:
1. Fabrication process.
2. PMOS fabrication.
3. CMOS fabrication.
WEEK 2:
1. NMOS enhancement mode transistor action.

2. BICMOS fabrication.
3. Difference b/w CMOS technology and Bipolar technology
UNIT 2:
WEEK 3:
4. IDS-VDS relation
5. Various pull-ups
6. CMOS inverter analysis.
WEEK 4:
4. Trans conductance (gm) & Figure of merit(w0).

5. NMOS Inverter.
6. Pass transistor
UNIT 3:
WEEK 5:
4. Stick diagram
5. Scaling of MOS circuit
6. NMOS and CMOS contacts.
WEEK 6:
4. Design rules and layout.
5. Scaling of MOS circuits
6. To design CMOS nand gate.
UNIT 4:
WEEK 7:
4. Switch logic
5. Driving large capacitance
6. Sheet resistance
WEEK 8:
4. Fan-in and fan-out.

5. Logic Gates and Other complex gates.
6. Wiring Capacitances.
UNIT 5:
WEEK 9:
4. Shifters.
5. ALU
6. Counters.
WEEK 10:
4. Adders.
5. Multiplier’s.
6. Comparators.
UNIT-6:
WEEK 11:
4. CPLD.
5. FPGA
6. Programmable array logic
WEEK 12:
4. Standard cell.
5. Programmable array logic.
6. PLA’S
UNIT 7:
WEEK 13:
4. Circuit design flow

5. Design capture tools
6. Test principles.
WEEK 14:
4. VHDL synthesis.
5. Simulation.
6. Layout design.
UNIT 8:
WEEK 15:
4. Chip-level test
5. System –level test
6. CMOS testing.
WEEK 16:
4. Need for testing.

5. Test principles
6. Layout design for improved test ability
23. Books / Material
Text Books
Essentials of VLSI circuits and systems – Kamran Eshraghian, Eshraghian
Text-1.
Dougles and A. Pucknell, PHI,2005 Edition.
Principles of CMOS VLSI Design - Weste and Eshraghian, Pearson Education,
Text-2.
1999.
Suggested / Reference Books
Modern VLSI Design - Wayne Wolf, Pearson Education, 3rd Edition, 1997.
Ref-1.
Ref-2. VLSI Technology – S.M. SZE, 2nd Edition, TMH, 2003.

Ref-3. Digital Integrated Circuits - John M. Rabaey, PHI, EEE, 1997.
Web Sites
a. www.cmosedu.com
b. www.wikkipedia.com
c. www.btechadda.com
d. www.wikibooks.org
* For the topics Internal & external Circlips, Gaskets and seals (stationary and rotary)
24. Quality Control Sheets
a. Course ebd Survey

Hard Copies need to be attached
b. Teaching Evaluation
Hard Copy
25.Students List
26.Group-Wise students list for discussion topics
Need to form batches in Class room with student interest
END

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VLSI Design

Branch: ECE Version No : 01

Classification status (Unrestricted / Restricted )

Prepared by : 1) Name : G. Sree Lakshmi 1) Name :K.V.S.Nagaraju

INTRODUCTION : Introduction to IC Technology – MOS, PMOS,

VLSI CIRCUIT DESIGN PROCESSES: VLSI Design Flow, MOS

Suggested / Reference Books

Ref-2. VLSI Technology – S.M. SZE, 2nd Edition, TMH, 2003.

4. Mission of the Department

5. Program Educational Objectives of B. Tech (ECE) Program :

I. To prepare students with excellent comprehension of basic sciences, mathematics

5. Program Outcomes of B.Tech ECE Program:

1. An ability to apply knowledge of Mathematics, Science, and Engineering to solve

6. Course Objective and Outcomes

 To understand the steps involved in IC fabrication.

In this course, we will study the fundamental structures of VLSI Systems at

While learning how to construct fundamental VLSI systems structures from

1. Introduction to CMOS Design. Rabaey et al., Chapter 1.

2. CMOS Device Fabrication Processes. Rabaey et al., Chapter 2.

3. CMOS Transistor Device Models. Rabaey et al., Chapter 3.

4. CMOS Interconnect Wire Models. Rabaey et al., Chapter 4.

5. CMOS Inverter Model. Rabaey et al., Chapter 5.

6. Combinational and Sequential Design. Rabaey et al., Chapters 6 & 7 (selected

MOSFET concepts, Basics of STLD

9. Instructional Learning Outcomes

Students should be able to:

UNIT II: VLSI circuit design processes

UNIT III: Gate level design

UNIT V: Programable Logic Devices and CMOS Testing

S.No. Course Outcome POs

4 Apply design rules to get Layout of IC. PO5

5 Demonstrate semiconductor IC design such as PO13

6 Design various forms of memories. PO3,PO4,PO12

11. Class Time Table:

12. Individual Time Table

13.Lecture Shedule with methodology being used

GEETHANJALI COLLEGE OF ENGINEERING & TECHNOLOGY

CHEERYAL (V), KEESARA (M), RR District.

Department of Computer science and engineering

13.1 Micro Plan:-

Subject: VLSI Design Name of the Faculty: G Sreelakshmi

Unit Regular / Teaching aids used

22 Tutorial class on unit 2 -revision Regular

32 Switch logic, Alternate gate circuits Regular BB

51 Tutorial class on unit 7 -revision Regular

52 8 CMOS TESTING : CMOS Testing Regular BB

Unit Regular / Teaching aids used

31 4 GATE LEVEL DESIGN : Logic Gates and Regular BB

32 Switch logic, Alternate gate circuits Regular BB

Subject: VLSI Design Name of the Faculty: M Krishna Chaitanya

Unit Regular / Teaching aids used

22 Tutorial class on unit 2 -revision Regular

31 4 GATE LEVEL DESIGN : Logic Gates and Regular BB

32 Switch logic, Alternate gate circuits Regular BB

51 Tutorial class on unit 7 -revision Regular

52 8 CMOS TESTING : CMOS Testing Regular BB

13.2. Subject Contents

14. Detailed notes

Synthetic detail of an integrated circuit through four layers of planarized copper

The second n-type layer (25µm=1mil) where all active and

The third layer of IC fabrication is Diffusion process. Active and

1. Typical value of Resistance 10Ω < R < 30 kΩ & Capacitance <30pf.

BASIC ELECTRICAL PROPERTIES