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Transactions on Circuits and Systems II: Express Briefs

A 14 bit, 30 MS/s, 38 mW SAR ADC Using


Noise Filter Gear Shifting
Martin Krämer Student Member, IEEE, Erwin Janssen Member, IEEE, Kostas Doris Member, IEEE and Boris
Murmann Fellow, IEEE

Abstract—We present a SAR ADC that employs a comparator there is no latch decision time sensing. Our design uses an
with time varying noise performance, realized by changing the alternative solution that is similar to [6], but we report
integration time of a Gm-C preamplifier. This approach allows us significantly higher speed (15 times faster) and SNDR (~19
to relax precision and enhance speed during non-critical dB). However, to be fair the solution in [6] uses considerably
decisions, leading to an aggregate speedup of 22% compared to a
lower power than our solution.
conventional design. The ADC operates at 30 MS/s, achieves a
peak SNDR of 77.2 dB and consumes 38 mW from 1.2 V/2.5 V The approach described in this paper also switches between
supplies, corresponding to a Schreier FOM of 163.1 dB (161.6 dB two noise levels (as illustrated in Fig. 1), but it employs a
at Nyquist). The proof-of-concept converter is implemented in a comparator whose noise is varied by changing the integration
40-nm LP CMOS process and occupies 0.24 mm2. time of its Gm-C preamplifier (noise filter gear shifting). This
shortens the sub-cycles in the high noise phase and thus leads
Keywords— Analog-to-digital conversion, CMOS, successive to an overall speed-up. The described proof-of-concept
approximation register, redundancy. implementation re-uses a previous design [3] and achieves a
I. INTRODUCTION speed-up of 22%. We conjecture that further improvements
are possible using multiple noise settings and a wider noise
The successive approximation register (SAR) ADC is an tuning range (which was limited due to re-use).
attractive architecture for high-speed, high-resolution
digitization with low latency. Recent designs have shown that
several tens of MS/s and an effective number of bits (ENOB)
greater than 11 are achievable with good power efficiency [1-
3]. In such ADCs, the comparator is the most critical block
due to the simultaneous requirement for high speed and low
noise. Therefore, improving the comparator and its use within
the SAR loop is critical for further advancements.
One promising direction is to exploit redundancy in the
SAR algorithm. As explained in [4-5], low-noise comparisons
are only needed in the last few decisions (where little or no
redundancy is present). In order to benefit from this feature,
one must design a comparator whose noise can be
dynamically adjusted in return for improvements in energy Fig. 1. Successive approximation cycle1. Dashed line: conventional approach
with low noise. Solid line: Cycle using noise filter gear shifting.
and/or speed. One possibility is to use two comparators, one
with relaxed noise for the MSBs, and a low-noise version for The remainder of this paper is structured as follows. In
the LSBs [4]. This primarily helps reduce energy, but comes Section II, we introduce the overall architecture and describe
with overhead in complexity, additional capacitance at the further details of the noise gear shifting approach. In Section
charge conservation node (resulting in a noise penalty) and the III, we discuss circuit implementation details, followed by
need for extra redundancy to absorb the offset mismatch measured results in Section IV. Section V provides a
between the two comparators. The 40 kS/s SAR ADC of [5] conclusion.
overcomes these issues by using a single comparator that is
fired multiple times during critical decisions, thereby II. ADC ARCHITECTURE
achieving low noise on demand via majority voting. Fig. 2(a) shows the ADC block diagram. The design is
Unfortunately, this technique is incompatible with high-speed based on [3] and uses a current-steering feedback DAC that
design, since the critical decisions are detected by measuring closes the SAR loop via an analog multiplexer (MUX). The
the latch decision time. In a high-speed converter with latch feedback DAC uses two redundant bits so that the ADC can
time constants of a few picoseconds, the time resolution tolerate comparison errors due to noise and incomplete DAC
needed to distinguish between critical/non-critical decisions settling (see Appendix) during the MSB cycles of the SAR
becomes impractically small. loop. The main differences between the present design and [3]
The aforementioned issues are addressed in the 7-10b, 2 are: (1) The input buffer was removed and (2) the gear shifting
MS/s ADC of [6]. This design uses a programmable
integration capacitance in the comparator’s dynamic pre- 1
The superimposed noise represents noise from the comparator referred to the
amplifier, which leads to a nearly constant input offset and successive approximation waveform for illustrative purposes. In reality, this
noise is added only after the signal enters the comparator.
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2016.2554858, IEEE
Transactions on Circuits and Systems II: Express Briefs

was added to modulate the comparator noise. In essence, this III. CIRCUIT DESIGN
means that the present design was optimized for higher SNR Fig. 3 expands on implementation details of the converter.
and lower power, whereas the design of [3] was mainly aimed The input signal (1.8 Vpp-diff) is acquired in 6.6 ns (20 % of the
at easing the input drive requirements (which also helped cycle) via bottom-plate sampling (ɸ1 switches, simple NMOS
maximize the SFDR) and maximizing speed at the expense of devices). The sampling instant (falling edge of ɸ1e) is derived
noise. from an external 300 MHz clock to achieve low sampling
jitter, while the SAR loop is self-timed [10]. The MUX
switches controlled by ɸ1 are bootstrapped [11]. The
bootstrapping helps minimize nonlinear tracking errors in the
signal path, while it is needed in the DAC path (during ɸ1
phase) to maintain small Ron for low noise (Ron = 10Ω). Even
though the DAC noise is filtered by the G m-C pre-amplifier, a
relatively low DAC output resistance (RDAC 100 Ω) must be
maintained to achieve the SNR level targeted in this design.

Fig. 2. (a) ADC block diagram. (b) Timing diagram for the low-SNR MSB
decisions (left) and high-SNR LSB decisions (right).

The key innovation of this design lies in the timing of the


comparator and its Gm-C pre-amplifier, illustrated in more
detail in Fig. 2(b). At the start of each conversion cycle, the
output of the Gm-C pre-amplifier is reset via ɸres and the DAC
input bits are updated. The duration of this reset phase is fixed
and defined via a delay line (T res in Fig. 2(a), ~600 ps). After
reset, the Gm-C stage integrates its input for a time which
depends on the state of the SAR algorithm (programmable
delay line Tint). During the MSB cycles 1-9, the integration
time is short (Tint0 = 0.85 ns), yielding a low SNR at the output
of the Gm-C stage. Any decision errors caused by the extra
noise are absorbed by the converter’s redundancy.
For the critical LSB decisions in cycles 10-16, the
integration time is increased (Tint1 = 1.6 ns) to improve the
SNR. As shown in [7-9], the input-referred noise bandwidth of
the switched Gm-C stage is given by
Fig. 3. ADC implementation details. (a) Overall circuit with key component
(1) values and supply voltage domains. (b) Implementation of the Gm cell.

provided that Tint is much smaller than the RC time constant The feedback DAC uses a segmented current-steering
at node Vx. Thus, the input–referred noise power is topology (8b MSB and 7b LSB) and operates from 2.5 V to
approximately halved (3 dB improvement) when we gear-shift accommodate triple-cascoded current cells for high DC
from Tint0 to Tint1. At the end of the above-described linearity (>90 dB). Dynamic nonlinearities are not a
integration phase, the latch is fired to detect the polarity of Vx, significant issue, since the DAC has time to settle. Also, DAC
which determines the output bit for the present cycle. The glitches are suppressed since they occur during the loop’s
SAR conversion then proceeds to the next cycle as usual. reset phase. The DAC uses non-binary weights to incorporate
two bits of redundancy. All currents are derived from an on-

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2016.2554858, IEEE
Transactions on Circuits and Systems II: Express Briefs

chip bandgap reference and the DAC’s MSB weights are and DAC (CF) decoupling capacitors (see Fig. 53). To evaluate
calibrated at start-up using the LSB section [2, 12]. the noise filter gear shifting, we measured the ADC’s SNR as
Extra care was taken to ensure that the DAC bias circuit a function of integration time (see Fig. 6). In this
does not contribute a significant amount of noise. A 50 pF measurement, the same Tint is used for all cycles and the ADC
filter capacitor (CF) is introduced to filter the bias noise (see therefore runs at reduced speed (20 MS/s). As expected, we
Fig. 3(a)), limiting its contribution to 10% of the total noise see an SNR change as Tint is swept between the two extreme
for a full-scale DAC output (see [13] for a detailed analysis). values (Tint0 = 0.85 ns and Tint1 = 1.6 ns). Notice that the
Fig. 4 shows the schematic of the comparator latch, which min/max integration times, for us, are limited by the delay line
uses the same architecture as described in [14]. Since the noise implementation 4 . The observed change is consistent with
performance of such a latch is poor, it must be preceded by a halving of the comparator noise for the large integration time
sufficiently large amount of voltage gain in high-resolution setting (Tint1). Note that the measured overall ADC SNR
SAR ADCs. In our design, this gain is provided by the G m-C changes by less than 3 dB due to the other noise contributors
preamplifier during integration and is fundamentally bounded (kT/C sampling noise, etc.). For more details see [13].
by the GmRo product of the circuit (see Fig. 3(a)). There are
two design options for achieving a large G mRo product. One is
to maximize Ro using cascoding and/or gain boosting, but this
is difficult with short channel devices and low VDD. Instead,
we boost Gm using four wideband stages (see Fig. 3(b)) with
an aggregate voltage gain of approximately 80. The
intermediate nodes in these stages settle together with the
DAC during Tres (~600 ps). The fifth stage is terminated with
a large resistor so that the time constant at the output is much
larger than the integration time (as required for (1) to hold).
Finally, it should be noted that due to the large voltage
gain of the Gm-C pre-amplifier, the kT/Cint reset noise
(introduced when res goes low) becomes negligible when
referred to the input. This term is therefore also ignored in the
Fig. 5. Die photograph.
derivation of (1).

Fig. 4. Schematic of the comparator latch. Fig. 6. SNR vs. integration time (Tint).

The Gear shifting is implemented on chip and uses the SAR The SNDR versus fs plot of Fig. 7 illustrates the speed
register to identify the 10th decision2. The programmable delay advantage gained by the gear shifting. Using T int1 for all cycles
uses an inverter chain with different taps to access the different (dashed line) limits the maximum speed to 24.5 MS/s, while
delay times. A digital MUX is used to select the wanted delay gear shifting between Tint0/Tint1 (solid line) yields 30 MS/s (22
value; once the 9th cycle is completed, the MUX selects the % higher). We observe that there is no notable difference in
longer delay. the SNDR.
IV. MEASUREMENT RESULTS It should be emphasized that the speed of our previous
design [3] drops to 25 MS/s when one wants to achieve the
The ADC was fabricated in a 40 nm LP CMOS process
same SNR. The goal of this paper is to maximize SNR and
and occupies 0.236 mm2 including the supply (C2.5V and C1.2V)
3
The layout of our chip is nearly identical to [3]. Only the buffer was
2
The gear shifting position was not optimized. The DAC is segmented, bypassed in this design via metal mask changes and the gear shifting was
providing a natural decision to switch the gears at that point. In order to added.
4
implement the DAC calibration, we ensured additional redundancy at this One general lower limit for Tint0 is set by the maximum allowed noise, which
point and hence we had enough redundancy to recover from the noise as well. one has to recover from using the designed redundancy.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2016.2554858, IEEE
Transactions on Circuits and Systems II: Express Briefs

break the noise speed tradeoff, hence we used the highest T int1 low frequencies and 161.6 dB at Nyquist. Table I compares our
time for the gear shifting. Notice that the design in [3] already design with other state-of-the-art designs.
uses the shortest integration time (T int0) for all cycles, so it was Compared to our previous work [3], the present design
not possible to achieve 35 MS/s and increasing the SNR. The achieves higher SNR and lower power, at the expense of a
5 MS/s difference is the price to be paid for not having a small reduction in speed and SFDR. The loss in speed is due to
shorter Tint0. the large integration time used for the critical decisions, which
Fig. 8 summarizes measurements with the gear shifting is key for achieving the reported SNDR. Figure 10 shows a
activated (at 30 MS/s) and Fig. 9 shows the output FFT for a 1 speed-resolution scatter plot for SAR ADCs, extracted from the
MHz full-scale input. The ADC achieves a low frequency data set of [16].
SNDR of 77.2 dB, which degrades by 1.5 dB at Nyquist due
to distortion. The SNR loss across input frequency is only TABLE I. Performance comparison.
about 0.5 dB. This
[1] [2] [3]
Work
Process (nm) 40 65 28 40
Resolution (bits) 14 14 15 14
Sampling Rate (MS/s) 30 80 100 35
ADC Input Cap [pF] 3.5 4 1.25 0.2
SNDR at LF/Nyq (dB) 77.2 73.6 71 75
71 6 74
75.7
SNDR at Nyq. (dB) .3 7.1 .4
FOMS* at LF (dB) 163.1 164.7 169 160.1
Fig. 7. SNDR vs. sampling frequency (fs) using fixed Tint = Tint1 (dashed) and 16 1 15
161.6
with gear shifting between Tint0/Tint1 (solid). FOMS* at Nyq. (dB) 1.8 65.1 9.5
SFDR up to Nyq. (dB) 84 80 76 90
Total Power (mW) 38 35.1 8 54.5
Supply [V] 1.2/2.5 1.2/1.8 1/1.8 1.2/2.5

*FOMS = SNDR(dB)+10log((fs/2)/P)

Fig. 8. Measured SFDR, SNR and SNDR vs. fin.

Fig. 10. SAR ADC performance survey using data from [16].

V. CONCLUSION
This paper described a design technique that helps alleviate
the stringent tradeoff between comparator noise and speed in
high-speed, high-resolution SAR ADCs with redundancy. By
shortening the integration time of the G m-C preamplifier
Fig. 9. Measured output FFT. during non-critical decisions, we demonstrated a 22% speed-
up compared to the standard design configuration with the
The ADC consumes a total power of 38 mW excluding the same SNDR.
bandgap and digital I/Os. This number includes 27.3 mW from The tuning range for the comparator integration time in
the DAC and the remainder is due to the comparator, SAR this proof-of-concept demonstration was limited to a factor of
logic, CML clock buffer and clock distribution. The design two. Future designs will likely be able to benefit from wider
achieves an SNDR-based Schreier FOM [15] of 163.1 dB for range and could consider more than two integration time

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2016.2554858, IEEE
Transactions on Circuits and Systems II: Express Briefs

settings. Furthermore, the gear shifting point can be also


subject to further optimizations.
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