IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO.
2, FEBRUARY 2016
A 65 nm Programmable ANalog Device Array
(PANDA) for Analog Circuit Emulation
Naveen Suda, Student Member, IEEE, Jounghyuk Suh, Nagib Hakim, Member, IEEE,
Yu Cao, Senior Member, IEEE, and Bertan Bakkaloglu, Senior Member, IEEE
Abstract—Reconfigurable analog/mixed signal (AMS) plat-
forms in scaled CMOS technology nodes are gaining importance
due to the increased design cost, effort and shrinking time-to-
market. Similar to field programmable gate arrays (FPGA) for
digital designs, a Programmable ANalog Device Array (PANDA)
provides a flexible and versatile solution with transistor-level
granularity and reconfiguration capability for rapid prototyp-
ing and validation of analog circuits. This paper presents de-
sign and synthesis methodology of a PANDA design on 65 nm
CMOS technology, consisting of a 24 × 25 cell array, recon-
figurable interconnect, configuration memory and serial pro-
gramming interface. To implement AMS circuits on the PANDA
platform, this paper further proposes a CAD tool for technology
mapping, placement, routing and configuration bit-stream gen-
eration. Several representative building blocks of AMS circuits,
such as amplifiers, voltage and current references, filters, are
successfully implemented on the PANDA platform. Dynamic re-
configuration capability of PANDA is demonstrated through input
offset cancellation of an operational amplifier using an FPGA in a
closed loop. Initial measurement results of PANDA implemented
circuits demonstrate the potential of the methodology for rapid
prototyping and hardware validation of analog circuits.
Index Terms—Amplifiers, analog processing circuits, design
automation, design methodology, field programmable analog
arrays, field programmable gate arrays, filters, reconfigurable
architectures.
I. I NTRODUCTION
C MOS SCALING in sub-100 nm regime has provided
tremendous opportunities to digital circuit designers in
terms of transistor speed and integration density. On the other
hand, it poses serious challenges to analog/mixed signal (AMS)
system design due to the degradation of transistor intrinsic gain,
reduced voltage headroom, and increased process variations.
This leads to the growing design trend where architectural
improvements with additional analog/digital feedback circuits
are required along with primary analog circuits to compen-
sate for device-level non-idealities. Comprehensive validation
Manuscript received June 30, 2015; revised October 16, 2015; accepted
December 5, 2015. Date of publication January 25, 2016; date of current
version March 16, 2016. This research work is supported by Intel, Santa
Clara, CA 95054 USA. This paper was recommended by Associate Editor
N. Krishnapura.
N. Suda, Y. Cao, and B. Bakkaloglu are with the School of Electrical
and Computer Engineering, Arizona State University, Tempe, AZ 85281 USA
(e-mail: nsuda@asu.edu; ycao@asu.edu; bertan@asu.edu).
J. Suh is with NXP Semiconductors, Tempe, AZ 85284 USA (e-mail:
sjounghy@asu.edu).
N. Hakim is with Intel Architecture Group, Santa Clara, CA 95054 USA
(e-mail: nagib.hakim@intel.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2015.2512718
1549-8328 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
181
of such complex systems by simulation is time-consuming
and impractical, especially in this era of shrinking time-to-
market in consumer electronics industry. Furthermore, high
manufacturing costs in advanced nodes emphasize the need
of rapid-prototyping platforms for AMS systems. In this con-
text, reconfigurable analog platforms, analogous to digital field
programmable gate arrays (FPGA), would be crucial in rapid-
prototyping and validation of new designs before an expensive
tape-out.
Previous academic and industrial efforts focused on field
programmable analog arrays (FPAA) with a wide range of
configurable analog blocks (CAB) ranging from coarse grained
macros such as operational amplifiers [1], operational transcon-
ductance amplifiers [2]–[4], switched capacitor circuits [5],
ADCs and DACs [6] to medium grained primitives such as
differential pairs and transconductors [7], [8]. FPAAs with
transistor-level CABs known as field programmable transistors
arrays (FPTAs) are explored in [9], [10] for evolvable hardware
applications. Some researchers developed FPAAs with CABs
consisting of a combination of coarse-grained macros along
with programmable transistors using floating-gate transistor as
reconfiguration switches [11]–[15]. However, due to the wide
variety of analog circuits such as bias circuits, amplifiers, filters,
switching circuits, oscillators, etc., it is not possible to imple-
ment an arbitrary analog function using a generic set of CABs.
Hence a transistor-level reconfigurable analog platform, named
Programmable ANalog Device Array (PANDA), is developed
in [16], which enables rapid prototyping and validation of AMS
circuits across different technology nodes.
This work extends the previous simulation work on PANDA
[17] to silicon implementation of the full system including an
array of PANDA cells, reconfigurable interconnect and com-
puter interface for configuration. To map AMS circuits onto
the new platform, we further customized a set of computer-
aided design (CAD) tools for design partitioning, technology
mapping, placement, routing, and configuration bit-stream
generation. Despite the mature FPGA CAD research, digital
methodologies do not suit well for PANDA because of the in-
trinsic differences in requirements of analog and digital circuits.
Hence, a new CAD tool, PANDA-PRO is developed for im-
plementation of AMS circuits on the PANDA platform, which
overcomes the shortcomings of previous digital methodologies.
This paper mainly focuses on the silicon demonstration of
the PANDA platform in 65 nm CMOS technology, CAD tool
development for design implementation of AMS circuits on
the platform and concludes with initial measurement results of
several circuit building blocks implemented on the platform.
182 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 2, FEBRUARY 2016

Fig. 1. Architecture of PANDA. (a) Island-style reconfigurable interconnect similar to FPGAs. (b) A typical tile consisting of a PANDA cell connected to the
reconfigurable interconnect via connection blocks (CB), switch blocks (SB). A PANDA cell with 3-transistor stack is shown as an example.

PANDA inherits the island-style architecture from FPGAs as

shown in Fig. 1(a), where each cell is connected to the routing
channels through transmission-gate based switches, as shown
in Fig. 1(b). Interconnect parasitics from switches and routing
channels limit the maximum frequency of the circuits imple-
mented on PANDA. Nevertheless, low frequency applications
such as reconfigurable multi-sensor front-end circuits, audio
processing applications, etc., are appropriate candidates that
fully utilize the reconfiguration capabilities of PANDA. More-
over, dynamic reconfiguration capability of PANDA, which
enables on-the-fly configuration of the cell size and their con-
nectivity, provides new opportunities for rapid-prototyping and
validation of self-calibrating and adaptive circuits which cost
considerable amount of simulation time because of analog-
digital co-simulation.
Fig. 2. (a) Programmable NMOS transistor using digital controls (b0 , b1 , b2 )
The rest of the paper is organized as follows. In Section II, (b) Target analog transistor mapped to either 1-transistor PANDA cell (left) or
an overview of PANDA architecture and the system implemen- 3-transistor PANDA cell (right) based on ID , Rout , and Gm requirements.
tation in 65 nm CMOS technology is presented. Section III
presents the design flow of AMS circuits on the platform, TABLE I
T RANSISTOR S IZE D ISCRETIZATION
including customization of placement and routing algorithms
for PANDA. Section IV presents initial measurement results
of circuits implemented on PANDA. Section V presents ap-
plications and limitations of this methodology and Section VI
concludes the paper by comparing our work with prior FPAAs.

II. OVERVIEW OF THE 65 nm PANDA S YSTEM

Fig. 1 shows the block diagram of the PANDA system, which
consists of an array of reconfigurable cells along with island-
style interconnect and segmented routing channels similar to
FPGAs [18]. Since each cell can be connected to any other cell
through the reconfigurable connection block (CB) and switch
blocks (SB), this platform is versatile for implementation of any
AMS circuit. To demonstrate the design potential of PANDA on
silicon, a full system consisting of 24 × 25 array of program-
mable cells, reconfigurable interconnect, configuration memory
and serial interface is fabricated in 65 nm CMOS technology.
A. PANDA Cells
Implementation of an AMS circuit on PANDA platform
requires mapping of each transistor to a PANDA cell to match
the drain current (ID ), output resistance (Rout ) and transcon-
ductance (Gm ) [17]. To implement any generic AMS circuit,
PANDA cells comprise of transistors with different widths
and lengths. For practical implementation, transistor widths are
discretized using binary weighted transistors (1×, 2×, and 4×)
in parallel to a fixed transistor (Fx) as shown in Fig. 2(a), such
that the effective transistor width can be configured from Fx
to Fx + 7x using the digital controls (b0 , b1 , b2 ). 6 different
types of PANDA cells each with different fixed and variable
programmable width transistors are designed to achieve an
effective width coverage of 80 nm to 10 μm with a maximum
discretization error of 10%. The transistor sizes in these 6 cell
types are shown in Table I. If a circuit demands for more
accuracy, PANDA cells with coarse width transistors can be
used in parallel to cells with fine width transistors.
SUDA et al.: A 65 nm PROGRAMMABLE ANALOG DEVICE ARRAY (PANDA) FOR ANALOG CIRCUIT EMULATION 183

TABLE II C. Routing Architecture

S UMMARY OF PANDA C ELL T YPES
PANDA utilizes the island-style routing architecture in con-
junction with segmented routing architecture [18] from FPGAs,
where each cell connects to any other cell in the array through
reconfigurable interconnect. Each tile consists of a PANDA
cell, connection blocks (CB), switch block (SB), and configura-
tion memory. Connection block is required for each terminal of
the PANDA cell, to connect a cell to the routing tracks. Switch
blocks are located at intersection of horizontal and vertical
tracks to connect a source track to destination track(s). Each tile
is carefully designed so that the configuration memory required
To map long-channel transistors that have higher output
for configuring the transistor widths, CB and SB connectivity,
resistance, transistors T1 is stacked to T2 to form a cascode
is present in the same tile.
pair as shown in Fig. 2(b). Transistor T3 with its gate connected
The main drawback of island-style architecture with routing
to VDD is added to the stack for flexibility in matching ID ,
segments that extend only one block length is that a signal from
Rout , and Gm . Two variants of transistor length L = 60 nm
a cell to other cell which is “n” blocks away has to pass through
and L = 120 nm are provided in the platform for flexibility
“n” SB switches and 2 CB switches. This degrades/destroys
to map a wide range of target transistors. To add versatility to
the analog circuit functionality for large “n,” because of the
the platform, programmable resistors, capacitors and parasitic
resistance of the each switch along the path. Hence we use
BJTs are also incorporated into the array. The different types of
segmented routing similar to FPGAs, where each routing track
PANDA cells, their sub-types and number of cells of each type
extends to more than one block length before ending at a
present in the array are summarized in Table II.
SB. This reduces the number of passing SB switches when
To demonstrate the transistor-level I-V characteristic match-
connecting two distant cells. In the current implementation,
ing between a target transistor and PANDA cell, an NMOS
routing tracks with segments which extend up to 16 blocks are
transistor of W/L = 560 nm/60 nm is mapped to a 1-transistor
provided for parasitic reduction while routing. Routing tracks
PANDA cell at bias conditions of VG = 0.4 V, VD = 0.5 V,
with smaller segment lengths are also provided in the platform
and VS = 0 V. Measured I-V characteristics of the mapped
for flexibility in routing when connecting nearby cells.
PANDA cell compared to the simulated characteristics of the
Switch block (SB) is situated at the intersection of horizontal
target transistor is shown in Fig. 3(a). ID − VD characteristics
and vertical routing tracks and connects an incoming track to
show a close match at the nominal bias of VG = 0.4 V. ID −
some specific outgoing tracks based on the architecture of the
VG characteristics match till VG = 0.5 V, but after that voltage
switch block. The number of tracks to which each incoming
drop across the routing switches increases which reduces the
track can connect is known as switch block flexibility (Fs),
effective VD at the transistor drain terminal.
where Fs = 3 in typical FPGAs. There are different switch
Fig. 3(b) shows the measured I-V characteristics of a
block architectures available in FPGA literature, such as dis-
3-transistor PANDA cell which maps to a long-channel tran-
joint [19], universal [20], Wilton [21] and Imran switch block
sistor of W/L = 560 nm/260 nm at bias conditions of VG =
[22] each having its own advantages/disadvantages. Imran
0.6 V, VD = 0.6, VS = 0 V. In Fig. 3(b) ID − VG characteris-
switch block is used in PANDA, as it is area efficient and gives
tics, the change in ID with VD is minimal due to the high output
best routable designs for segmented routing architecture [22].
resistance of the long-channel transistor.
The number of tracks to which connection block connects, is
called connection block flexibility (Fc), which should be half
B. Reconfiguration Switches the total number of tracks for best routability and area efficiency
[18]. Hence the connection block in PANDA is designed such
Similar to FPGAs, transmission gate (TG) based switches are
that it connects to 7 routing tracks among the total of 13 tracks.
used in the reconfigurable routing, as they can easily be con-
The extracted parasitic resistance and capacitance of a rout-
figured by changing the memory locations that drive the gates
ing line that connects two adjacent cells are 7 Ω and 1 fF,
of the TG. However, different from the switches in FPGAs,
respectively, which are considerably less than those of the
switches in the PANDA platform carry DC current, which
switches. The total capacitance associated with a routing line
may induce voltage drop affecting the DC bias conditions and
can be evaluated as sum of parasitic capacitance of all the
may also destroy the circuit functionality. Increasing the TG
switches connected to that line and the capacitance of the rout-
size reduces the resistance, but it also increases the parasitic
ing segment itself. For example, the total estimated capacitance
capacitance, which in-turn decreases the maximum operating
on a long routing line that extends to 16 blocks is 216 fF,
frequency of the platform. Hence TG sizing is critical for the
whereas the total capacitance on a short line that connects
overall functionality and performance of the platform. We sized
adjacent cells is 21 fF.
up the NMOS transistor to 3 μm/60 nm and PMOS transistor
to 6 μm/60 nm to reduce the maximum ON resistance of TG
D. Configuration Memory and Infrastructure
switch to 400 Ω, whereas the approximate capacitance of the
switch is 10 fF. External I/Os are also connected to the internal Memory required to store the PANDA cell sizing, connection
routing tracks through the same reconfiguration switches. block and switch block connectivities is placed in each tile.
184 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 2, FEBRUARY 2016

Fig. 3. Measured I-V characteristics of (a) PANDA cell with effective W/L = 8 × 80 nm/60 nm emulating a target transistor of W/L = 560 nm/60 nm
mapped at nominal VG = 0.4 V, VD = 0.5 V, VS = 0. (b) 3-transistor PANDA cell with T1 and T2 as 230 nm/120 nm and T3 is OFF emulating an analog
transistor of W/L = 560 nm/260 nm at nominal VG = 0.6 V, VD = 0.6 V, VS = 0.

occupies a total area of 3.46 mm2 including the ESD protection

diodes and I/O bonding pads.

III. C IRCUIT I MPLEMENTATION M ETHODOLOGY

Implementation of a circuit on PANDA platform requires a
wide range of CAD tools for design partitioning, cell mapping,
placement, routing, and bit-stream generation. Although the
FPGA CAD tools are mature and widely used for digital circuit
implementation, they do not suit well for PANDA because of
the following shortcomings associated with them in comparison
with analog synthesis.
Fig. 4. Die micrograph of the 65 nm PANDA chip.

• Heterogeneity: All the logic blocks in typical digital

Byte-wise addressable memory is distributed into two columns
in each tile for ease in routing of the memory outputs to
the reconfiguration switches. Although the cells have different
dimensions, in order to maintain the uniform array structure,
all the tiles are designed to have uniform width while two
tile heights are chosen based on the number of reconfiguration
switches. This gives different ratios of area of actual transistor
to that of the entire tile as 0.05% for the smallest cell and 17%
for the largest cell. This shows that over 80% of the total chip
area is occupied by the reconfigurable routing fabric.
To transfer configuration bit-stream from computer to the
PANDA platform a customized serial peripheral interface (SPI)
protocol is used. A SPI slave along with row/column address
decoding logic, data/address buffers is incorporated into the
system to help in reconfiguration. The micrograph of the
PANDA die fabricated in a standard 65 nm digital CMOS
technology with 1-poly and 8 metal layers is shown in Fig. 4. It
FPGAs are identical, whereas PANDA has heterogeneous
cells with different transistor sizes, resistors, capacitors,
etc. Recent FPGAs have heterogeneous blocks such as
memory, arithmetic units along with conventional logic
blocks and there are also tools available for such archi-
tectures [23]. However, these tools are not customized for
mapping analog circuits to PANDA.
• Routing Parasitics: Parasitics from routing not only de-
grade circuit performance as that happens in digital
FPGAs, but can also completely destroy the functionality
of analog circuits because of the DC and AC voltage drops
in switches. Hence performance degradation because of
interconnect fabric must be fully addressed at each step
of placement and routing.
• Special Requirements for Analog Circuits: The new
analog synthesis tool should be aware of different con-
straints such as circuit topology, matching and sensitive
SUDA et al.: A 65 nm PROGRAMMABLE ANALOG DEVICE ARRAY (PANDA) FOR ANALOG CIRCUIT EMULATION
Fig. 5. PANDA-PRO CAD tool flow.
nodes, etc., which are specific for analog circuits, but not
required in FPGAs.
• Design Scale: Modern FPGAs typically have 0.1–
4 million reconfigurable logic cells; hence the CAD tools
need to trade-off the quality of final solution for config-
uration speed. In a typical analog circuit which only has
100–1000 transistors, the tool can afford multiple place-
ment and routing iterations to achieve the target perfor-
mance and related accuracy.
A new CAD tool, PANDA-PRO is developed overcoming
the above shortcomings of FPGA CAD tools, to implement
AMS circuits on PANDA platform. The steps involved in
PANDA-PRO starting from mapping to bit-stream generation
are summarized in Fig. 5.
A. Automatic Mapping
Mapping of the input design to PANDA cells is the fun-
damental and critical step in the implementation. First, the
input design SPICE netlist is hierarchically partitioned and
operating bias conditions of each transistor are extracted. From
the circuit connectivity generic constraints such as input dif-
ferential transistors and matched pairs are extracted. These
constraints will be used in placement and routing phase. Then,
each transistor is mapped to the PANDA cells for the extracted
voltage bias conditions. Mapping involves sizing the transistors
of the PANDA cell to match its I-V characteristics to that of
the target transistor, thereby matching ID , Gm , and Rout [17].
First, a coarse search on the discrete-sized 1-transistor and
3-transistor PANDA cell types in Table II is performed and the
cell types which yield smaller error in ID , Gm , and Rout with
respect to target transistor are selected for a detailed-search. In
the detailed search, the transistor sizes in the selected PANDA
cells are iteratively changed in the direction to reduce the error
in ID , Gm , and Rout . The PANDA cell that achieves least error
is selected as the final solution for that target transistor. Trans-
mission gate switches are included into the cell in mapping
stage, so that their impact is compensated during cell sizing.
The detailed methodology for mapping of each transistor to
PANDA cells is presented in [17].
185
Fig. 6. Pseudo-code for placement algorithm based on simulated-annealing.
B. Placement
PANDA-PRO placer is based on simulated-annealing [24],
similar to traditional FPGA placers [25]; however the main
differences being the heterogeneous cell types and additional
design constraints of analog circuits. Simulated-annealing is a
probabilistic global optimization method, emulating a physical
process called annealing, where a material at high temperature
(T) is gradually cooled to achieve a minimum energy state.
PANDA-cell mapped netlist is given to the placement tool
which minimizes the placement cost given in the following
equation.

N ets
Placement cost = wtk (|xi − xj | + |yi − yj |) (1)
k
where wtk is the weight assigned to each net, (xi , yi ) and
(xj , yj ) are the coordinates of source and every destination cells
for that net. Critical nets can be assigned higher weights so that
its net length is optimized.
Placement process using simulated annealing is summarized
as pseudo-code shown in Fig. 6. The placement starts with
an initial random placement at a high initial temperature (T),
which is determined based on the circuit size [25]. If Ninst is
the number of instances, then the initial temperature is set to
20 times the standard deviation of placement costs of Ninst
random placements. Since different types of cells are present in
the array, a lookup table is utilized to aid the placement process
with information about the cell type, its locations in the array
and whether the location is already occupied. First, a randomly
chosen instance (I1 ) is moved to a new location (X1 ) of the
same cell type. If this new cell location is already occupied by
another instance (I2 ), then the instances I1 and I2 are swapped.
If it leads to a better placement, the move is accepted. If the
new placement has higher cost, the move is accepted with
certain probability and the acceptance probability reduces as
the process continues. Temperature is slowly decreased while
performing N moves at each temperature, where N = 10 · Ninst
4/3
[25], [26]. The process is terminated when the placement cost
converges.
C. Routing
PANDA-PRO router is based on Dijkstra’s algorithm [27]
to find the shortest path from a source to destination utilizing
186 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 2, FEBRUARY 2016
Fig. 7. Illustration of routing for parasitic reduction: Among multiple routing
solutions, route-2 is the final solution since it passes through only 1 switch
block and uses routing segments of smaller length.
fixed routing resources. For each net, the router starts expanding
all possible connectivities from the source connection block,
which is termed as wavefront expansion. Then the routing
cost at each expanded node is computed from the following
equation.
costi = costi−1 + costSB + Lseg costseg (2)
where costi−1 is the cost at the previous node, costSB is
the cost of switch block, Lseg is the length of the segment,
costseg is the cost of segment of length 1. The last term in
the cost function (Lseg costseg ) is added to penalize longer
routing segments. When a wavefront reaches the destination,
the routing cost is noted and wavefront expansion is continued
till all the other nodes either exceed this routing cost or reach
the destination. This makes sure that short segments are given
higher priority than long segments for the same number of
passing switches. The costSB is set a large number compared to
costseg , so that the router selects a route with a longer segment
than the route that passes through multiple switch blocks,
thereby reducing switch parasitics. An example of routing for
reduced parasitics is shown in Fig. 7. Using costSB = 50 and
costseg = 1, the costs of route-1, 2 and 3 to route a net from
source cell “S” to destination cell “D” are 154, 54, and 61,
respectively. Route-1 passes through 3 switches and thus, has
a high routing cost. Both route-2 and 3 pass through only
1 switch, but route-2 uses shorter length segments than route-3
and hence it has lower cost.
After placement and routing, parasitics from routing includ-
ing are stitched back to PANDA-mapped netlist and simulated
to verify if target circuit specifications are met. If the target
specifications are not met, then the cells which are connected
through large number of switches are resized to compensate for
the DC drop across the switches. This process is repeated till the
target specifications are met and then configuration bit-stream
that controls the cell sizing and routing is generated. The overall
tool flow including the netlist parsing, constraint generation,
transistor-level mapping using HSPICE simulations, place and
route and post-route netlist generation is coded in Perl; while
the placement, routing and bit-stream generation from the
PANDA-mapped netlist are implemented in C. For graphical
visualization of the placement and routing for debugging pur-
poses, VPR tool [25] is customized for PANDA architecture.
Fig. 8. Typical setup for configuration and circuit measurements on PANDA
platform.
IV. 65 nm C IRCUIT M EASUREMENTS
Several fundamental AMS building blocks, such as ampli-
fiers, filters, voltage, and current reference circuits, are designed
in 65 nm technology and mapped to the PANDA platform
to demonstrate the potential of this methodology for rapid
prototyping and validation. Each of these designs including the
biasing circuits are mapped to PANDA cells, placed, routed,
and configuration bit-stream is generated using the developed
PANDA-PRO tool. This bit-stream is serially transferred from
PC to the platform via a commercially available USB to SPI
converter IC (MCP2210). SPI receiver in the PANDA platform
receives the configuration bit-stream, decodes the addresses
and sends the data to corresponding memory locations that
configure the transistor sizing and connectivity of the routing
network. Once programmed, the platform performs the func-
tionality of the designed target circuit till power down, reset,
or reconfiguration. The typical measurement setup used for
measurements of circuits implemented on PANDA platform is
shown in Fig. 8. PANDA chip is integrated on to a test board in
a socket along with the peripherals such as voltage regulators,
USB to SPI protocol converter IC (MCP2210), etc., to help in
circuit measurements in different configurations.
Amplifiers are the fundamental building blocks in analog
IC design ranging from biasing circuits to precision ampli-
fication stages and filters. Basic amplifier topologies such as
5-transistor operational transconductance amplifier (OTA) and
2-stage Miller-compensated OTA are designed in 65 nm tech-
nology and implemented on PANDA platform using the devel-
oped tool. The measured performance metrics such as DC gain,
unity gain frequency, common mode rejection ratio (CMRR),
power supply rejection ratio (PSRR), total harmonic distortion
(THD) at 0.2 V output swing and current consumption of these
circuits compared to the target design simulation results are
shown in Table III. The target circuits are simulated with a load
capacitance of 15 pF to account for pad and probe capacitance.
The measurement results show a good match in DC charac-
teristics including gain, CMRR, PSRR, but show degradation
in AC characteristics especially at frequencies > 10 MHz.
Though AC performance can be improved to some extent by
increasing bias current [17], it increases voltage drop in the
routing switches and may further degrade the circuit perfor-
mance. Output distortion, on the other hand, shows significant
degradation compared to that target circuits because of the non-
linearity in the transmission gate based switches.
Using these OTAs as building blocks, biasing circuits such
as bandgap voltage reference and current reference circuits are
SUDA et al.: A 65 nm PROGRAMMABLE ANALOG DEVICE ARRAY (PANDA) FOR ANALOG CIRCUIT EMULATION
TABLE III
M EASURED P ERFORMANCE OF 65 nm PANDA-M APPED OTA S
Fig. 9. Measured bandgap reference voltage of the 65 nm PANDA implemen-
tation compared to target bandgap reference circuit on the same die.
Fig. 10. Measured current reference (IREF ) of PANDA implementation
compared to the simulated target design.
implemented on PANDA platform. The implemented bandgap
reference circuit is shown in Fig. 9 inset. Bandgap reference
voltage of PANDA implementation measured from room tem-
perature to 80 ◦ C compared to that of custom designed bandgap
reference circuit after trimming is shown in Fig. 9. Current
reference circuit as shown in Fig. 10 inset is implemented on
the platform, where a reference voltage (VREF ) is forced on a
resistor (R) using negative feedback which defines the current
through the resistor as VREF /R. Measured reference current
of PANDA implementation shows a good match to the target
design as shown in Fig. 10.
187
TABLE IV
M EASURED P ERFORMANCE OF 65 nm PANDA-M APPED C IRCUITS
TABLE V
D ESIGN S CALE , ROUTING S WITCHES , AND T IME TO P LACE & ROUTE
An amplifier with resistive feedback, a first order Gm − C
filter, active RC low pass and high pass filters are also imple-
mented on the platform. The measured performance metrics of
these circuits match with the simulation results of the target
designs as shown in Table IV. Since ID , Rout , and Gm of each
transistor of the target analog circuit is reproduced by PANDA
cells successfully, circuits implemented on PANDA capture
the essential DC and AC characteristics of the target circuits.
The number of programmable cells along with the number of
reconfiguration switches and the time taken for place and route
of some circuits implemented on the platform are summarized
in Table V.
V. A PPLICATIONS AND L IMITATIONS
FPGAs are proven successful as both rapid prototyping
tools and application platforms for digital circuits. For analog
designs, due to the variety and complexity of analog circuits,
FPAAs are specific to a limited set of applications depend-
ing on the type of building blocks and routing architectures.
FPAAs are deployed in a wide range of applications includ-
ing biomedical applications [28], sensor analog front-end and
readout circuits [28]–[30], audio processing [31], biologically
inspired signal processing [14], emulation of smart power grids
[32], [33], etc. Depending on scale of the design, PANDA
platform is also capable of implementing the above-mentioned
applications.
Furthermore, owing to its transistor-level fine granularity,
PANDA provides a unique opportunity for analog designers
to validate new circuit topologies by rapid prototyping be-
fore an expensive tape-out in a new technology node. Other
applications of the platform include the emulation of circuits
with sub-threshold transistors, where the transistor models are
not accurate. The PANDA platform can also be used as an
educational tool, where students could design a circuit, simulate
and quickly prototype it on the platform to observe the circuit
performance in minutes.
188 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 2, FEBRUARY 2016
Fig. 11. (a) Block diagram to demonstrate offset cancellation circuit using a
comparator and FPGA in a closed loop. (b) Offset measurement circuit.
A. Dynamic Reconfiguration Capability
Since configuration bit-stream is transmitted to the byte-wise
addressable memory that stores cell sizing and connectivity
information, any memory location can be manually rewritten
after configuration, thus enabling dynamic reconfiguration ca-
pability of PANDA. This capability to reconfigure only a part of
the circuit facilitates multiple applications such as calibration,
digital trimming, automatic gain control, offset cancellation,
device variability and aging compensation, etc.
We demonstrate dynamic reconfiguration capability of
PANDA via offset cancellation of a 2-stage OTA by using an
FPGA to detect the offset error and correct it by sending the
bit-stream to resize its input transistors. The block diagram
of offset calibration is shown in Fig. 11(a) and (b) shows the
circuit used to measure offset. To cancel the offset of the OTA,
a comparator is configured in PANDA and its output is fed
to FPGA. The status of the comparator output is read from
the FPGA using SPI interface. Based on the output of the
comparator, new bit-stream that resize the input transistors to
cancel the offset is generated and sent to the platform. For
demonstration purposes, transistor sizing update based on com-
parator output is implemented in software, which could easily
be implemented in FPGA to make it a standalone platform.
The offset cancellation loop continues to cancel the offset till
the system converges i.e. when the residual offset is limited
by the LSB of the input transistor size. Using this technique
the offset of the 2-stage OTA is reduced from 452 μV to 29 μV.
If the application demands for higher accuracy, smaller cells
can be used in parallel to original input transistors to have finer
control over the sizing.
B. Reconfigurable Multi-Sensor Readout Circuits
There is a growing demand for integrated sensors in mobile
platforms, where low power consumption is critical. These
sensors need diverse front-end circuits for signal conditioning
of the different signal types to be sensed such as current,
voltage, charge, resistance etc. A wide variety of circuits such
as current sensing transimpedance amplifier, capacitive sensing
charge amplifier, variable gain amplifier, etc., are required for
sensing those signals. A generic multi-sensor front-end circuit
design to meet the requirements of all the diverse sensors
TABLE VI
S UMMARY OF PARAMETERS IN PANDA P LATFORM
is non-trivial [34] and might lead to over-design and/or high
power consumption. Moreover, with the increasing demand for
low cost consumer electronics and shrinking time-to-market,
FPAAs are proven to be powerful tools for such multi-sensor
front-end circuit implementation [35]. PANDA also presents a
viable solution for this application owing to its transistor-level
fine-granularity along with its ability to reconfigure on-the-fly
to any sensor front-end circuit.
C. Limitations of the 65 nm PANDA Platform
Measurement results of circuits implemented on PANDA
demonstrate a good match in primary performance metrics with
those of the targets circuits such as the gain, CMRR, PSRR,
bandwidth, etc., which depend on the transistor’s intrinsic
properties—ID , Rout and Gm . However, second-order per-
formance metrics such as noise, distortion, matching, etc.,
which depend more on technology parameters and physical
layout than transistor properties, cannot be matched exactly by
PANDA-implemented circuits.
PANDA cells are interconnected by transmission gate based
switches that have a finite resistance (< 400 Ω), which places
an upper limit on the current per circuit branch. As the DC
current increases, voltage drop across the transmission gate
switches increase which may destroy the circuit functionality
by changing the bias conditions. Depending on the number of
transistors in each branch, required voltage headroom for bias-
ing each transistor and number of switches that connect them
after placement and routing, the current per branch is limited to
100 μA. For example, if a circuit branch consists of 2 transistors
connected by a total of 5 switches from the supply (1.2 V) to
the ground and if it can tolerate a maximum voltage drop of
0.2 V across the switches, then the maximum current through
that branch is 100 μA. This current limitation in turn limits
the maximum operating frequency of the PANDA-implemented
circuits driving the I/O pad and external PCB parasitics to
100 MHz, unless driven by custom on-chip analog buffers.
However, in this work the maximum measured frequency of the
implemented OTA shown in Table III is only 8.6 MHz, because
of the passive probes used in measurements, which add a load
of 12 pF to the circuit.
Implementation of large-scale AMS circuits with thousands
of transistors is not feasible in the current implementation
of the platform because of the limited number of PANDA
cells. For such large-scale AMS circuit implementation, it is
desirable to have a platform with a combination of coarse-
grained macros such as opamps, ADCs, DACs along with fine-
grained transistor-level cells such that it will have the ease
of mapping and less parasitics associated with coarse-grained
macros along with versatility and flexibility of fine-grained
configurable blocks.
SUDA et al.: A 65 nm PROGRAMMABLE ANALOG DEVICE ARRAY (PANDA) FOR ANALOG CIRCUIT EMULATION
TABLE VII
C OMPARISON OF 65 nm PANDA W ITH O THER FPAA S
Although digital circuits can be implemented by mapping
each transistor to PANDA cells, it is quite cumbersome and area
inefficient. It is preferable to have field programmable mixed-
signal array [15] using a combination of FPGA configurable
logic blocks (CLB) with PANDA cells and coarse-grained
macros such that any digital circuit in feedback loop with the
primary analog circuit can be implemented and validated using
the same platform. Nevertheless, PANDA provides a promising
solution for rapid prototyping and validation of analog circuits
at scaled technology nodes with versatility and flexibility of
transistor-level granularity.
VI. C ONCLUSION
A full system implementation of PANDA in a 65 nm CMOS
process is presented and its parameters are summarized in
Table VI. CAD tools for mapping, placement, routing, and
programming, which are essential for implementation of analog
circuits on the designed platform, are developed. The efficacy
of the platform in analog circuit validation is demonstrated
through implementation of several analog circuit building
blocks including amplifiers, biasing circuits, and active fil-
ters on the platform. Measured performance metrics of these
circuits show a good match with the targeted designs, which
prove the effectiveness of PANDA for rapid prototyping. A
comparison of 65 nm PANDA platform with other FPAAs is
summarized in Table VII. Transistor-level fine granularity of
PANDA provides a unique opportunity for analog designers
to validate new circuit topologies and architectures before an
expensive tape-out. Dynamic reconfiguration capability of the
PANDA platform in conjunction with an external FPGA or
a processor for reconfiguration opens up new realms such
as self-calibrating circuits, adaptive circuits, reconfigurable
multi-sensor readout circuits, evolvable hardware, etc. Overall,
PANDA provides a good solution for rapid prototyping and
validation of analog circuits and also functions as an application
platform for low frequency analog processing applications such
as audio processing and sensor front-end circuits.
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Naveen Suda (S’12) received the B.Tech degree
in electronics and communication engineering from
National Institute of Technology Warangal, India,
in 2007 and the M.Tech degree in VLSI from
the Indian Institute of Technology Guwahati, India,
in 2010. He is currently pursuing the Ph.D. degree in
electrical engineering at Arizona State University.
He worked as an R&D Engineer at Tejas Net-
works, Bangalore, India, in 2007–2008 and as Circuit
Design Engineer at IBM Bangalore in 2010–2011.
He worked as a summer intern at Intel, Santa Clara,
CA, USA, in 2014 and at ARM, San Jose, CA, USA, in 2015. His research in-
terests are low-power analog/mixed signal circuits, field-programmable analog
circuits, and design automation for reconfigurable design.
Jounghyuk Suh received the B.S. degree in elec-
tronics and electrical communication engineering
from Korea Aerospace University, Goyang, in 2007.
He received M.S. and Ph.D. degrees in electrical
engineering from Arizona State University, Tempe,
AZ, USA, in 2009 and 2013. He joined NXP Semi-
conductors Inc. Secure, Interface and Power Group,
working on analog and mixed signal interface and
power management ICs.
Nagib Hakim received the M.S. and Ph.D. de-
grees in electrical engineering from Columbia Uni-
versity, New York, in 1986 and 1992, respectively
after which he joined Intel Corporation in Santa
Clara, CA, USA. His work in CAD for process
development and design includes statistical cir-
cuit modeling and optimization, SER prediction,
and power/performance analysis. He is currently a
Principal Engineer in the System Validation En-
abling division focusing on methodologies to accel-
erate post-silicon electrical validation. His research
and development interests include accurate large-scale circuit modeling and
emulation, as well as model to silicon correlation. He was a recipient of the
Mahboob Khan Outstanding Industry Liaison Award in 2012.
Yu Cao (S’99–M’02–SM’09) received the B.S. de-
gree in physics from Peking University, China,
in 1996. He received the M.A. degree in biophysics
and the Ph.D. degree in electrical engineering
from University of California, Berkeley, CA, USA,
in 1999 and 2002, respectively.
He worked as a summer intern at Hewlett-Packard
Labs, Palo Alto, CA, USA, in 2000, and at IBM
Microelectronics Division, East Fishkill, NY, USA,
in 2001. After working as a Postdoctoral Researcher
at the Berkeley Wireless Research Center (BWRC),
Berkeley, CA, USA, he is now an Associate Professor of Electrical Engineering
at Arizona State University, Tempe, AZ, USA. He has published numerous
articles and two books on nano-CMOS modeling and physical design. His
research interests include physical modeling of nanoscale technologies, design
solutions for variability and reliability, reliable integration of post-silicon
technologies, and hardware design for on-chip learning.
Dr. Cao was a recipient of the 2012 Best Paper Award at IEEE Computer
Society Annual Symposium on VLSI, the 2010, 2012, 2013 and 2015 Top 5%
Teaching Award, Schools of Engineering, Arizona State University, 2009 ACM
SIGDA Outstanding New Faculty Award, 2009 Promotion and Tenure Faculty
Exemplar, Arizona State University, 2009 Distinguished Lecturer of IEEE
Circuits and Systems Society, 2008 Chunhui Award for outstanding oversea
Chinese scholars, the 2007 Best Paper Award at International Symposium on
Low Power Electronics and Design, the 2006 NSF CAREER Award, the 2006
and 2007 IBM Faculty Award, the 2004 Best Paper Award at International
Symposium on Quality Electronic Design, and the 2000 Beatrice Winner Award
at International Solid-State Circuits Conference. He has served as Associate
Editor of the IEEE T RANSACTIONS ON C OMPUTER -A IDED D ESIGN OF
I NTEGRATED C IRCUITS AND S YSTEMS , and on the technical program com-
mittee of many conferences. He is a member of the IEEE EDS Compact
Modeling Technical Committee.
Bertan Bakkaloglu (M’94–SM’08) received the
Ph.D. degree from Oregon State University,
Corvallis, OR, USA, in 1995 and joined Texas
Instruments Inc. Mixed Signal Wireless Design
Group, Dallas, TX, USA, where he worked on
analog, RF and mixed signal front ends for wireless
and wireline communication ICs. He worked on
system-on-chip designs with integrated battery
management and RF, analog baseband functionality
as a design leader. In 2004 he joined the Electrical
Engineering Department at Arizona State University,
Tempe, AZ, USA, as an Associate Professor. His research interests include
mixed signal circuit design for supply regulators, biomedical, chemical and
MEMS sensor interface circuits, fractional-N frequency synthesizers, high
speed data converters, and built-in-self-diagnostic circuits for high reliability
mixed signal circuits.
Dr. Bakkaloglu has been associate editor for IEEE T RANSACTIONS ON
C IRCUITS AND S YSTEMS and currently an associate editor for IEEE T RANS -
ACTIONS ON M ICROWAVE T HEORY AND T ECHNIQUES . He is the General
Chair for 2015 RFIC Symposium.