13.

Sequential Circuit Timing

o Objectives o Reading Assignment
This section covers several timing considerations encountered n Much of the information in this section is not in the Brown
in the design of synchronous sequential circuits. It has the & Vranesic text. There is material on clock skew in section
10.3. That section also discusses the effects of gating the
following objectives:
clock.
n Define the following global timing parameters and show
how they can be derived from the basic timing parameters
of flip-flops and gates.
u Maximum Clock Frequency
u Maximum allowable clock skew
u Global Setup and Hold Times

n Discussways to control the loading of data into registers

and show why gating the clock signal to do this is a poor
design practice.

Elec 326 13.1 Sequential Circuit Timing Elec 326 13.2 Sequential Circuit Timing

13.1. Maximum Clock Frequency o Example

o The clock frequency for a synchronous sequential D Q Q
circuit is limited by the timing parameters of its flip- CK Q
flops and gates. This limit is called the maximum
clock frequency for the circuit. The minimum clock
period is the reciprocal of this frequency.
o Relevant timing parameters
n Gates:
u Propagation delays: min tPLH, min tPHL, max tPLH, max tPHL

n Flip-Flops: TW ≥ max tPFF + tsu

u Propagation delays: min tPLH, min tPHL, max tPLH, max tPHL
u Setup time: tsu n For the 7474, max tPLH = 25ns, max tPHL = 40ns, tsu = 20ns
u Hold time: th TW ≥ max (max tPLH + tsu, max tPHL + tsu)
TW ≥ max (25+20, 40+20) = 60

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o Example o Example
0
Q0 D Q
Q1
D Q MUX
D Q Q 1

Q Q
CK
CK

TW ≥ max tPFF + max tPMUX + tsu

TW ≥ max tPFF + max tPINV + tsu

Elec 326 13.5 Sequential Circuit Timing Elec 326 13.6 Sequential Circuit Timing

o Example
o Clock Skew
n If a clock edge does not arrive at different flip-flops at
exactly the same time, then the clock is said to be skewed
between these flip-flops. The difference between the times
of arrival at the flip-flops is said to be the amount of clock
skew.
n Clock skew is due to different delays on different paths
Paths from Q1 to Q1: None
from the clock generator to the various flip-flops.
u Different length wires (wires have delay)
Paths from Q1 to Q2: TW ≥ max tPDFF +tJKsu = 20 +10 = 30 ns
u Gates (buffers) on the paths
TW ≥ max t PDFF + max t AND + tJKsu = 20 + 12 + 10 = 42 ns
u Flip-Flops that clock on different edges (need to invert clock for
Paths from Q2 to Q1: TW ≥ max tPJKFF + tOR + TDsu = 25 + 10 + 5 = 40 ns some flip-flops)
Paths from Q2 to Q2: TW ≥ max tPJKFF + max tAND + t JKsu = 25 + 12 + 10 = 47 ns u Gating the clock to control loading of registers (a very bad idea)

TW ≥ 47 ns
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o Example (Effect of clock skew on clock rate) n Clock C1 skewed after C2
n Clock C2 skewed after C1
D2 Q2
D Q
Q1 D Q
D2 Q2
D Q
Q1 D Q C2
C1 Q
Q
C2
C1 Q
Q CK

CK

TW ≥ max T PFF + max t OR + tsu

(if clock not skewed, i.e., tINV = 0)

TW ≥ max T PFF + max t OR + tsu + max tINV

(if clock skewed, i.e., tINV > 0)

TW ≥ max T PFF + max t OR + tsu TW ≥ max T PFF + max t OR + tsu - min tINV
(if clock not skewed, i.e., tINV = 0) (if clock skewed, i.e., tINV > 0)

Elec 326 13.9 Sequential Circuit Timing Elec 326 13.10 Sequential Circuit Timing

o Summary of maximum clock frequency calculations o Example

Q1 D2
D Q D Q
Logic
C1 Network C2

tXY = Network delay from X to Y

tXD = Network delay from X to D
TW
TW tQY = Network delay from Q to Y
C1
C1 tQD = Network delay from Q to D
tSK = tINV
tSK = tINV C2
C2
Q1
Q1
D2
D2
tPFF tOR
tPFF tOR tsu n For each of the following two connections find
tsu
u The minimum clock period
u The maximum and minimum delay from CLK to YOUT
C2 skewed after C1: T W ≥ max TPFF + max tNET + tsu - min tINV
C2 skewed before C1: TW ≥ max T PFF + max tNET + t su + max t INV

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 n Circuit 2:
n Circuit 1:

n≥2 n≥2

tXY = Network delay from X to Y

tXY = Network delay from X to Y
tXD = Network delay from X to D
tXD = Network delay from X to D
tQY = Network delay from Q to Y
tQY = Network delay from Q to Y
tQD = Network delay from Q to D
tQD = Network delay from Q to D

Minimum Clock Period: Minimum Clock Period:

Tw ≥ max t PFF + max tQY + (n-2) max tXY +max tXD + tsu ≥ TW Tw ≥ max t PFF + max tXD + tsu
Tw ≥ max t PFF + max tQD + tsu Tw ≥ max t PFF + max tQD + tsu
Maximum Delay: Maximum Delay:
TCY ≤ max tPFF + max tQY + (n-1)tXY TCY ≤ max tPFF + max (max tXY , max t QY )
Minimum Delay: Minimum Delay:
TCY ≥ min tPFF + tQY TCY ≥ min tPFF + min (min t XY , min tQY )

Elec 326 13.13 Sequential Circuit Timing Elec 326 13.14 Sequential Circuit Timing

13.2. Maximum Allowable Clock Skew n Case 2: C1 delayed from C2

o How much skew between C1 and C2 can be tolerated Q1 D2
in the following circuit? D Q D Q

Q Q

D Q
Q1 D2 D Q

C1 C2
Q Q

C1 C2

n Case 1: C2 delayed after C1

tPFF > th + tSK

tSK < min tPFF - th

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o How does additional delay between the flip-flops o Summary of allowable clock skew calculations
affect the skew calculations?

tSK ≤ min tPFF - th

tsk ≤ min t PFF + min tMUX - t h

tSK + th ≤ t PFF + tNET

tSK ≤ min tPFF + min t NET - th

Elec 326 13.17 Sequential Circuit Timing Elec 326 13.18 Sequential Circuit Timing

o Example: What is the minimum clock period for the N2

D1
following circuit under the assumption that the clock D Q
Q1
N1
D2 D Q
Q2

C2 is skewed after C1 (i.e., C2 is delayed from C1)?

Q Q

C1 C2

n First calculate the maximum allowable clock skew.

N2
tSK < min tPFF + min tN1 - th
D1
D Q
Q1
N1
D2 D Q
Q2 n Next calculate the minimum clock period due to the path
from Q1 to D2.
Q Q
TW > max tPFF + max tN1 + tsu - min tSK
C1 C2 n Finally calculate the minimum clock period due to the path
from Q2 to D1
TW > max tPFF + max tN1 + tsu + max tSK
TW > max tPFF + max tN2 + tsu + (min tPFF + min tN1 - th)
TW > max tPFF + min tPFF + max tN2 + min tN1 + tsu - th

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 13.3. Global Setup Time, Hold Time and o Global setup & hold time (clock delayed)
Propagation Delay
D D Q
o Global setup and hold times (data delayed) CK
CLK Q
X NET D D Q

CK
CLK Q

TSU = tsu - min tC TH = th + max tC

TSU = tsu + max tNET TH = th - min tNET

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o Global setup & hold time (data & clock delayed) o Global propagation delay
X Q
NET D
D Q
D Q NET Y
CK
CLK Q
CK
CLK Q

TSU = tsu + max tNET - min tC TH = th - min tNET + max tC TP = tC + tFF + tNET

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o Summary of global timing parameters o Example
LD Q
D Q
D CK
CLK Q

n Find TSU and T H for input signal LD relative to CLK.

TSU = tsu +max t NET - min tC

= t su + max t INV + max tNAND + max tNAND - min tINV

TH = th - min tNET + max tC

= t h - min t NAND - min tNAND + max T INV

TSU = tsu + max tPN - min tPC ≤ tsu + max tPN

TH = th + max t PC - min t PN ≤ th + max tPC

TP = tPFF + tPN + tPC

Elec 326 13.25 Sequential Circuit Timing Elec 326 13.26 Sequential Circuit Timing

13.4. Register load control (gating the clock) o If LD was constrained to only change when the clock was low,
o A very bad way to add a load control signal LD to a then the only problem would be the clock skew.
register that does not have one is shown below
D D Q

LD CK
Q
CLK

o The reason this is such a bad idea is illustrated by the

following timing diagram.

o The flip-flop sees two rising edges and will trigger

twice. The only one we want is the second one.
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o If gating the clock is the only way to control the o The best way to add a LD control signal is as follows:
loading of registers, then use the following approach:
D D Q LD
D Q
CLK Q D
CLK Q
LD

n There is still clock skew, but at least we only have one

triggering edge.

Elec 326 13.29 Sequential Circuit Timing Elec 326 13.30 Sequential Circuit Timing

13.5. Synchronous System Structure and Timing 13.6. Tips & Tricks
o Use timing diagrams to determine the timing properties of
sequential circuits

13.7. Pitfalls
o Using typical timing values from the data sheet (use
only max and/or min values)
o Gating the clock

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13.8 Review
o How the flip-flop and gate timing parameters affect
the maximum possible clock frequency.
n How clock skew affect maximum possible clock frequency.
o How the delay of logic between flip-flops affects the
maximum allowable clock skew.
o How flip-flop setup and hold times are translated by
the combinational logic delays to get global setup and
hold times.
o The detrimental effect of gating the clock signal.

Elec 326 13.33 Sequential Circuit Timing