Fig 1

Beginning of simulation no data is written in so FIFO is empty until

rde =1
 Fig 2
Continuation of the previous wave form, it can be seen that data
written first is first read out.
 Fig 3
Wre = 1 and rde =0 hence after 64 write operation f_full is set.

Until next read operation it would be set, data sent during this
period will be lost.
 Fig 4
Reset = 1 both read and write pointer points to 0th location of
ram until reset is cleared.

During this time f_empty would be set , this is like beginning of

operation once again.
ABSTRACT

FIFO is a First-In-First-Out memory queue with control logic that manages the read and
write operations, generates status flags like fifo empty fifo full. It is often used to Control
the flow of data between source and destination.

FIFO can be classified as

1) Synchronous : - same clock control read and write operation
2) Asynchronous : - different clocks for read and write operation
In this project we are designing a synchronous FIFO.

Introduction

In computer programming, FIFO (first-in, first-out) is an approach to handling program

work requests from queues so that the oldest request is handled first. In hardware it is
either an array of flops or Read/Write memory that store data given from one clock
domain and on
request supplies with the same data to other clock domain following the first in first out
logic. The clock domain that supplies data to FIFO is referred as WRITE OR INPUT
LOGIC and the clock domain that reads data from the FIFO is referred as READ OR
OUTPUT LOGIC.

FIFO full and FIFO empty flags are of great concern as no data should be
written in full condition and no data should be read in empty condition, as it
can lead to loss of data or generation of non relevant data. The full and
empty conditions of FIFO are controlled using read and write pointers.

Fig1 data flow in FIFO

Design

Fig1 Block diagram of FIFO

Name mode Width Description

Clk Input 1 bit Master clock to control read and write operation
to internal memory(ram)
Wre Input 1 bit Active high signal indicates that data is available
in data_in bus it should be written into internal
memory(ram)
Rde Input 1 bit Active high signal indicates that data should be
read out from the internal memory and place it in
the data_out bus
Reset Input 1 bit Active high signal ,when it is set read and write
pointer points to 0th location of internal memory,
for normal operation it should be reset
Data_in Input 8 bit 8 bit input data to FIFO
F_full output 1 bit Indicates that FIFO’s internal memory has no
space left to take in new data
F_empty output 1 bit Indicates that FIFO’s internal memory is
empty and therefore has no data to serve
upon the read request
Data_out output 8 bit 8 bit data out of FIFO
Fig 2 shows the functional block diagram of FIFO

As we can see from the figure fifo contains

1) 64 byte Ram to store data.
2) Two 7 bit counter used as a read and write pointer for Ram.
3) Control logic to control read and write operation to Ram and to give f_full and
f_empty signal based on read and write pointer.
Design of Ram

Name Mode Width Description

wr Input 1 bit Active signal ,indicates that data should be written
into Ram
rd Input 1 bit Active signal ,indicates that data should be read
out of Ram
clk Input 1 bit During the rising edge of the clock all read and
write operation takes place
waddr Input 6 bit Address for data to be written
raddr Input 6 bit Address for data to be read
datain Input 8 bit Data to be written into Ram
dataout output 8 bit Data to be read out of Ram
VHDL program

Library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

Entity Rams is

Port ( wr,rd,clk : in std_logic;

Datain : in std_logic_vector(7 downto 0);

Dataout : out std_logic_vector(7 downto 0);

waddr,raddr : in std_logic_vector(5 downto 0));

END Rams;

Architecture Behave of Rams is

Type memory is array ( 63 downto 0) of std_logic_vector( 7 downto 0);

Signal mem : memory ;

Signal a,b : integer range 0 to 64 ;

Begin

Process(clk)

Begin

if (clk'event and clk = '1') then

if ( wr = '1') then
a <= conv_integer(waddr);

mem(a) <= Datain;

end if;

if ( rd = '1') then

b <= conv_integer(raddr);

Dataout <= mem(b);

End if;

End if;

end process;

End Behave;
Design of 7 bit counter

Name Mode Width Description

Clk Input 1 bit clock to count
Enw Input 1bit Active high signal, enables counter to count when
it is set
reset Input 1bit Active high signal, when it is set counter resets to
0000000
adddrw output 7 bit Counter out put

VHDL program

Library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;
entity wcounter is

port( clk,enw,reset : in std_logic;

addrw : out std_logic_vector(6 downto 0));

end wcounter;

architecture wrb of wcounter is

begin

process(clk)

variable qw : std_logic_vector(6 downto 0) :="0000000";

begin

if(clk'event and clk='1' and enw='1') then

if(reset='1') then

qw := "0000000";

elsif(qw = "1111111")then

qw :="0000000";

else

qw := qw+1;

end if;

end if;

addrw <= qw;

end process;

end wrb;
Design of control logic

Name Mode Width Description

wrad Input 7 bit Out put of the write address counter
Rard Input 7 bit Out put of the read address counter
Dr Input 1 bit Read enable of fifo
Rw Input 1 bit Write enable of fifo
Fu Inout 1 bit Fifo full
Em Inout 1 bit Fifo empty
Enwc Out 1 bit Enable of write address counter, also write enable of
Ram
enrc Out 1bit Enable of read address counter, also read enable of
Ram
VHDL program

Library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity emf is

Port ( wrad : in STD_LOGIC_VECTOR (6 downto 0);

rrad : in STD_LOGIC_VECTOR (6 downto 0);

dr,rw : in std_logic;

fu : inout STD_LOGIC;

em : inout STD_LOGIC;

enwc,enrc : out std_logic );

end emf;

architecture Behavioral of emf is

signal b1,b2,b3 : std_logic;

begin

b1 <= (wrad(0) xnor rrad(0)) and(wrad(1) xnor rrad(1)) and(wrad(2) xnor rrad(2))
and(wrad(3) xnor rrad(3)) and(wrad(4) xnor rrad(4)) and(wrad(5) xnor rrad(5));

b2 <= wrad(6) xor rrad(6);

b3 <= wrad(6) xnor rrad(6);

fu <= b1 and b2;

em <= b1 and b3;

enwc <= rw and (not fu);

enrc <= dr and (not em);

end Behavioral;

Functioning of FIFO with these components connected

together
1) Ram acts as temporary memory location to store data.

2) Two7 bit counters are used to provide write and read address to
Ram, only 6 bits are sufficient to address 64 byte of memory but to
differentiate between fifo full and fifo empty condition we are using
another bit

3) Control logic

a) It gets the read counter, write counter, read enable and write
enable of FIFO as input.

b) It enables both counters and read and write operation of Ram

based on certain condition given below

Actual signal Signal name Description

in control
circuit
F_full fu It is set, if msb of read and
write counter differs but
remaining bits are same
F_empty em It is set, if read counter is
equal to write counter
Read enble of ram enrc It is reset, if fifo empty =1 or
and enable of read rde=0
 counter
write enble of ram enwc It is reset, if fifo full =1 or
and enable of write wre=0
counter

Port mapping all the components

It is according to functional block diagram shown in fig 2

VHDL Program
Library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity fifo is

port ( clk,wre,rde,reset : in std_logic;

f_full,f_empty : out std_logic;

data_in : in std_logic_vector(7 downto 0);

data_out : out std_logic_vector(7 downto 0));

end fifo;

architecture fifob of fifo is

component Rams

Port (

wr,rd : in std_logic;
 clk : in std_logic;

Datain : in std_logic_vector(7 downto 0);

Dataout : out std_logic_vector(7 downto 0);

waddr,raddr : in std_logic_vector(5 downto 0));

end component;

component emf

Port ( wrad : in STD_LOGIC_VECTOR (6 downto 0);

rrad : in STD_LOGIC_VECTOR (6 downto 0);

dr,rw : in std_logic;

fu : inout STD_LOGIC;

em : inout STD_LOGIC;

enwc,enrc : out std_logic );

end component;

component wcounter

port( clk,enw,reset : in std_logic;

addrw : out std_logic_vector(6 downto 0));

end component;

signal v3,v4,v5,v6,v7 : std_logic;

signal v1,v2 : std_logic_vector(6 downto 0);

begin

f1 : wcounter port map(clk,v5,reset,v1);

f2 : wcounter port map(clk,v6,reset,v2);

f3 : emf port map(v1,v2,rde,wre,v3,v4,v5,v6);

f4 : Rams port map(v5,v6,clk,data_in,data_out,v1(5 downto 0),v2(5 downto 0));

 f_full <= v3;

f_empty <= v4;

end fifob;

Modifications In design to demonstrate in FPGA kit

1) Frequency divider to reduce 100k Hz to around 1Hz

2) 7 segment led display interfacing

1) Frequency divider is a 17 bit counter msb of counter is used as clock for FIFO

VHDL program for frequency divider

Library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity freq is

Port ( clk1 : in STD_LOGIC;

clk1_out : out STD_LOGIC_VECTOR (16 downto 0));

end freq;
 architecture Behavioral of freq is

begin

process(clk1)

variable mw : std_logic_vector(16 downto 0) := "00000000000000000";

begin

if(clk1'event and clk1='1') then

if (mw="11111111111111111") then

mw := "00000000000000000";

else

mw := mw+1;

end if;

end if;

clk1_out <= mw;

end process;

end Behavioral;

2) 7 segment led display interfacing requires

a) Code converter :- 4 bit binary data to 7 bit led code

b) 2 :1 mux :- to select data

c) Decoder :- to enble 1 led out of 2

a) Code converter program

library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity conversion is

Port ( din : in STD_LOGIC_VECTOR (3 downto 0);

dout : out STD_LOGIC_VECTOR (6 downto 0));

end conversion;

architecture Behavioral of conversion is

begin

with din select

dout <= "0111111" when "0000",

"0000110" when "0001",

"1011011" when "0010",

"1001111" when "0011",

"1100110" when "0100",

"1101101" when "0101",

"1111101" when "0110",

"0000111" when "0111",

"1111111" when "1000",

"1100111" when "1001",

“1110111" when "1010",

"1111100" when "1011",

"0111001" when "1100",

 "1011110" when "1101",

"1111001" when "1110",

"1110001" when "1111",

"1111111" when others;

end Behavioral;

b) 2:1 mux program

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux is

Port ( sel : in STD_LOGIC;

i1 : in STD_LOGIC_VECTOR (6 downto 0);

i2 : in STD_LOGIC_VECTOR (6 downto 0);

y : out STD_LOGIC_VECTOR (6 downto 0));

end mux;

architecture Behavioral of mux is

begin

with sel select

 y <= i1 when '0',

i2 when '1',

i1 when others;

end Behavioral;

c) 1 to 2 decoder

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder is

Port ( sel1 : in STD_LOGIC;

y1 : out STD_LOGIC_VECTOR (1 downto 0));

end decoder;

architecture Behavioral of decoder is

begin

with sel1 select

y1 <= "10" when '0',

"01" when '1',

 "11" when others;

end Behaviora
VHDL Program

entity final is

port ( clk,wre,rde,reset : in std_logic;

f_full,f_empty : out std_logic;

data_in : in std_logic_vector(7 downto 0);

data_out : out std_logic_vector(6 downto 0);

len : out std_logic_vector(1 downto 0));

end final;

architecture Behavioral of final is

component fifo is

port ( clk,wre,rde,reset : in std_logic;

f_full,f_empty : out std_logic;

data_in : in std_logic_vector(7 downto 0);

data_out : out std_logic_vector(7 downto 0));

end component;

component decoder is

Port ( sel1 : in STD_LOGIC;

y1 : out STD_LOGIC_VECTOR (1 downto 0));

end component;
 component freq is

Port ( clk1 : in STD_LOGIC;

clk1_out : out STD_LOGIC_VECTOR (16 downto 0));

end freq;

component mux is

Port ( sel : in STD_LOGIC;

i1 : in STD_LOGIC_VECTOR (6 downto 0);

i2 : in STD_LOGIC_VECTOR (6 downto 0);

y : out STD_LOGIC_VECTOR (6 downto 0));

end component;

component conversion is

Port ( din : in STD_LOGIC_VECTOR (3 downto 0);

dout : out STD_LOGIC_VECTOR (6 downto 0));

end component;

signal s1 : std_logic_vector(16 downto 0);

signal s2 : : std_logic_vector(7 downto 0);

signal v1,v2 : std_logic_vector(6 downto 0);

begin

fa0 : freq port map (clk,s1);

fa1 : fifo port map(s1(16),wre,rde,reset,f_full,f_empty,data_in,s2);

fa2 : conversion port map(s2(3 downto 0),v1);

fa3 : conversion port map(s2(4 downto 7),v2);

fa4 : mux port map(clk,v1,v2,data_out);

 fav : decoder port map(clk,len);

end Behavioral