Binary Arithmetic & Alus: O Objectives O Reading Assignment

6.
Binary Arithmetic & ALUs

o Objectives o Reading Assignment
This section is concerned with the algorithms for binary n Much of this material was introduced in Elec 220.
arithmetic operations and the logical networks used to
implement these operations. It will: n This material is also covered in Chapter 5, Number
Representations and Arithmetic Circuits, in Brown &
n Review Vranesic.
u The binary number code and the algorithms for addition and
subtraction of binary numbers. n Appendix A of Brown & Vranesic has additional
u The sign-magnitude and two's complement number codes used for
information on the Verilog features covered in this chapter.
representing negative numbers.
u The operation of simple ripple carry adders and subtractors.
n Show how addition can be speeded up using carry
lookahead techniques.
n Show how Verilog can be used to model arithmetic circuits.
Elec 326 6.1 Binary Arithmetic & ALUs Elec 326 6.2 Binary Arithmetic & ALUs
6.1. Binary Arithmetic

o The Binary Number Code o Arithmetic Operations
n Example: Binary-to-Decimal Translation n Binary Addition
X = 101101 (Base 2)
1 1 1 1 0 0 0 0 CARRY
X = 1•25 + 0•24 + 1•23 + 1•22 + 0•21 + 1•20
0 0 1 1 1 1 0 0 X
= 1•32 + 0•16 + 1•8 + 1•4 + 0•2 + 1•1
0 1 0 1 1 0 1 0 Y
= 32 + 0 + 8 + 4 + 0 + 1
0 1 0 0 1 0 1 1 0 SUM
= 45 (Base 10)
n Example: Decimal-to-Binary Translation
1 1 1 0 0 0 0 0 CARRY
N = 23 (Base 10)
1 1 0 1 0 1 0 0 X
N = Q1•2 + N0 = 11•2 + 1 N0 = 1
Q1 = 11 = Q2 • 2 + N1 = 5 • 2 + 1 N1 = 1 1 0 1 1 0 0 1 0 Y
1 1 0 0 0 0 1 1 0 SUM
Q2 = 5 = Q3 • 2 + N2 = 2 • 2 + 1 N2 = 1
Q3 = 2 = Q4 • 2 + N3 = 1 • 2 + 0 N3 = 0
Q4 = 1 = Q5 • 2 + N4 = 0 • 2 + 1 N4 = 1
N = 10111 (Base 2)
1
n Binary Subtraction n Modulo Arithmetic (no carries)
000 000 000
111 0 001 111 0 001 111 0 001
7 1 7 1 7 1
+6
0 0 0 1 1 1 1 0 BORROW 110 6
+2
2 010 110 6 2 010 110 6
+5
2 010
3 3 3
1 1 0 1 1 0 0 0 X 101
5
4 011 101
5
4 011 101
5
4 011
0 1 0 0 1 1 0 1 Y 100
100 + 010 = 110
100
100+110 = 010
100
011 + 101 = 000
1 0 0 0 1 0 1 1 DIFFERENCE 000 000 000
111 0 001 111 0 001 111 0 001
7 1 7 1 7 1
-6
110 6 2 010 110 6 2 010 110 6 2 010
+7 -4
1 0 0 0 1 1 1 0 0 BORROW 101
5
4
3
011 101
5
4
3
011 101
5
4
3
011
0 1 0 1 0 0 0 1 X 100 100 100

111 + 111 = 110 110 - 100 = 010 100 - 110 = 110
1 1 0 0 1 0 1 0 Y 000 000
1 0 0 0 0 1 1 1 DIFFERENCE 111 0 001 111 0 001
7 1 7 1
110 6 -4 2 010 110 6 -7 2 010
5 3 5 3
101 4 011 101 4 011
100 100
100 - 100 = 000 000 - 111 = 001
n Comments on transitions through zero o Negative Numbers

u An addition that causes a transition up to or through 0 is called an n Sign-Magnitude Representation
overflow.
u Most significant bit is used as the sign bit (0 = plus, 1 = negative).
u A subtraction that causes a transition through 0 is called an For example, +5 = 0101, -5 = 1101
underflow.
u Two representations of zero (000...00 and 100...00)
u For positive integers, overflows and underflows are errors.
u Addition involves several tests and is relatively difficult to
implement in hardware.
u Used in floating point
2
n Two's Complement Representation n Two's Complement of an n-bit number
u Divide binary numbers into two equal subsets and assign one to u Definition: If y is an n-bit binary number, then 2n - y is called the
represent positive integers and the other for negative numbers two's complement of y and denoted y*.
0000 l For example: n = 4, y = 0011, y* = 10000 - 0011 = 1101
1111 0001
1110
-2
-1 0 1
2
0010 l Note: y + y* = y + 2n - y = 2n = 0
1101 -3 3 0011
l Hence y* represents -y.
1100 -4 + 4
0100
-
1011
-5
-6 6
0101
5
u Forming the two's complement of a binary number
1010 -7 -8 7 0110
1001
1000
0111 l 2n = 11...11 + 00...01, where both binary numbers are n bits.
l y* = 2n - y = (11...11 + 00...01) -y = (11...11 - y) + 00...01
u Note that there is only one representation of zero
l 11...11 - y = y', the bitwise complement of y
u The most significant bit can be treated as a sign bit (although the
l y* = y' + 00...01
rest of the word is not the magnitude of negative numbers)
l To find the two's complement of y, flip all the bits of y and add 1
u Rotations around the circle works the same way as with positive
integers: Addition - clockwise, Subtraction - counter clockwise l Note that 0* = 0
u There are two ways to subtract a positive number y from another u Sign Extensions: To convert an m bit number to an n-bit number
number x of either sign: where m>n, pad on the left with the sign bit
l Move CCW y steps from x. l 0011 -- 00000011 +3
l Move CW 2n - y steps from x l 1011 -- 11111011 -5
u Note that in the third and fourth examples, the addition resulted in
n Two's Complement Addition movement through zero, but it did not produce an incorrect sum.
u Two's complement addition is just addition modulo 2n Thus movement through zero is not an error for two's complement
addition.
+2 0010 +2 0010
+3 0011 -3 1101 u However, it is possible to produce an error, either a sum that is too
+5 0101 -1 1111 big or too small to represent in the number of bits available.
u Overflow and Underflow:
1111 0000 0001 1111 0000 0001
1110 0010 1110
l Adding two numbers with different signs can never produce an overflow or
-1 0 1 -1 0 1 0010
underflow.
-2 2 -2 2
1101 0011 1101 0011
-3 3 -3 3 l Adding two positive numbers produces an overflow if the sign of the result is
1100 -4 2+3 4 0100 1100 -4 4 0100 negative.
2-3
-5 5 -5 5
1011 -6 6 0101 1011 -6 6 0101 l Adding two negative numbers produces an underflow if the sign of the result is
1010 -7 -8 7 0110 1010 -7 -8 7 0110 positive.
1001 0111 1001 0111
1000 1000 +7 0111 -7 1001
-2 1110 -2 1110 +6 0110 -4 1100
+6 0110 -5 1011 +13 1101 -11 0101
+4 0100 -7 1001 1111 0000 0001 1111 0000 0001
1110 -1 0 1 0010 1110 -1 0 1 0010
1111 0000 0001 1111 0000 0001 1101
-2 2
0011 1101
-2 2
0011
1110 -3 3 -3 3
-1 0 1 0010 1110 -1 0 1 0010
1100 -4 4 0100 1100 -4 4 0100
-2 2 -2 2 +7+6 -7-4
1101 0011 1101 0011 -5 5
-3 3 -3 3 -5 5
-2+6 1011 0101 1011 -6 6 0101
1100 -4 4 0100 1100 -4 -2-5 4 0100 -6 6
1010 -7 -8 7 0110 1010 -7 -8 7 0110
-5 5 -5 5
1011 -6 6 0101 1011 -6 6 0101 1001 0111 1001 0111
1000 1000
1010 -7 -8 7 0110 1010 -7 -8 7 0110
1001 0111 1001 0111
1000 1000 l Note that in one case there is a carry out and in the other there is not
3
n Two's Complement Subtraction u Overflow and Underflow:
l Subtracting two numbers with the same signs can never produce an overflow
u Add the two's complement of the subtrahend to the minuend. or underflow.
l Subtracting a negative number from a positive number produces an overflow if
+4 0100 0100 +3 0011 0011 the sign of the result is negative.
-(+3) -0011 1101 -(+4) -0100 1100 l Subtracting a positive number from a negative number produces an underflow
if the sign of the result is positive.
+1 0001 -1 1111
1111 0000 0001 1111 0000 0001
1110 -1 0 1 0010
-2 2
1110
-2
-1 0 1
2
0010 +4 0100 0100 -4 1100 1100
1101 0011 1101 0011
1100
-3 3 -3 3 -(-5) -1011 0101 -(+5) -0101 1011
-4 +4-(+3) 4 0100 1100 -4 4 0100
-5 5 -5
+3-(+4)
5 +9 1001 -9 0111
1011 -6 6 0101 1011 0101
-7 -8 7 -6 6
1010 0110 1010 -7 -8 7 0110 1111 0000 0001 1111 0000 0001
1001 0111 1001 0111 1110
1000 1000 -1 0 1 0010 1110 -1 0 1 0010
-2 2 -2 2
1101 0011 1101 0011
-3 3 -3 3
+3 0011 0011 -3 1101 1101 1100 -4
+4-(-5)
4 0100 1100 -4 -4-(+5) 4 0100
-5 5
-(-4) -1100 0100 -(-4) -1100 0100 1011 -6 6 0101 1011
-5
-6 6
5
0101
1010 -7 -8 7 0110 -7 -8 7
+7 0111 +1 0001 1001 0111
1010 0110
1000 1001 0111
1000
1111 0000 0001 1111 0000 0001
1110 1110 -1 0 1 0010
-1 0 1 0010
-2 2
-2 2 1101 0011
1101 0011 -3 3
-3 3 -3-(-4)
1100 -4 4 0100 1100 -4 4 0100
+3-(-4)
-5 5 -5 5
1011 0101 1011 -6 6 0101
-6 6
1010 -7 -8 7 0110 1010 -7 -8 7 0110
1001 0111 1001 0111
1000
6.2. Arithmetic Operations in Verilog n Negative numbers are written with a minus sign in the front.
o Numbers in Verilog u Verilog represents a negative number as the two’s complement of
the unsigned binary number.
n Binary numbers can be represented by an expression of the
l For example -4’b0110 = 4’b1010 and -8’d12 = -8’b00011000 = 8b11101000
following form: <length>’<radix> <digits>, where
n The length may exceed the number of bits needed to
u <length> is the number of bits in the number; it is optional.
represent the number.
u <radix> denotes the radix of the representation.
u In this case the bits are padded on the left to get the specified length.
l b - binary, o - octal, h - hex, d - decimal
u <digits> is a sequence of digits in the indicated radix.
n The length may be less the the number of bits needed to
represent the number.
n Examples:
u In this case the high order bits are truncated.
u 12’b100010101001
n Underscore symbols may be used to improve readability.
u 12’o4251
u For example 8’b000110001100 = 8’b0001_1000_1100
u 12’h8A9
n It is also possible to use the symbols x or z in addition to 0
u 12d2217
and 1 in any bit position.
4
o Vectors in Verilog n Making smaller vectors from bigger vectors
n A vector in Verilog is a finite, ordered list of bits. The u The i-th bit of a vector W may be specified as W[i].
length of the vector is the number of bits it contains. l If i is not in the range of W, then W[i] has value x (undefined).
n Vectors are declared in Verilog in the following way: l The index i can be a variable (of type integer) or a constant.
input [3:0] W; //W is a 4-bit input signal, where bit 0 is the right- u A sub-vector of a vector W can be specified as W[ra:rb], where ra
!!!!!!!!!!!!!!!!!!!!!//most bit and bit 3 is the left-most bit and rb specify a sub-range of the range of W.
output [1:8] SUM; //SUM is an 8-bit output signal, where bit 1 is the l For example, if W is declared as “wire [1:8] W;” then W[3:6] is a 4-bit sub-
!!!!!!!!!!!!!!!!!!!!!!!!!!!!//left-most bit and bit 8 is the right-most bit vector of W consisting of bits 3, 4, 5, and 6.
wire [3:1] A, B; //A and B are 3-bit internal signals (i.e., wires), with l The sub-range must be specified with two integer constants, not variables.
!!!!!!!!!!!!!!!!!!!!!!!//bit 1 on the right and bit 3 on the left n Making bigger vectors from smaller vectors
n The range of the vector is specified as [Ra:Rb] where u The concatenation operator { , } can be used to combine two or
u Ra and Rb are integers that specify the left and right indices of the more vectors.
vector l {W,Y} is a vector obtained by writing the bits of W followed by the bits of Y.
u Ra can be > Rb, or Ra can be < Rb. l For example if W = b1001 and Y = b011, then {W,Y} = b1001011
u Ra or Rb can be positive or negative u The replication operator n{W} produced a vector consisting of n
concatenated copies of the vector W.
n Exercise o Binary numbers in Verilog

wire [3:0] W, Y; n Vectors in Verilog may be used to represent binary
numbers in the obvious way.
wire [1:7] X; u It is the position, not the index, of a bit that determines its
significance in the number. That is
Let W = 4’b1101, Y = 4’b0101 and X = 7’b1100101
l The left-most bit is the most significant bit of the number.
u Evaluate the following: l The right-most bit is the least significant bit of the number.
W[2] = b1 n Arithmetic operations
Y[1] = b0 u Addition and Subtraction of vectors
X[0] = bx l Adds or subtracts the vectors as if they were unsigned binary numbers
l The length of the sum or difference is equal the length of the longest operand.
X[3: 5] = b001 l If the lengths of the operands are not equal, the shorter one is padded on the left
with 0’s.
{W,Y} = b11010101
l Examples:
{X[6:7], W[3:1] } = b01110 t If A = 1011b0, B = b0110 and C = b10001, then
t A + B = b11100
3{Y[1:0]} = b010101 t A - C = b00101
t C - B = b01011
t B - C = b10101
5
n To obtain the carry out of an addition the operands must be n Vector assignment statements.
extended as follows:
wire [3:0] X, Y, S;
u Let A and B be 8 bit vectors. assign S = X + Y;
u Then {1’b0, A} + {1’b0, B} is a 9-bit sum of A and B where the u The sizes of the vectors on the right side of the assignment are
left-most bit is the carry out of the low order 8 bits. adjusted (padded with 0 or truncated) to the size of the result
vector on the left side.
n Adding negative binary numbers (in two’s complement
notation) of unequal length. wire [3:0] X, Y;
wire [4:0] S;
u The shorter number must be padded with the number’s sign bit assign S = X + Y; //same as S = {1’b0, X} + {1’b0, Y}
u If A = 8’b0100_1010, B = 4’0110, and C = 4’1001 where all are u Concatenation can also be used on the left side of the assignment
supposed to represent two’s complement numbers, then B must be
padded with 0’s and C must be padded with 1’s if they are added to wire [3:0] X, Y, S;
A. wire carryout;
assign {carryout, S} = X + Y; //X and Y padded with one 0
A + {4{B[3], B} = 8’b0100_1010 + 8’b0000_0110
A + {4{C[3], C} = 8’b0100_1010 + 8’b1111_1001
6.3. Arithmetic Circuits n Verilog representation of a full adder:

u A structural specification:
o Full Adders CI B A S CO
S A module fulladd(Cin, x, y, s, Cout);
B A 0 0 0 0 0 0 1 0 1 input Cin, x, y;
0 0 1 1 0 CI 1 0 1 0 output s, Cout;
0 1 0 1 0 B
0 1 1 0 1 CO
xor(s, x, y, Cin);
CO FA CI A
1 0 0 1 0 and(z1, x, y);
1 0 1 0 1 0 0 1 0 and(z2, x, Cin);
1 1 0 0 1 CI 0 1 1 1 and(z3, y, Cin);
S 1 1 1 1 1 B or(Cout, z1, z2, z3);
endmodule
S = A'•B'•C + A•B'•CI' + A•B•CI + A'•B•CI' l Altera software does not support xor gate module. How would you get around that
A limitation?
= B'•(A'•CI + A•CI') + B•(A•CI + A'•CI') B S u A behavioral specification:
= B'•(A⊕CI) + B•(A⊕CI)' CI
module fulladd(Cin, x, y, s, Cout);
= B⊕(A⊕CI) input Cin, x, y;
output s, Cout;
= A⊕B⊕CI CO
assign s = x ^ y ^ Cin;
CO = A•CI + B•CI + A•B = MAJ(A, B, CI) assign Cout = (x & y) | (x & Cin) | (y & Cin);
endmodule
6
u A simpler behavior specification
module fulladd (Cin, x, y, s, Cout); o Ripple Carry Adders

input Cin, x, y;
output s, Cout; B A
B3 A3 B2 A2 B1 A1 B0 A0
reg s, Cout; n n
CO ADDER CI
CO FA FA FA FA CI
always @(x or y or Cin)
{Cout, s} = x + y + Cin; n
S3 S2 S1 S0 S
endmodule
n Worst case delay occurs when there is a carry that must
propagate from stage 0 to stage n-1 (or from CI to CO)
u Let tCICO be the delay from CI to CO on a single FA
u Then the worst case delay is given by
tADD = n¥tCICO
n Verilog representation of a 4-bit ripple carry adder n Generic Specifications

u A structural specification using the previous fulladd module u Allows the specification of module whose size can be specified by a
parameter (e.g., the number of bits in a ripple carry adder).
module adder4(carryin, X, Y, S, carryout);
input carryin; u Parameters are defined in Verilog statements of the following type:
input [3:0] X, Y;
output [3:0] S;
output carryout; parameter n = 4;
wire [3:1] C;
u Then vectors of length can be defined as follows:
fulladd stage0 (carryin, X[0], Y[0], S[0], C[1]);
fulladd stage1 (C[1], X[1], Y[1], S[1], C[2]); wire [n-1:0] W
fulladd stage2 (C[2], X[2], Y[2], S[2], C[3]);
fulladd stage0 (C[3], X[3], Y[3], S[3], carryout);
u An example of the use of generic specifications is the n-bit adder
endmodule given on the following page.
l Comment: the specification of fulladd can be included in the same file as the l n is determined by the parameter statement (32 in the example).
adder4 or in a different one if its location is known l k is an integer that is used as the index variable of a for loop, and it does not
correspond to a physical connection in the module.
7
module addern (carryin, X, Y, S, carryout);
parameter n = 32;
input carryin; n A ripple carry adder with carry out and overflow:
input [n-1:0] X, Y;
output [n-1:0] S; module addern (carryin, X, Y, S, carryout, overflow);
output carryout; parameter n = 32;
reg [n-1:0] S; input carryin;
reg carryout; input [n-1:0] X, Y;
reg [n:0] C;
output [n-1:0] S;
integer k;
output carryout, overflow;
always @(X or Y or carryin) reg [n-1:0] S;
begin reg carryout, overflow;
C[0] = carryin;
for (k=0; k<n; k=k+1) always @(X or Y or carryin)
begin begin
S[k]=X[k]^Y[k]^C[k]; {carryout, S} = X + Y + carryin;
C[k+1] = (X[k]&Y[k])|(X[k]&C[k])|(Y[k]&C[k]); overflow = (~X[n-1]&~Y[n-1]&S[n-1]) | (X[n-1]&Y[n-1]&~S[n-1]);
end
end
carryout = C[n];
end endmodule
endmodule
o Subtractors o Carry Look Ahead Techniques

n Convert an adder into a subtractor by inverting the
subtrahend and setting the CI to 1.
A
NOT n FA
B M
M
...
n n
NOT
CO ADDER 1 n
FA M
M
n
D
n A combined adder/subtractor: Add if A/S =0, Sub if A/S =1 FA

M
M
XOR
B
FA M
n n n M
CO ADDER A/S XOR ... Carry

Generation
Sum
Generation
n
n
S/D
8
n Carry Generate and Propagate
Gi = Xi • Yi Pi = Xi + Yi Ci+1 = Gi + Pi•Ci
C0 = C 0
C1 = G0 + P0 • C0
M
C2 = G1 + P1 • C1 = G1 + P1 •(G0 + P0 • C0)
C1 = A0•B0+A0•C0+B0•C0 = G1 + P1 • G0 + P1 • P0 • C0
= A0•B0+(A0+B0)•C0 C3 = G2 + P2 • C2 = G2 + P2 •(G1 + P1 • G0 + P1 • P0 • C0)
M = G2 + P2 • G1 + P2 • P1 • G0 + P2 • P1 • P0 • C0
C4 = G3 + P3 • C2
C2 = A 1•B1+A1•C1+B1•C1
= A1•B1+(A 1+B1)•(A0•B0+(A0+B0)•C0)
= G3 + P3 •(G2 + P2 • G1 + P2 • P1 • G0 + P2 • P1 • P0 • C0)
M = A1•B1+(A 1+B1)•A0•B0+(A1+B1)•(A0+B0)•C0 = G3 + P3 • G2 + P3 • P2 • G1 + P3 • P2 • P1 • G0 + P3 • P2 • P1 • P0 • C0
= G + P • C0
C3 = A2•B2+A2•C2+B2•C2 where G = G3 + P3 • G2 + P3 • P2 • G1 + P3 • P2 • P1 • G 0
= A2•B2+(A 2+B2)•(A1•B1+(A1+B1)•A0•B0+(A1+B1)•(A0+B0)•C0) and P = P3 • P2 • P1 • P0
M = A2•B2+(A2+B2)•A1•B1+(A2+B2)•(A1+B1)•A0•B0+
(A2+B2)•(A1+B1)•(A0+B0)•C0
Carry
Generation
u Note that this expression has only three levels of delay for all i.
u Note also that the number of variables in the product term grows
with i.
u These equations are used to define carry look ahead logic as
illustrated in the following figures.
n Adder with carry look ahead

CI C
n Tree-Structured Carry Look Ahead Adder
C
C0 A S
X0 A B
ADD1 S0 ADD1 S CLA
Y0
B
P0 G0
C1 P G CLA CLA CLA CLA

P G
X1
ADD1 S1
Y1 FA FA FA FA FA FA FA FA
Carry
P1 G1
Look
Ahead u The 74S182 is a commercial CLA chip
Logic C2
X2
ADD1 S2
u These carry look ahead networks can be
Y2
P2 G2
connected to extend the technique to
more than four bits in the following way.
C3
X3
ADD1 S3
Y3
P3 G3
P G
9
6.4. Tips & Tricks 6.6. Review
o Form the two's complement by inverting the bits and adding 1.
o The relationship between carry out and overflow
o Alternatively form the two’s complement by scanning the signals in two’s complement addition and subtraction.
number from right to left, skipping zero’s and the first 1, and o The relative advantages of sign magnitude vs. two’s
then toggling the remaining bits.
complement addition and subtraction.
o Perform subtraction by adding the two's complement of the
subtrahend. o The limits on the time to perform addition and how to
achieve them
o Verilog features;
n Constant numbers
6.5. Pitfalls
n Vectors & vector operations
o Viewing the carry out as an overflow/underflow for two's n Arithmetic operations
complement addition/subtraction.
u Vectors of different lengths
n Generic specifications
10

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6.

Binary Arithmetic & ALUs

6.1. Binary Arithmetic

0 1 0 1 0 0 0 1 X 100 100 100

110 6 -4 2 010 110 6 -7 2 010

n Comments on transitions through zero o Negative Numbers

n Exercise o Binary numbers in Verilog

6.3. Arithmetic Circuits n Verilog representation of a full adder:

module fulladd (Cin, x, y, s, Cout); o Ripple Carry Adders

n Verilog representation of a 4-bit ripple carry adder n Generic Specifications

o Subtractors o Carry Look Ahead Techniques

n A combined adder/subtractor: Add if A/S =0, Sub if A/S =1 FA

CO ADDER A/S XOR ... Carry

n Adder with carry look ahead

C1 P G CLA CLA CLA CLA

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