IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO.
2, FEBRUARY 2011
A Compact Model for Threshold Voltage of
Surrounding-Gate MOSFETs With Localized
Interface Trapped Charges
Te-Kuang Chiang, Member, IEEE
Abstract—Based on the perimeter-weighted-sum method
and scaling theory, a compact threshold voltage model for
surrounding-gate MOSFETs with localized interface trapped
charges is developed by considering the effects of equivalent oxide
charges on the flat-band voltage. The model shows how various
charge conditions such as the positive/negative trapped charges
and device structure parameters such as the silicon thickness,
oxide thickness, and channel length affect the threshold voltage
behavior. The model is verified by the 3-D device simulator and
can be efficiently used to explore hot-carrier-induced threshold
voltage degradation of the charge-trapped memory device.
Index Terms—Hot-carrier-induced threshold voltage,
surrounding-gate MOSFETs.
I. I NTRODUCTION
A S THE DEVICE dimension is further shrunk to the deep-
submicrometer regime, the hot-carrier effects (HCEs) will
degrade the device/circuit performance [1], [2]. The generic
mechanism of the hot-carrier-induced trapped charges was
revealed in the previous literature [3]. It indicates that the
device/circuit degradation with the trapped charges is mainly
caused by accumulated dc stress under the condition that the
gate voltage is near the threshold voltage and the high drain
voltage, i.e., the drain-avalanche hot-carrier (DAHC) stress
condition. In other words, the damaged zone and the interface
positive/negative trapped charges can be attributed to DAHC.
Several studies have modeled the hot-carrier-induced threshold
voltage of the planar and the double-gate MOSFETs in the
past decade [4], [5]. However, there are only a few papers
that investigate the threshold voltage model of surrounding-
gate MOSFETs with the interface trapped charges, although
Cho et al. [6] have reported the threshold voltage and subthresh-
old slope characteristics of long-channel vertically cylindrical
Manuscript received May 24, 2010; revised October 26, 2010; accepted
November 3, 2010. Date of current version January 21, 2011. This work was
supported in part by the National Science Council under Contract NSC98-2221-
E-390-038. The review of this brief was arranged by Editor J. C. S. Woo.
The author is with the Advanced Devices Simulation Laboratory, Depart-
ment of Electrical Engineering, National University of Kaohsiung, Kaohsiung
811, Taiwan (e-mail: tkchiang@nuk.edu.tw).
Color versions of one or more of the figures in this brief are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2010.2092777
0018-9383/$26.00 © 2010 IEEE
567
MOSFETs when the bulk trap states are presented. Hot-carrier-
induced threshold voltage degradation for the surrounding-gate
MOSFETs with the interface trapped charges is not comprehen-
sively studied. The surrounding-gate MOSFETs that demon-
strate better packing density, higher driving current, and shorter
scaling length than both planar and double-gate MOSFETs
are more promising for future very large scale integration
circuits [7]. Further exploitation and use of surrounding-gate
MOSFETs in circuits require a physics-based transistor model.
In this brief, by considering the effects of equivalent oxide
charges on the flat-band voltage [8], we report an analytical
threshold voltage model for the surrounding-gate MOSFETs
with localized interface trapped charges based on the scaling
theory [9], [10] and perimeter-weighted-sum method [11]. The
proposed model is verified by 3-D numerical simulation [12]
and explicitly illustrates how various interface trapped charge
conditions and device structure parameters affect the threshold
voltage. The findings of the model are much useful in inves-
tigating HCEs and offer basic guidance for the design of the
charge-trapped memory device.
II. M ODEL D ESCRIPTION
Fig. 1(a) is the schematic of the 3-D surrounding-gate
MOSFETs. Fig. 1(b) and (c) show the 2-D device structure
to derive the model. With various interface trapped charge
distributions, the channel can be divided into three regions.
Regions 1 and 3 denote the undamaged zone. Region 2 is the
damaged zone. The trapped charge density induced by the hot
carriers can distribute near the drain side of the oxide-channel
interface, where the high electric field occurs. In general, we
can simulate the trapped charge density distribution by inserting
the damaged region between the source and drain ends. In other
words, we can assume that the Ld of the damaged region (i.e.,
region 2) lies between the undamaged region near the source
side (i.e., region 1 “Lg − Ls − Ld ”) and the undamaged region
near the drain side (i.e., region 3 “Ls ”). The surrounding-gate
MOSFET is genuinely composed of double-gate MOSFETs
and cylindrical MOSFET. Based on the scaling theory, the
central potential Φc,i (z), together with the natural length of λ,
should satisfy the scaling equation
d2 Φc,i (z) 1
− 2 (Φc,i (z) − φi ) = 0 (i = 1, 2, and 3) (1)
dz 2 λ
568 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 2, FEBRUARY 2011

ai and bi in (7) can be obtained by the continuity of both electric

field and potential at L1 and L2 and the boundary conditions
at source/silicon and drain/silicon junction (as expressed in
the Appendix). The minimum central potential in (7) can be
expressed as

Φc,i,min = 2 ai bi + φi . (8)

By setting Φc,i,min = 2φB and solving the Vgs in (8), one can
obtain the threshold voltage for double-gate MOSFETs

qNa tsi qNa t2si Bi + Bi2 − Ai Ci
Vth,DG,i = Vfb,i + + −
2COX1 8εsi Ai
(9)

qNa tsi qNa t2si Bi + Bi2 − Ai Ci
Vth,CYL,i = Vfb,i + + −
4COX2 16εsi Ai
(10)

for cylindrical MOSFETs. The largest value of Vth,DG,i in

(9) and the largest value of Vth,CYL,i in (10) will dominate
Fig. 1. Schematic of surrounding-gate MOSFETs. (a) Three-dimensional the threshold voltage. (All of Ai , Bi , and Ci are summarized
with cut plane along A-A in Fig. 1(a), the two-dimensional device structure in the Appendix.) Finally, by using the perimeter-weighted-
is used to derive the model, where regions 1, 3, and 2 denote the fresh and
damaged zones, respectively, (c) with cut plane along B-B ; the device is sum method [11], which treats the pillowlike surrounding-
genuinely composed of a cylindrical MOSFET with radius of tsi/2 and double- gate MOSFET as the ends and the double-gate regions of the
gate MOSFET with a width of WDG . channel as separate devices operating in parallel, the threshold
voltage for the surrounding-gate MOSFETs can be obtained
with as the perimeter-weighted sum of the threshold voltage for the
1 8COX1 cylindrical MOSFET and the threshold voltage for the double-
= (2) gate MOSFET
λ 2 4tsi εsi + COX1 t2si
qNa tsi qNa t2si Vth,i = Vth,DG,i × αDG + Vth,CYL,i × (1 − αDG )
φi = Vgs − Vfb,i − − (3)
2COX1 8εsi
(i = 1, 2, and 3) (11)
for double-gate MOSFETs and
with
1 16COX2
= (4) 2WDG
λ2 4tsi εsi + COX2 t2si αDG = (12)
2WDG + πtsi
qNa tsi qNa t2si
φi = Vgs − Vfb,i − − (5) where αDG is the ratio of twice the channel width of the
4COX2 16εsi
double-gate MOSFETs to the perimeter of the surrounding-
for cylindrical MOSFETs, where φi is the central potential gate MOSFETs, which can be 1 (if WDG  πtsi ) for pure
for the long-channel device, and Vfb,1 = Vfb,3 is the flat-band double-gate device and can be 0 (if WDG  πtsi ) for genuine
voltage in undamaged regions. In the damaged region, due to cylindrical MOSFETs. For the surrounding-gate device, 0 <
the effect of equivalent oxide charges on the flat-band voltage, αDG < 1.
we obtain
⎡t ⎤
ox III. R ESULTS AND D ISCUSSION
1 ⎣ xρ(x) qNf
Vfb,2 = Vfb,1 − dx + Qit ⎦ = Vfb,1 − To verify the proposed model, the 3-D device simulator
Cox tox Cox
0 “Devise” is used to simulate the device. The threshold voltage is
(6) extracted for the gate voltage that causes the electron concen-
where ρ(x) is the localized oxide charge density, which is as- tration at the position of the minimum central potential to be
sumed to be zero for simplicity, and Qit = qNf is the uniform equal to the bulk doping density. For the fixed positive/negative
localized interface trapped charge sheet density. Cox can be interface sheet charge density, Fig. 2 shows how the threshold
either Cox1 or Cox2 for double-gate and cylindrical MOSFETs, voltage degradation is affected by the normalized damaged
which have been defined in the previous literatures [9], [13]. zone for the different diameters of silicon body. The increased
The general solution of (1) can be obtained as damaged zone can further degrade the threshold voltage, be-
cause the correspondingly increased interface positive/negative
Φc,i (z) = ai e λ z + bi e− λ z + φi .
1 1
(7) trapped charges will decrease/increase the minimum channel
CHIANG: THRESHOLD VOLTAGE OF SURROUNDING-GATE MOSFET WITH TRAPPED CHARGE
Fig. 2. Threshold voltage degradation versus normalized damaged zone for
different diameters of silicon body.
Fig. 3. Threshold voltage degradation versus normalized damaged zone for
different oxide thicknesses.
potential barrier [5], which hence results in the rolloff/rollup of
the threshold voltage. This interface-trapped-charge-induced
threshold voltage degradation is called ITTVD. For the positive
interface trapped charges, the small diameter of silicon body of
tsi = 20 nm will suffer less ITTVD in comparison to the large
diameter of tsi = 40 nm when Ld increases. This is because
the large silicon thickness decreases more minimum central
potential barrier than the small silicon thickness for the positive
interface charges. On the contrary, for the negative interface
trapped charges, the large diameter of silicon body of tsi =
40 nm will undergo less ITTVD when compared to the small
diameter of tsi = 20 nm due to the fact that the small silicon
thickness decreases more minimum central potential barrier
than the large silicon thickness. The fixed positive/negative
interface sheet charge density for the small diameter of silicon
body will lessen/enhance ITTVD when the damaged zone
increases. Although the small diameter of silicon body is pre-
ferred to resist ITTVD caused by the positive charges, the di-
ameter of silicon body should become larger not only to reduce
ITTVD by the negative charge but also to enhance the current
driving capability by means of the wide cross-sectional area of
the channel. Fig. 3 shows the variation of threshold voltage
degradation with the normalized damaged zone for different
569
Fig. 4. Threshold voltage rolloff versus gate length for both fresh and dam-
aged devices.
oxide thicknesses. The interface positive/negative charges with
large damaged zone will bring about great threshold voltage
degradation, particularly for the thick oxide thickness. To make
the device experience less ITTVD, not only should the thin
gate oxide be accounted for but the small damaged zone must
also be desired for the device. Note that, when the gate oxide
thickness is reduced below 10 nm [13], the gate leakage current
caused by the tunneling effects will deteriorate the device
performance. The tradeoff about keeping the low threshold
voltage degradation without increasing the large gate leakage
current should be seriously considered in designing the device.
Fig. 4 depicts the dependence of the threshold voltage rolloff on
the channel length for both the damaged and fresh devices. The
ITTVD caused by interface trapped charges may be coupled
with drain-induced barrier lowering (DIBL). Since the ITTVD
caused by the negative trapped charges (i.e., threshold voltage
rollup as shown in Fig. 3) has an opposing effect to DIBL that
causes threshold voltage rolloff for the short-channel device,
the threshold rolloff induced by DIBL for the damaged device
with the negative trapped charges will be decreased and become
less than that for the fresh device as the gate length is reduced.
On the contrary, due to the fact that the ITTVD caused by
the positive trapped charges (i.e., threshold voltage rolloff as
shown in Fig. 3) takes the same effect as DIBL, the threshold
rolloff induced by DIBL for the damaged device with the
positive trapped charges will be enhanced and become more
than that for the fresh device. Although the negative interface
trapped charge can alleviate DIBL, it will bring about the large
operation of threshold voltage and can be an obstacle for low-
voltage circuit application. It is worthwhile to point out that, for
the small damaged zone of Ld = 10 nm with the longer channel
length of Lg > 70 nm (i.e., the smaller normalized damaged
zone of Ld /Lg < 1/7), ITTVD can be negligible in comparison
with DIBL, and the threshold voltage degradation for all of the
three cases will be dominated by DIBL. This clearly explains
why the threshold voltage rolloff for all of the three cases
are almost the same as shown in Fig. 4 as Lg > 70 nm with
Ld = 10 nm. With the fixed interface trapped positive/negative
charge, Fig. 5 shows the degradation of threshold voltage with
normalized damaged zone for the double-gate (αDG = 1), the
570 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 2, FEBRUARY 2011

silicon and drain/silicon junctions, the coefficients for a1 and

b1 in (8) can be obtained as

coth(kLg ) − 1
a1 =
2
× [(cosh(kL1 − kLg ) − cosh(kL2 − kLg )) (φ2 − φ1 )

+ Vds + Vbi − φ1 ) ekLg − Vbi + φ1 (A.1)
csch(kLg )
b1 =
2
× [(cosh(kL2 − kLg ) − cosh(kL1 − kLg )) (φ2 − φ1 )

+ ekLg (Vbi − φ1 ) − Vbi − Vds + φ3 (A.2)
coth(kLg ) − 1
Fig. 5. Threshold voltage degradation versus normalized damaged zone for a2 =
double-gate, cylindrical-gate, and surrounding-gate MOSFETs. 2


qNf
cylindrical (αDG = 0), and the surrounding-gate (αDG = 0.7) × e kLg
Vbi + Vds − φ2 +
Cox
MOSFETs. It is obviously seen that the cylindrical MOSFETs
are superior to both of the double-gate and surrounding-gate qNf
MOSFETs for less threshold voltage degradation when the + φ2 − − Vbi + (φ2 − φ1 )
Cox
damaged zone is increased. The double-gate MOSFETs will

cause most threshold voltage degradation among the three ekL2 ek(2Lg −L2 )
× cosh(kL1 ) − − (A.3)
devices. Although the surrounding-gate MOSFETs give rise to 2 2
the large threshold voltage rollup/rolloff in comparison with
the cylindrical MOSFETs, it increases the current drive over coth(kLg ) − 1
b2 =
cylindrical MOSFETs due to wider cross-sectional area for 4
the current flow. We should make a promise between keeping
the stability of the threshold voltage and maintaining the high × 2e2kLg Vbi − 2ekLg (Vbi + Vds ) + (φ1 − φ2 )
current drive for choosing either cylindrical or surrounding-gate
MOSFETs in the circuit application. 
× ek(L1 +2Lg ) − ekL2 + ek(2Lg −L1 ) − ek(2Lg −L2 )

 
IV. C ONCLUSION qNf
− 2 φ2 − (e2kLg
−e )
kLg
(A.4)
A compact analytical threshold voltage model for Cox
surrounding-gate MOSFETs with localized interface trapped
coth(kLg ) − 1
charges has been developed. The model thoroughly investigates a3 =
the effect of interface trapped charges with the positive/negative 2
 kL
polarity, the damaged zone, the oxide thickness, and the × e (Vbi + Vds − φ3 ) + φ1 − Vbi
g

diameter of silicon body on the threshold voltage degradation.

When ITTVD is prominent and coupled with short-channel + (φ2 − φ1 ) (cosh(kL1 ) − cosh(kL2 ))] (A.5)
effects, the positive/negative interface trapped charges can ekLg
(coth(kLg ) − 1)
increase/decrease threshold voltage degradation caused by b3 =
2
DIBL. In addition, the thin oxide will improve the threshold 
voltage behavior when the interface trapped charges are × ekLg (Vbi − φ1 ) − Vbi − Vds + φ1
presented and the damaged zone is increased. Instead of a 
+ ekLg (φ2 − φ1 ) (cosh(kL2 ) − cosh(kL1 )) (A.6)
small diameter of silicon film, a large diameter of silicon body
is required to resist the threshold voltage rollup when the
negative interface trapped charges are presented. The model where k = 1/λ, L1 = Lg − Ld − Ls , and L2 = Lg − Ls .
is verified by the 3-D simulation results and can be efficiently With known ai , bi , and φi and solving for Vgs in (8), the
applied to explore the threshold voltage behavior for the threshold voltage can be achieved, and the coefficients in (9)
charge-trapped memory device. and (10) are expressed as

Ai = 1 − 4αi γi (A.7)
A PPENDIX
Bi = −2(ΦB + βi γi + αi ηi ) (A.8)
According to the continuity of both electric field and poten-  
tial at L1 and L2 and the boundary conditions at the source/ Ci = 4 φ2B − βi ηi (A.9)
CHIANG: THRESHOLD VOLTAGE OF SURROUNDING-GATE MOSFET WITH TRAPPED CHARGE 571

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4

2qNf 2kLg
× (e − ekLg ) + (φ1 − φ2 ) Te-Kuang Chiang (M’04) received the B.S. degree in electrical engineering
Cox from the National Cheng Kung University, Tainan, Taiwan, in 1985, the M.S.
 degree in electrical engineering from the State University of New York, Stony
× ek(L1 +2Lg ) − ekL2 +ek(2Lg−L1 ) − ek(2Lg −L2 ) Brook, in 1989, and the Ph.D. degree in electrical engineering from the National
Cheng Kung University in 1998.
 In 1991, he joined the Department of Electronic Engineering, Southern
Taiwan University, Tainan. Since 2008, he has been with the Department of
− 2ekLg (Vbi + Vds ) + 2e2kLg Vbi (A.17) Electrical Engineering, National University of Kaohsiung, Kaohsiung, Taiwan,
where he is currently a Professor and the Department Chair.
ekLg (coth(kLg ) − 1) Since 2003, Prof. Chiang has been a member of the IEEE Electron Device
η3 = Society (EDS). Since 2005, he has been involved with the organization of the
2 IEEE International Conference on Electron Devices and Solid-State Circuits
 and the IEEE International Conference on Solid-State and Integrated Circuits
× (ekLg − 1)Vbi − Vds + ekLg (φ2 − φ1 ) Technology, where he has given invited talks. Since 2006, he has served as the
× (cosh(kL2 ) − cosh(kL1 ))] . (A.18) IEEE EDS Tainan Chapter Treasurer, Vice Chair, and an IEEE representative
to the EDS Regions/Chapters Committee. He is also a Reviewer of Semi-
conductor Science and Technology, Solid-State Electronics, Microelectronics
Reliability, the Japanese Journal of Applied Physics, the IEEE E LECTRON
D EVICE L ETTERS, and the IEEE T RANSACTIONS ON E LECTRON D EVICES.
ACKNOWLEDGMENT His current research interest is focusing on the device modeling for advanced
metal–oxide–semiconductor field-effect transistors (MOSFET) structures such
The author would like to thank L. Jan-Fan and Y. Ming-Jie as double-gate MOSFET, trigate MOSFET, fin-shaped FET, and surrounding-
for their kind support for the simulation data. gate MOSFET.