Session 11: Modern Routing: from Timing, Reliability

to Machine Learning GLSVLSI’18, May 23-25, 2018, Chicago, IL, USA

Electromigration Design Rule aware Global and Detailed

Routing Algorithm∗
Xiaotao Jia, Jing Wang, Yici Cai, Qiang Zhou
Tsinghua National Laboratory for Information Science and Technology
Department of Computer Science and Technology, Tsinghua University, Beijing, China
jiaxiaotao@outlook.com,j-w16@mails.tsinghua.edu.cn,{caiyc,zhouqiang}@tsinghua.edu.cn

ABSTRACT
Electromigration (EM) in interconnects is becoming a major
concern as the scaling of technology nodes. Electromigration
affects chip performance and signal integrity seriously by
generating shorts or opens, and then shortens the life-time
of integrated circuits. In this paper, we propose an EM-aware
routing algorithm in both global and detailed routing stages.
Based on physics-based EM modeling and analysis, EM issueFigure 2 : [EM failures - Void (Open) and Hillock (short)], Source – W.D. Nix et al. 1992
is modeled as physical design rule. In global routing stage, an Figure 1: EM-failures: Void (open circuit) and
efficient EM-aware Mazerouting algorithm is implemented. hillock (short circuit) [5].
An concurrent EM-aware detailed router is then proposed
based on multi-commodity flow method. Experimental re-
sults show that comparing with general routing algorithm,
the proposed EM-aware algorithm could effectively reduce
EM risk of signal wires by 92% with slight increasing of wire
length and via count.
KEYWORDS
Electromigration, Global Routing, Detailed Routing, Design
Rule
ACM Reference Format:
Xiaotao Jia, Jing Wang, Yici Cai, Qiang Zhou. 2018. Electromi-
gration Design Rule aware Global and Detailed Routing Algo-
rithm. In Proceedings of Great Lakes Symposium on VLSI 2018
(GLSVLSI’18). ACM, New York, NY, USA, 6 pages. https://doi.
org/10.1145/3194554.3194567
1 INTRODUCTION
Electromigration (EM) is becoming a major concern for cur-
rent VLSI designs as the technology nodes advance into the
nanometer regime. It occurs when the current density flow-
ing through the conductor is high enough to cause the drift
of metal ions. EM decreases the reliability of integrated cir-
cuits (ICs). An EM failure may cause either a void (open) or
∗
This work was supported by the National Natural Science Founda-
tion of China (Grand No. 61774091).
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https://doi.org/10.1145/3194554.3194567
a hillock (short) as shown in Fig. 1, which eventually lead-
s to circuit functional error. The 2012 edition of the ITRS
roadmap has predicted that all minimum-sized interconnect-
s would be EM-affected by 2018, potentially restricting any
further downscaling of wire sizes (Fig. 2 [12]). In the latest
edition of the ITRS roadmap, EM is reported as one difficult
challenge for 16 nm technology.
Analog designers have become aware of EM issue for a
long time, and digital designers are now being affected as
well. At 90 nm and before, EM impact on digital ICs, par-
ticularly signal nets, has been minimal, making signal EM
analysis and fixing an optional design step. At 45 nm and
beyond, this is no longer the case. Metal widths are shrink-
ing because of pitch scaling. Interconnects become thinner
and thinner. Wire length continuously increases to meet the
complex device integration demands. These thin and long
interconnects switch at gigahertz speed in order to the push
for higher performance. Once combined, these factors result
in higher current densities, which amplify the effects of signal
EM at advanced technology nodes [5]. With the shrinking of
technology nodes, EM becomes even more critical in digital
circuits on signal nets [11]. As declared by Synopsys, there
are more EM violations on signal interconnects at 28 nm
compared to those at 65 nm and 40 nm.
Analysis, prevention and fixing are three main compo-
nents of an optimal EM solution [6]. EM analysis provides
theoretical guidance for EM violation prevention and fixing.
Analysis accuracy could significantly affect the final EM re-
sults. EM violations fixing is usually processed in post-layout
stage. It is not acceptable to fix those violations manually by
experienced engineers nowadays. Nano-technology requires
fixing method to be automatic, accurate, timing and design
rule checking aware. However, only performing fixing in post-
stage is not an ideal strategy as it would be iterative and may
break down existing results. Furthermore, post-layout fixing
could not make obvious improvement because the increasing
design complexity leaves very limited space for post-layout

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Session 11: Modern Routing: from Timing, Reliability
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Minimum gate length in nm
18 17 15 14 13 12 11 10
Current density in MA/cm²
6 There are likewise some works that model design rules for
5
4
3
2 exact segment currents are only known after the entire topol-
1 ogy of the net has been laid out. Combining current densi-
2014 2016 2018 2020
Year
Currently used manufacturing solutions
Manufacturable EM-robust solutions are known
Manufacturable EM-robust solutions are NOT known
Required current density for driving four inverter gates
Figure 2: Expected evolution of required and max-
imum IC wires. While the required current density
scales with frequency and reducing cross-section, the
maximum tolerable current density is shrinking due
to smaller structure sizes [12].
optimization. As described in [8], current density, temper-
ature, segment width and segment length are several main
factors that cause EM violations. For a given design, the lay-
out is mainly determined in routing stage during which the
segment length and width could be controlled to lower the
probability of EM violation generation. For modern complex
and challenging ICs, the best way to effectively prevent sig-
nal EM violations is to address it as early as possible during
physical design stage.
Related Works: The EM issue was originally discovered
by Gerardin over 100 years ago [5]. It started to become of
practical interest in 1966 with the introduction of the first
ICs. EM has become a significant concern in analog circuit-
s. There are many research works that address EM issue in
routing and post-routing stage. In digital circuits, the EM
issue has been a significant concern in power delivery net-
works for many years. But as the shrinking of technology n-
odes, the EM problem on interconnects i.e. metal wires and
vias is addressed by both academics and industries. Gener-
ally, existing works related to EM could be classified as two
terms: current-driven and design-rule driven.
As described in [6], an integrated clock signal EM solution
is provided during routing stage by IC Compiler. A preven-
tion flow is implemented for clock nets during clock tree syn-
thesis stage. It also includes a signal EM analysis and fixing
flow after routing stage on a timing / route DRC clean data-
base. The work in [3] presents a design strategy using special
signal non-default rules to re-route the wire segments of crit-
ical nets which present a high density and are EM-unsafe.
The work in [14] proposes an EM-aware redundant via inser-
tion algorithm that considers current distribution with dif-
ferent via layouts. However, post-layout optimization space
is limited. In routing stage, EM issue on 3D ICs has been
considered especially around TSVs in [13]. However the work
does not consider other design rules such as spacing. Mag-
ma Inc. introduced Blast Fusion and Blast Noise in order to
achieve a current-density-correct routing of signal nets. Pub-
lic Ltd. offered an integrated routing solution Lyric AMS for
GLSVLSI’18, May 23-25, 2018, Chicago, IL, USA
analog and mixed-signal IC designs with the consideration
of pin current for current-density-correct routing.
9 8 7
EM issue such as [3]. In industrial area, complexity of metal
and via EM rules are also proposed depending on segmen-
t width and segment length [4]. The major challenge facing
any current-driven signal routing is the inherent feature that
2022 2024
ty and net’s layout requirement together as physical design
rules could effectively reduce the EM risk in nanometer ICs.
Our Contributions As described above, EM generation
in ICs is mainly affected by current density, temperature,
segment width and segment length. The best way to reduce
the EM risk is combining these factors together in design
stage. In this paper, an EM design rule aware routing algo-
rithm in both global and detailed routing stages is proposed.
The main contributions of this work are listed as follows.
• EM design rule is proposed based on EM modeling and
analysis. With the EM design rule, it is much easy and
reasonable to consider EM issue in routing stage.
• A sequential EM design rule aware global routing al-
gorithm is proposed. The proposed algorithm could
effectively reduce the EM-unsafe global segments.
• An EM design rule aware detailed routing algorithm
based on multi-commodity flow theory is proposed, for
the first time to our best knowledge. With the guid-
ance of global routing results, the proposed concurrent
detailed routing algorithm could significantly reduce
the EM risk.
The remainder of this paper is organized as follows. Section
2 reviews the EM modeling of signal nets. Section 3 demon-
strates the overall flow of the proposed routing algorithms.
Section 4 proposes EM design rule and discusses the EM-
aware global routing and detailed routing algorithm. Exper-
imental results are demonstrated in Section 5, followed by
the conclusion in Section 6.
2 EM MODELING
Mostly EM reliability assessments are mainly based on the
semi-empirical Black’s equation [1] to estimate the mean
time-to-failure (MTTF). Thus, many EM works during phys-
ical design stage also utilize this model such as the work in
[3]. However, Black’s equation suffers some major problems
in today’s chip design. It is an over-simplified model of the
actual physics for EM failure mechanisms and only work-
s for constant temperature and current density. Recently, a
more physics-based EM model have been proposed to mit-
igate the shortcomings of Black’s equation [8]. In the work
of [8], a dynamic EM model under time-dependent current
and temperature stressing is proposed and a fast stress cal-
culation method (Eqn. (1)) is also proposed to demonstrate
what happened before the MTTF.
 ( ) 
∞ cos (2n+1)πx (2n+1)2 π 2
eZρjl

1 x ∑ l −κ t

σ = σT + − −4 e l2 (1)
Ω 2 l n=0 (2n + 1)2 π 2
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Session 11: Modern Routing: from Timing, Reliability
to Machine Learning
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DZƵůĞƐ
ZĞƐƵůƚƐ
DͲĂǁĂƌĞ'ůŽďĂůZŽƵƚŝŶŐ
dƌĂĐŬƐƐŝŐŶŵĞŶƚ
DͲĂǁĂƌĞĞƚĂŝůĞĚZŽƵƚŝŶŐ
ZĐŚĞĐŬ
Figure 3: Overall flow of the proposed EM-aware
routing algorithm.
Here, l is segment length, j is the current density, σT is
the thermal stress. e, Z and ρ are electronic constants. The
details of these symbols are described in [8].
From Eqn.(1) we can find that the stress is only associ-
ated with current density j, temperature T , segment width
w and segment length l. Lower current density (lower cur-
rent or wider wire), lower temperature and shorter segment
length could reduce the increasing speed of stress, and then
increase the lifetime of chip. This conclusion agrees with
the well-known “Blech Length” [2] which indicates that any
wire whose length is shorter than this threshold will have a
stretched limit for electromigration.
3 OVERALL FLOW
Fig. 3 shows the overall flow of the proposed EM design rule
aware routing algorithm. The inputs are placement results
and EM design rules. Placement results are stored in Ope-
nAccess (OA) format. And EM design rules vary for different
parameters (current density, wire width, wire length, etc.).
Then the proposed EM design rule aware global routing al-
gorithm is performed on the basis of traditional Mazerout-
ing algorithm in a 3D global routing graph. It will penalize
the routing results which violate the EM design rules. Tra-
ditional track assignment algorithm is executed taking the
global routing results as inputs. As the track assignment is
performed layer by layer, EM issue can not be avoided by
a large margin. So it is not considered in this stage. The
last routing stage is EM design rule aware detailed routing
based on multi-commodity flow method. EM design rules are
translated into constraints of an integer linear program (ILP)
problem. These constraints are used to restrict the genera-
tion of EM-unsafe wires. The ILP problem is solved by a
commercial solver. The final step is the design rule checking
(DRC) including open, short, spacing, minarea, EM etc. and
the DRC violations will also be reported.
4 EM DESIGN RULE AWARE
ROUTING ALGORITHM
In this section, we firstly propose EM design rule based
on the EM modeling and analysis described in section 2.
Then an EM-aware routing algorithm restricted by the pro-
posed EM design rule is presented. In our routing algorithm,
divide-and-conquer mechanism is utilized to to reduce the
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GLSVLSI’18, May 23-25, 2018, Chicago, IL, USA
complexity of the routing problem. The full routing flow is
constructed with global routing, track assignment and de-
tailed routing. EM design rules are incorporated into global
routing stage and detailed routing stage.
4.1 EM design rule
The theoretical analysis and modeling of EM prove that the
final layout of chip has significant effects on EM results. It is
therefore necessary to consider EM-related design parame-
ters as early as possible in the physical design flow, especially
in routing stage.
In the IC design flow, exact wire currents are only known
after the entire topology of the net has been laid out. Cur-
rent calculation based on Kirchhoff’s current law requires
the sequence of all terminals. Since it is very hard to calcu-
late the real time currents in routing stage, the current is
usually treated as a constant value. maximum current and
mean current are commonly used. The constant value could
be estimated by some technology files such as process de-
sign kit (PDK). In other words, the current could be a given
and constant value in routing stage and different nets have
different values. Thus, only wire width and wire length are
variable factors in routing stage. Fortunately, it is also the
basic task of routing algorithm that generates physical lay-
out with the requirement of wire shape. In order to reduce
the EM occurrence risk, EM design rules based on this ob-
servation are proposed in this work. For a given net, the
proposed EM design rule requires that the value of s(j, l, w)
should be less than a threshold. The threshold is associated
with signal net parameters such as temperature, working fre-
quency, expected MTTF. In modern ICs, the wire width on
each layer is suggested being uniform. Thus, the EM design
rule could be further simplified as a wire length and current
density dependent design rule in each layer.
4.2 EM-aware Global Routing Algorithm
The implemented global routing algorithm is built on graph-
search technique. The algorithm is guided by the congestion
information associated with routing regions and net topolo-
gies. Before the graph-search technique is implemented in
routing, a global routing graph (GRG) should be construct-
ed firstly. A global router is used to obtain the coarse solu-
tion of GRC to GRC paths for all nets on a GRG. There are
many graph-search techniques for global routing including
Steiner tree based technique, A∗ algorithm and Mazerout-
ing algorithm. Each of them has its own advantages and
disadvantages. In this paper, a multi-level Mazerouting al-
gorithm is implemented to perform global routing in a 3D
routing graph.
At each level, an EM-aware Mazerouting algorithm is ap-
plied as shown in Algorithm 1. The routing process is exe-
cuted window by window at all routing levels. For each given
window, the inputs are net terminal positions and EM con-
straints of all nets locating at this window. At the beginning,
the actual length ActLen of graph edge in current routing
level is calculated using window size and routing grid count
(line 1). Then the algorithm will route all the nets one by
Session 11: Modern Routing: from Timing, Reliability
to Machine Learning GLSVLSI’18, May 23-25, 2018, Chicago, IL, USA

Algorithm 1 EM-aware global routing algorithm Table 1: Sets and variables of detailed routing
Input: Routing window information, routing nets information, set/notion meaning
EM constraints
1: CalActualLength(window, track count) → ActLen; A/N /S arc/node/signal net set
2: for each net i do Anj adjacent arc set of node nj
3: GetWireWidth() → width Anj ,o /Anj ,in arc set that starts from / end at the node nj
4: EM Constr[i] × width/ActLen → σ Anj ,w /Anj ,v metal wire / via arc set of node nj
5: Mazerouting : c(ai ) the capacity of arc ai with value of 0 or 1
6: ··· p(ai ) the cost of arc ai with positive value
7: getPathLength() → L the flow command of node nj with value of
r(sk , nj )
8: ⌊L/σ⌋ → α -1, 0, or 1 that net sk requires
9: StdCost · 2α → EM Cost binary variable,
f (sk , ai )
10: AddEMCost2RoutingCost() flow of signal net sk goes through arc ai
11: ···
∑|S| ∑|A|
one. Based on the specified EM constraints, current densi- min. (f (sk , ai ) · p(ai )) (3a)
k=1 i=1
ty, wire width (may vary for different metal layers) of the s.t. η(sk , nj ) − γ(sk , nj ) = r(sk , nj ), ∀sk ∈ S, ∀nj ∈ N, (3b)
net, we can calculate the maximum step that the router can ∑
η(sk , nj ) = f (sk , a) (3c)
a∈An ,o
run (lines 3–4). Then is the EM-aware 3D Mazerouting. D- j
∑
ifferent from the traditional one, EM design aware routing γ(sk , nj ) =
a∈An ,in
f (sk , a) (3d)
j
algorithm penalizes the paths that exceed the maximum step ∑|S|
f (sk , ai ) ≤ c(ai ), ∀ai ∈ A, (3e)
by Eqn. (2) (lines 7–10). It is obvious that the penalty value k=1
∑|S| ∑
is exponential with the quotient of path length and maxi- f (sk , a) ≤ 2, ∀nj ∈ N, (3f)
k=1 a∈An
j
mum step. The longer the path, the higher the routing cost.
f (sk , ai ) ∈ {0, 1}, ∀sk ∈ S, ∀ai ∈ A. (3g)
The StdCost in Algorithm 1 and Eqn. (2) represents the
routing cost of an edge used in general purpose routing al-
symbols and variables are listed in TABLE 1 to describe the
gorithm. Finally, the algorithm will select a path with the
routing model based on the routing graph. The meaning of
lowest routing cost.

StdCost if σ ≤ L
each set or variable is described in the second column. Based



 on those sets and variables, multi-commodity flow based ILP
StdCost · 2 if σ < L ≤ 2 · σ
EM Cost =


.
.
(2) formulation of detailed routing problem is built as Eqn. (3).

 .

 The objective function (3a) is to minimize the total routing
StdCost · 2n−1 if (n − 1) · σ < L ≤ n · σ
After the global routing, track assignment is implement- cost. Constraints (3b) are used to connect all the terminals
ed to assign global routing segments to each routing track. of a net together i.e. ensure that there are no open nets af-
Then the detailed routing algorithm described in the follow- ter routing. Arc and node capacity constraints (3e)(3f) could
ing section will take its results as inputs. guarantee no short violations are generated. In order to build
a practical detailed router, spacing design constraints learn-
4.3 EM-aware Concurrent Detailed
ing from [9, 10] are also formulated in this work. Our ILP
Routing Algorithm formulation is very similar to that in [9, 10]. However, EM
It has been found during our experiments that after the track related constraints are seamlessly integrated in our model
assignment, there are many segments that have a high prob- which will be described in the following sections.
ability of generating EM violations because of long distance, 4.3.2 Algorithm of Finding Net Detour Window. As dis-
even though EM-aware global routing algorithm is imple- cussed above, EM design rule aware detailed router is de-
mented. Thus, it is necessary to propose an EM-aware de- sirable to reduce the EM occurrence risk. However, it is not
tailed routing algorithm to shorten the long wires by some necessary that all the routing windows execute EM-aware
techniques such as net detour or layer shifting. In this sec- detailed routing. For a given segment, if it is too long that
tion, an EM-aware concurrent detailed routing algorithm is may generate EM violation, only part of windows that it goes
proposed based on multi-commodity flow method. through need integrate the EM constraints. The integration
4.3.1 Concurrent Detailed Routing Model. Normally, the of EM constraints makes the ILP problem much hard to solve
detailed routing problem of a chip is divided into many sub- and may increase the wirelength and via count. Therefor, by
problems based on global routing cells. Each subproblem this way, we can not only achieve the goal of reducing EM
is simplified as a path-finding problem. To finish the rout- occurrence risk but also maintain the routing quality and
ing task, a routing graph based on given routing resources reduce runtime. In this section, an algorithm of finding net
(routing layers, routing grids, blockages etc.) is built first- detour window is proposed as Algorithm 2 before detailed
ly. Because there are always several available routing layers, routing. For a given global segment on layer i, assuming that
the routing graph G = (N, A) is three dimensional. The con- the segment length is l and the maximum length for EM-safe
current detailed routing model is based on multi-commodity calculated by EM rules, current density and layer width is
flow method. In order to indicate the commodity flow direc- σ (line 2–3). If l ≤ σ, no EM ILP constraints are needed for
tion, the routing graph is formulated as directed. Some set this segment. Otherwise only n = ⌊l/σ⌋ window(s) needs to

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Session 11: Modern Routing: from Timing, Reliability
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Algorithm 2 Algorithm of finding net detour window
Input: Track assignment results, EM constraints
1: for each segment s do
2: getLength(s) → l ; getWidth(s) → width
3: getMaxLength(width, EM Const) → σ
4: if l > σ then
5: n = ⌊l/σ⌋
6: for k = {1, 2, ..., n} do
7: getWindow(s, k) → w
8: w.unsaf e segs.push back(s)
9: for each routing window w do
10: model ILP formulation as Eqn.(3)
11: if w.unsaf e segs.size()> 0 then
12: add EM constraints to Eqn.(3)
13: solve ILP problem
build EM ILP constraints for this segment. If l > σ, the seg-
ment is termed as EM-unsafe segment in this paper. Then
the segments will be partitioned evenly by n points. Those
windows where the partition points locating at need to build
EM ILP constraints for this segment. In routing stage, de-
tailed router will be executed window by window. For each
window, if there are one or more segments that have to be
detoured in it, EM design rule based constraints described
in 4.3.3 will be formulated and added into Eqn. (3).
4.3.3 EM design rule based ILP constraints. Algorithm 2
collects all the windows in which EM-aware detailed routing
algorithm is performed. At the same time, it determines the
segment set that need to formulate EM ILP constraints for
each window. Now EM-aware detailed routing model is pro-
posed. On the basis of concurrent detailed routing model in
section 4.3.1, EM ILP constraints are formulated in order to
detour the corresponding wires by Algorithm 3. For a giv-
en routing window, firstly we need to estimate whether or
not it is an EM-unsafe window. If yes, EM ILP constraints
will be formulated. Concurrent detailed routing model could
route two-terminal and three-terminal nets simultaneously,
but this work will only formulate EM ILP constraints for
two-terminal nets. Because EM modeling of multi-branch
and 3D wires is still inadequate. Based on the results of
Algorithm 2, we could get access of the necessary segment
information such as terminal position. It is restricted that
two terminals (T 1 and T 2) of an EM-unsafe segment are lo-
cated at the same row or column, otherwise, EM constraints
will be not formulated. Based on the segment information,
EM ILP constraint(s) are formulated as Equation (4). The e-
quation is under construction to make sure that the wire has
a detour in other layer rather than goes through the window
by a line. It is to be noted that not all the variables in this
routing region need to be collected into EM ILP constraints.
Assuming that the segment is horizontal and the row index
that the segment locating at is r. k is the net index that the
segment is owned to. The constraint only collects the edge
variables associated with net k and row r, but associated via
edges are not
∑
collected∑as Eqn.(4) shows.
col cnt
f (sk , a) ≤ col cnt − 2
j=1,j=j+2 a∈An ,w
j
Here, nj is the node in the rth row. col cnt is the routing
track count, so there are col count − 1 edges (ignore edge
GLSVLSI’18, May 23-25, 2018, Chicago, IL, USA
Algorithm 3 Algorithm of formulating EM ILP constraints
Input: Routing window w
Input: routing nets information
1: if w.unsaf e segs.size() ≤ 0 then
2: continue;
3: for each s in unsaf e segs do
4: if s.T 1.row = s.T 2.row and s.T 1.col = s.T 2.col then
5: modelEMConstraints(s)//based on Eqn. (4)
direction). If routing path is forbidden to go through the
window by a line, col count − 2 edges could be used at most.
Thus the right hand value of Eqn. (4) is col cnt − 2.
In order to make the work easier to comprehend, glob-
al and detailed routing algorithm with the consideration of
EM issue are simplified as EMGR and EMDR, respectively, other-
wise are QGR and QDR (routing-quality-driven global/detailed
routing algorithm [10]).
5 EXPERIMENTAL RESULTS
The proposed EM-aware routing algorithm is implemented
with C++ language on Linux server with 2.6 GHz Intel Xeon
CPU and 16 GB memory. In detailed routing stage, GUROBI
[7] is applied as our ILP solver. Our experiments are execut-
ed on five industry benchmarks with 45 nm library on OA
format which are cited from [10] and have been placed by
Encounter. However, we could only get access to the physi-
cal layout information of these benchmarks and no current
information could obtain. In our experiments, the maximum
length of each net is assigned randomly with the range of 6
to 10 times of GRC width. These random length values could
be replaced by real current information if it is available.
In order to demonstrate the effectiveness of the proposed
algorithm, some comparisons are made between routing al-
gorithms with and without the consideration of EM issue.
The metrics for comparison in the experiments are total
wire length (WL) measured by millimeter, total via count
(#Via), DRC violation count (#DRC) and runtime (Time)
measured by second. Furthermore, we propose another com-
parison parameter, EM-unsafe wire length (EMWL). It is cal-
culated by the length sum of global segments or metal wires
whose length exceeds the corresponding EM threshold. The
larger the EM-unsafe wire length, the greater the probability
of EM violation generation.
5.1 Effectiveness of EM-aware global
routing algorithm
In this section, some experimental results are demonstrated
to prove the effectiveness of the proposed EM-aware global
routing algorithm. In TABLE 2, the first column indicates
two global routing algorithm QGR and EMGR. The second col-
umn shows four comparison metrics. Columns 3-7 are exper-
imental results of five different benchmarks. The last column
is the comparison results in average. The third row in TA-
BLE 2 shows the net count of each benchmark. It could be
seen from the comparison that comparing with QGR, EMGR
(4) could averagely reduce the EM-unsafe wire length by 26%
at the cost of slight increasing of wire length, via count and
runtime by 1%, 3% and 12%, respectively.
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Table 2: Effectiveness of EM-aware GR algorithm study the effectiveness of overall EM-aware routing flow i.e.
Routing Benchmarks Flow4. Comparing with Flow3, Flow4 could further reduce
Metrics Comp.
Flow the EM-unsafe wire length by 5%. Meanwhile, DRC count
chip1 chip2 chip3 chip4 chip5
#Net - 36k 52k 10k 91k 100k - is also decreased by 9%. Compared with QGR, EMGR reduces
WL 645 820 1657 1519 1691 1
the subproblem count that should take EM into considera-
#VIA 351 380 738 665 739 1 tion in detailed routing stage. So detailed routing in Flow4
QGR EMWL 219 429 953 902 1019 1
Time 27.65 23.55 54.18 50.27 52.07 1 spends less time that in Flow3. Finally, the entire runtime of
WL 645 823 1667 1528 1701 1.01 Flow4 is reduced by 12% comparing with Flow3. While the
#VIA 354 391 766 693 769 1.03 routing quality is almost the same. Comparing with Flow1,
EMGR EMWL 165 324 718 662 752 0.74
Time 28.91 26.01 61.04 58.72 58.47 1.12 Flow4 finally reduces the EM-unsafe wire length by 92% at
the cost of 1.96× runtime. The results prove the effective-
ness of EMGR once again. These comparisons indicate that
Table 3: Comparison of different routing flow the proposed EM-aware routing algorithm could effectively
reduce the EM-unsafe wire length, thus, reduce the proba-
Routing Benchmarks
Metrics Comp. bility of EM violation generation. At the same time, there
Flow
chip1 chip2 chip3 chip4 chip5
are only a minor loss of the routing quality.
WL 647 827 1674 1536 1709 1
Flow1:
QGR
#VIA
EMWL
370
117
401
218
780
471
704
444
780
504
1
1
6 CONCLUSION
+
#DRC 61 94 166 156 164 1 In this paper, electromigration issue is considered as a de-
QDR
Time 1033 1165 2154 1925 2302 1
sign rule based on physics-based EM modeling and analysis.
WL 649 831 1682 1543 1717 1.00
Flow2: EM-aware global routing and detailed routing algorithms are
#VIA 371 406 793 717 796 1.02
EMGR
EMWL 92 168 355 332 371 0.75
+
#DRC 56 81 168 160 177 1.04
proposed to reduce the EM violation generating probabili-
QDR
Time 1038 1115 2228 2001 2268 1.01 ty. Experiments demonstrate that the proposed algorithms
Flow3:
WL 651 836 1693 1553 1729 1.01 reduce the EM-unsafe wire length by 92% which is helpful
#VIA 373 409 798 722 802 1.02
QGR
EMWL 11 16 42 38 42 0.09
to increase the chip reliability. In the future work, we will
+
EMDR
#DRC 62 79 171 159 181 1.02 take via EM model into consideration to make the algorith-
Time 2061 2566 4926 4447 5087 2.22
m much complete and test the proposed algorithm using
WL 652 835 1692 1552 1728 1.01
Flow4:
#VIA 373 405 788 712 789 1.01 benchmarks with advanced technology nodes.
EMGR
EMWL 11 15 39 37 40 0.08
+
EMDR
#DRC 58 83 152 170 152 0.93 REFERENCES
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