LPU

ASSIGNMENT
NO1 OF
INTRODUCTION
TO COMPUTER
ORGANISATION &
ARCHITECTURE
SUBMITTED TO
SUBMITTED BY KETAN SOOD
VARUN KATOCH
 E3801
B53

BCA-MCA

PART A
Q1. Identify at least two application areas (discuss their roles also) for

Encoder/Decoder

Multiplexers/Demultiplexer

Flip Flops

ANS (A) Encoder/Decoder

An encoder is a device that is used to convert a signal or certain data into code.
This kind of conversion is done for a variety of reasons, the most common being
data compression. Other reasons for using encoders include data encryption for
making the data secure and translating data from one code to another new or
existing code. Encoders may be analog or digital devices. In analog devices, the
encoding is done using analog circuitry, while in digital encoders the encoding is
done using program algorithms. Some examples of encoders are multiplexers,
compressors, and linear and rotary encoders.

A decoder, on the other hand, functions the reverse of an encoder. It is a device

that is used to decode an encoded signal or data. It does this to help retrieve the
data that was encoded in the first place. Both encoders and decoders usually
function in tandem, i.e., an application that uses an encoder would ideally also
require a decoder. There are different types of decoders, e.g. demultiplexers.

Multiplexers (MUX)

For logic function realizations, instead of logic gates, Multiplexers can also be
used

Consider a boolean function f={1,2,6,7}. Here input variables are A,B,C.

Multiplexer schematic for multiplexer is shown in figure 13.1

Figure 13.1: ( ) multiplexer implementation of logic

function

Depending on the contorl input combination specfic input is connected to the

single output of multiplexer.

(13.1
)

When multiplexer is used to implement the above function. We connect

boolean logic '1' at the inputs corresponding to control inputs ABC= 1, 2, 4, and
6. For all other input boolean logic '0' is connected.

In case we take a multiplexer we can make as control input and then

determine what should be connected at the inputs of multiplexer as shown
below.

(13.2
)

(13.3
)

(13.4
)

(13.5
)
The realization is shown in figure 13.2 using a Mux.

Figure 13.2: Multiplexer ( ) Implementation

DEMULTIPLEXER
A demultiplexer (DMUX) is a device which essentially performs the opposite
operation to the MUX. That is, it functions as an electronic switch (/data
distributor) to route an incoming data signal to one of several outputs. Figure 2-
15 shows the logic symbol for the 1-line-to-4-line demultiplexer circuit and Table
2-15 list the associated Truth table. The corresponding logic circuit
implementation is then shown in Figure 2-16.

Figure 2-15 Logic symbol for 1-line-to-4-line demultiplexer

 Address Outputs

Data
S1 S0 Y0 Y1 Y2 Y3

D 0 0 D 0 0 0

D 0 1 0 D 0 0

D 1 0 0 0 D 0

D 1 1 0 0 0 D

Table 2 -15 Demultiplexer Function Tables

(C) FLIP FLOP

Flip-Flops and Latches

An SR latch is shown in figure 13.3. The latch Truth table is shown in the
following table. The two inputs, S and R denote ``set'' and ``reset'' respectively.
The latch has memory, and the present output is dependent on the state of the
latch. Thus the output at instant, denoted by is dependent on output at

instant, denoted by .

Figure 13.3: Construction of a latch from NOR

gates

Students should verify the veracity of the truth table from the figure 13.3.

S R

1 0 1 0

0 1 0 1

1 1 0 0

0 0

Note that in state, both and are 0, which seems absurd. Thus,
conventionally, the state is said to be ``not allowed''.

A similar latch, known as latch is constructed using NAND gates (as opposed
to NOR gates for latch). The students should again check that the working of
the latch coheres with that of the truth table.
 Figure 13.4: Construction of a latch from NAND
gates

0 1 1 0

1 0 0 1

0 0 1 1

1 1

To avoid ``race'' between the inputs, to have a control on when the input affects
the latch, the circuit 13.5 is often implemented.

Figure 13.5: Circuit to avoid ``race'' condition

The inputs have an effect on the latch only when , otherwise, the previous
state is maintained. The input may be a clock, so that whatever transitions in
and take place before the clock changes to do not affect the outputs,
and only when the inputs have become stable is the system affected.

Sequential circuits

In the above circuit, we have the problem of multiple tranistions when the clock
is active.

Master Slave Flip-Flop (S-R)

When , , and are both 1. Therefore, it is an undefined condition.

This can be eliminated by proper feedback.
for the above circuit, the truth table is

1 1

0 1 0

1 0 1

0 0
The problem with the circuit shown above is that when clock =1, the feedback
will cause oscillatinons and when clock goes zero, the predicting the ouput state
is difficult. On the other hand, master slave configuration does not allow
oscillation.

Edge triggered Flip-Flop

The above diagram shows a positive edge triggered flip-flop. The truth table is as
follows

0 1 0 1

1 0 1 0

0 0

1 1
Q2. Discuss the basic logic behind counters i.e. how will you obtain 1000(8) from
0111(7)? How will you implement the same? How many flip flops will be
complemented in a 10 bit binary counter to reach the next count after
1001100111?

Ans-

Complementing the lower-order bit.

Complementing the second order bit because the 1st bits of 0111 are 1.

Complementing the third order bit because the 1st two bits of 0111 are 1’s

Complementing the fourth order bit because the 1st three bits of 0111 are all 1’s

The number of flip flops will be complemented in a 10 bit binary counter to each
the next after 1001100111 is 4 bit because at fourth bit. It is changing from 0 to
1.

Q3. What will happen if buffer gate in the clock input of the register is removed?
What is the role of clear and load signals in designing register with parallel load?

Ans3 The buffer gate in the clock input reduces the power, requirement from the
clock generator. Less power is required when the clock is connected to only one
input gate instead of the power consuming that four inputs could have required.
If the buffer were not used. If the buffer gate is then a constant amount of power
flow in the register and it can cause fire in register.

The load input in the resister determines the action to be taken with each clock
pulse.
 PART B
Q4. The content of a four bit register is initially 1101. The register is shifted six
times to the right with the serial input being 101101. What is the content of the
register after each shift?

Ans4 Initial bit of resister is 1101.

& serial input is 101101.

1st right shift is 1110.

2nd shift is 0111.

3rd shift is 1011.

4th shift is 1101.

5th shift is 0110.

6th shift is 1011.

Q5. Draw the block diagram to implement following register transfer statement

yT2 : R2←R1, R1←R2

Ans- 5

LOAD
R Control
p
2 circuit

N N

R1
Q6. A digital computer has a common bus system for 16 registers of 32 bit each.
The bus is constructed with multiplexers.

How many selection inputs are there in each multiplexer?

What sizes of multiplexers are needed?

How many multiplexers are there in the bus?

ANS 6 a) 16 registers = 24 => 4 selection inputs

b) 16 registers => 16 x 1 line multiplexers

c) 32 bits / register => 32 multiplexers