A Project Report

on

ENERGY EFFICIENT SYNCHRONOUS SEQUENTIAL

CIRCUITS DESIGN USING CLOCK GATING
Submitted in partial fulfillment of the requirement for the award of the degree of

MASTER OF TECHNOLOGY

in

VERY LARGE SCALE INTEGRATION (VLSI)

Submitted by

SANAM JYOTHI 15ME1D5716

Under the Esteemed Guidance of
Mr. DONE SRIDHAR
M. Tech.,MISTE,(Ph. D)
Associate Professor
Mr.

Department of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING
(Approved by AICTE, New Delhi, Affiliated to JNTUK: Kakinada)
An ISO 9001:2008 certified, “AA’ Rated Institution by APKM in AP & NAAC B++ Grade
NH 5 Bypass Road, Vatluru (V), ELURU-534 007, W. G. Dist., A. P,
Website: www.rcee.ac.in. Phone: 08812 215150,215152. Fax: 08812 215005

2016-17
i
 RAMACHANDRA COLLEGE OF ENGINEERING
(Approved by AICTE, New Delhi, Affiliated to JNTUK: Kakinada)
An ISO 9001:2008 certified, “AA’ Rated Institution by APKM in AP & NAAC B++ Grade
NH 5 Bypass Road, Vatluru (V), ELURU-534 007, W. G. Dist., A. P,
Website: www.rcee.ac.in. Phone: 08812 215150,215152. Fax: 08812 215005

Department of Electronics and Communication Engineering

BONAFIDE CERTIFICATE

This is to certify that this project report entitled “ENERGY EFFICIENT

SYNCHRONOUS SEQUENTIAL CIRCUITS DESIGN USING CLOCK GATING” is
being submitted by SANAM JYOTHI 15ME1D5716 in partial fulfillment of MASTER OF
TECHNOLOGY in VERY LARGE SCALE INTEGRATION (VLSI) is a bonafide work
carried out under my guidance and supervision during the academic year 2016-2017 and it has
been found worthy of acceptance according to the requirement of the university.

Project Guide Head of the Dept.

Mr. DONE SRIDHAR Dr. UDARA YEDUKONDALU
M. Tech., MISTE., (Ph.D) M. Tech., Ph. D
Associate Professor Professor

Internal Examiner External Examiner

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 ACKNOWLEDGEMENTS
Many individuals have contributed towards fulfillment of this project in one or
many ways. This project could not have seen light without the help of all these people. It
will be my pleasure and responsibility to acknowledge their contributions.

I thank Mr. DONE SRIDHAR, Associate Professor, Department of ECE for his kind
cooperation and expert guidance in the successful completion of this project. I sincerely thank
his for his valuable time and enormous patience.

I thank Dr. UDARA YEDUKONDALU, Professor & Head, Department of ECE

for his valuable time and enormous patience. I thank him from the bottom of my heart for
providing and allowing me to use all the facilities of the Department.

I thank Prof. Dr. DOLA SANJAY S, Principal for providing us with all the
infrastructural facilities towards successful completion of this project.

I thank Sri. K. VENUGOPAL, Secretary, RCE for providing with good academic
and research environment in the Department.

I thank all the teaching and non-teaching members of the Department for their
help and encouragement.

I thank my parents, friends and all my gurus who stood for me and taught me to
stand against all odds in life. I also thank them for educating me in one or other way.

SANAM JYOTHI 15ME1D5716

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 ABSTRACT

The power consumption and area reduction are the key challenges in the Very Large
Scale Integration (VLSI) circuit design. Power consumption and Area reduction plays a
major role in sequential circuit design. Shift register is the main building block in the VLSI
circuits. The shift register is composed of clock inter connection network and timing
elements such as flip-Flops and latches. The shift registers are design using edge triggered
flip flops but the use of latches for shift register design also optimizes the area. This project
introduces a low power and area efficient shift register using pulsed latch and pulse
generation circuit. If the Flip-Flop is replaced with the pulsed latch the area and power
consumption can be reduced to 50% in the shift register. For this design a non overlap clock
pulses are used. This solves the timing problem between pulsed latches through the use of
multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed
clock signal. To minimize power consumption various non overlap delayed pulsed clock
signal design is proposed for data synchronization in an exceedingly multi bit shift register.
Further, this project is enhanced by using clock gating technique for further reduction of
power parameter.

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 TABLE OF CONTENT
Chapter Page No.
Acknowledgments iii
Abstract iv
Table of Content v
List of Figures vii
List of Table ix
CHAPTER – 1 1
INTRODUCTION 1
1.1 INTRODUCTION 1
CHAPTER – 2 9
LITERATURE SURVEY 9
2.1 LITERATURE SURVEY 9
2.2 Sequential Logic Circuits: 11
2.3 Classification of Sequential Logic: 11
2.4 Sequential Feedback Loop 13
2.5 SR Flip-Flop 13
2.6 The NAND Gate SR Flip-Flop 13
2.7 The Basic SR Flip-flop 14
2.8 S-R Flip-flop Switching Diagram 15
2.9 Positive NAND Gate SR Flip-flop 16
2.10 The NOR Gate SR Flip-flop 17
2.11 SR Flip Flop Switch Debounce Circuit 17
2.12 Quad SR Bistable Latch 74LS279 18
2.13 Gated or Clocked SR Flip-Flop 19
2.14 SHIFT REGISTER: 19
2.15 Serial-in to Parallel-out (SIPO) Shift Register 21
2.16 Serial-in to Serial-out (SISO) Shift Register 23
2.17 Parallel-in to Serial-out (PISO) Shift Register 24
2.18 Effect of PVT variations on pulsed latches: 25
CHAPTER – 3 29
PROPOSED TECHNIQUE 29
3.1 PROPOSED TECHNIQUE 29

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CHAPTER – 4 33
4.1 EXISTING TECHNIQUE: 33
4.1.1 Clock gating based reconfigurable pulsed latches: 33
4. 2 VLSI DESIGN - MOS TRANSISTOR: 35
CHAPTER – 5 52
RESULT 52
CONCLUSION 53
REFERENCES 54

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 List of Figures
Figure Page No.

Fig. 1.1 (a) Master-slave flip-flop (b) Pulsed latch 6

Fig. 2.1: Basic Sequential Design 11
Fig. 2.2: Sequential operation 12
Fig. 2.3: Storing mechanism. 13
Fig. 2.4: SR Flip-flops 14
Fig. 2.5: NAND based latch 16
Fig. 2.6: NOR based latch 17
Fig. 2.7: Timing diagram 17
Fig. 2.8: DUAL gate IC 18
Fig. 2.9: SR clocked latch 19
Fig. 2.10: Shift register 21
Fig. 2.11: Ring counter 21
Fig. 2.12: 4 bit register 23
Fig. 2.13: Parallel register 24
Fig. 2.14: parallel data register 25
Fig. 3.1: The basic construction of a simple pulser 29
Fig. 3.2: The proposed header switches-based pulser design 30
Fig. 3.3: The proposed MUX-based pulser design 31
Fig. 4.1: MOS structure contains three layers 35
Fig. 4.2: Band gap between conduction band and valance band 36
Fig. 4.3: The energy band diagram of components that make up the MOS. 37
Fig. 4.4: combined energy band diagram of MOS system 37
Fig. 4.5: The cross sectional view of an n-channel MOSFET, operating
in linear region 38
Fig. 4.6: The cross sectional view of n-channel MOSFET operating at
the edge of saturation region 39
Fig. 4.7: Drain – depletion region and are accelerated towards the drain
in high electric field 39
Fig. 4.8: Direction is perpendicular to the surface and y – direction is parallel
to the surface. 40
Fig. 4.9: The characteristics shown in the figure are ideal. 43

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Fig. 4.10: The generalized circuit structure of an nMOS inverter 43
Fig. 4.11: The basic structure of a resistive load inverter 44
Fig. 4.12: Inverter with N type MOSFET Load 45
Fig. 4.13: The linear enhancement load inverter is shown in the fig. (b).
It always 45
Fig. 4.14: Depletion Load NMOS 46
Fig. 4.15: The voltage transfer characteristics of the depletion load inverter 47
Fig. 4.16: The CMOS inverter circuit 48
Fig. 4.17: The VTC of CMOS is shown in the figure below 50

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 LIST OF TABLE
Table Page No.
Table 2.1 Truth Table for this Set-Reset Function 15
Table 2.2 Basic Data Movement Through A Shift Register 22
Table 4.1: For different value of input voltages, the operating regions are
listed below for both transistors. 49

ix
 CHAPTER – 1

INTRODUCTION

1.1 INTRODUCTION

Flip-flops and latches are affecting elemental repertory particle recycled largely in
all different variety of digital circuits. The present technology digital designs utilize in-
depth pipelining techniques also multiplied flip-flops easy modules like as shift register
files. A large allocation regarding effective clock power have place recycled into pick up
the particular successive elements. By reduction the clock power of latches and flip-flops,
the entire chip power can be reduced. Flip-flops appears new different Structures, parallel
as D- flip-flops, Tflip-flops and JK-flip-flops, of these D-Flip flop is the better standard
one. A regular Single Edge Triggered flip-flop data each of two powerful falling edge
either powerful rising edge of the clock period. Powerful single edge triggered latches
continue regularly configured as flip-flop outline, i.e., the sequential structures seeing two
flip-flops in cascade. The rapid growth in semiconductor devices and VLSI designs has
led to the development of high performance designs with enhanced reliability, customized
size and low power, and because of the power dissipation is critical issue for battery
operated systems.

Therefore the designs are needed to be consuming less power while maintaining
comparable performance. So everyone in VLSI design must think about area utilization
and power dissipation In digital design flip-flops and latches are basic storage elements.
Flip flops are precarious timing elements in digital circuits which have a great impact on
speed and power consumption. In VLSI chip design reducing power has become a
important consideration of an performance and area. The Shift register is a type of
sequential circuit it is mainly used for storage or transfer digital data. Low power
consumption and area reduction is one of the main objectives in the designing of VLSI
design.

The Shift register is the basic building block in VLSI circuits. It is commonly used
in many applications. The architecture of shift register is quite simple. The M bit shift
register can be is composed of M data flip-flops. The smallest flip-flops are suitable for
designing of shift register to reduce the area and power consumption. Latches and flip-
flops are the basic elements for storing information. The flip-flops and latches could be
grouped under the static and dynamic design styles. One latch or flip-flop can store one

1
bit of information. The main difference between latches and flip-flops is that for latches,
their outputs are constantly affected by their inputs as long as the enable signal is
asserted. In other words, when they are enabled, their content changes immediately when
their inputs change. Flip-flops, on the other hand, have their content change only either at
the rising or falling edge of the enable signal. This enable signal is usually the controlling
clock signal. After the rising or falling edge of the clock, the flip-flop content remains
constant even if the input changes.

The shift registers are commonly used for memory designs. The shift registers are
design using edge triggered flip flops. All the flip flops are synchronized through clock
signals. The increase in word length of shift register will increase the number of flip flops.
The edge triggered flip flops are design with two or more than two latches. The general
structure of flip flop is design using master slave latches. The internal structure of shift
register composed of N number of series connected D flip flops. The latches are design
using combination multiplexer logic cell using transmission gates. The structure of N bit
shift register is composed of series connected synchronized N number of flip flops. The
shift register is design with cascaded flip flops hence there is no interconnected circuits
between the flip flops hence speed is not the major constraints of shift register design as
compare to area and power. The latches are mostly not used in design of shift register due
to its timing problems. The non overlap pulse latches are the better option of design of
shift registers. It reduces the number of transistors for design which in turn also reduces
the area and power consumption. This paper proposes a low-power and area-efficient shift
register using pulsed latches.

The shift register solves the timing problem using multiple non-overlap delayed
pulsed clock signals instead of the conventional single pulsed clock signal. The shift
register uses a small number of the pulsed clock signals by grouping the latches to several
sub shifter registers and using additional temporary storage latches. 2. OBJECTIVE The
designing of a shift register is quite simple. An n bit shift register is composed of series
connected N data flip-flops.

The speed of the flip flops is of no major constraint here as there are no
connections between the shift registers and flip flops. The smallest flip flop is enough to
drive the requirement of the shift register and for this same reason the pulsed latches have
replaced the flip flops as they are much smaller in size Vis a Vis the flip flops there by
reducing power consumption. Although there are some drawbacks like that of the timing

2
problem, which is easy to overcome by the use of multiple clocked pulses instead of a
simple single pulsed clock. The shift register uses a small number of the pulsed clock
signals by grouping the latches to several sub shifter registers and using additional
temporary storage latches. FLIP-FLOPS are considered the most popular sequential
elements used in conventional ASIC designs.

This is mainly because of the simplicity of their timing model, which makes the
design and timing verification processes much easier. Master-Slave Flip-Flops (MSFFs)
are considered the most common and traditional implementations of flip-flops, due to its
stable operation and its simple timing characteristics. However, the fact that the MSFF
micro-architecture is usually built using two consecutive latches, it takes an appreciable
portion of the clock period, power consumption, and area. A typical MSFF has a
significant nominal timing overhead (sum of the clock-to-Q delay and the setup time) of 6
FO4 (fanout-of-4) and can reach 10 FO4 when considering clock skew and jitter. In
addition, the clock network, including the flops, often consumes one third to one half of
the total dynamic power of the chip. In addition to the mentioned overheads associated
with MSFF, some additional margins, which can reach up to 15% (depending on the sign
off methodology), are usually added to the nominal timing margins to ensure correct
operation under different process, voltage, and temperature (PVT) variations. This, in
turn, increases the already existing high timing and power overheads. For the above
reasons, MSFF can be considered as a good choice for low-to-medium performance
designs as they provide a good balance between delay, power, and easy design and
verification processes for chips working at a relatively low frequency. On the other hand,
high performance custom designs tend to use latches due to their lower timing overhead
that can reach 2 FO4 in some designs.

Although latch based designs are typically robust to clock skew and jitter (due to
the latch transparency period), latches have a complicated timing model, which, in turn,
complicates the design and the verification processes and increases the risk of hold time
violations, especially with PVT variations. To fill in the missing gap between MSFFs and
latches, pulsed latches (sometimes called pulsed flip-flops) have been used in some high-
performance designs. Pulsed latches (PLs) are latches driven by short pulses generated
from the normal clock signal using a pulse generator circuit called a pulser. The pulser
can be either embedded in the latch, or can be separated as a standalone circuit. If the
latter approach is used, a single pulser can be shared by more than one latch.

3
 Thus, it has the advantage of area and power consumption savings over the former
approach, and it is the focus of our discussion in this paper. In addition, the pulsar usage
can eliminate the need for some of the clock buffers used in the clock tree, thus providing
an additional amount of power and area savings. Having only one latch between the input
and the output, PLs have lower timing overhead than MSFFs. At the same time, since the
driving pulse is very short, the transparency period for the latch becomes very narrow,
allowing the PLs to have a timing behavior close to that of MSFFs, to the extent that they
are sometimes classified among flip-flop families.

Also, due to the presence of the narrow transparent window of the latch, pulsed
latches have an inherent tolerance to clock skew and jitter. Since they have fewer
transistors that are triggered by the clock signal, they have the advantage of reducing a
significant amount of clocking power, and they consume much less leakage power
compared to MSFFs due to the smaller area and fewer transistors. One complication in PL
design is the choice of the pulser output pulse width.

Too short of a pulse width may not be enough for the latches to store the input
data correctly, while too long of a pulse width will result in a longer latch transparency
window; which, in turn, increase the timing overhead or can violate hold time
requirements. This issue becomes more complicated when considering different sources
of variations. PVT variations have significant impacts on different circuit components.
Since sequential elements, in general, are by nature time sensitive elements, they are
among the circuit categories that are highly affected by any PVT variations. Since pulsed
latches, in particular, are very time sensitive, good study of the effect of different sources
of variations has to be considered. Since some of these variations, such as voltage and
temperature, are temporal variations that change over the operating period of chips,
careful analysis and design has to be performed to ensure that reliable circuit operation
can always be achieved without any significant loss in performance, power and area.

A SHIFT register is the basic building block in a VLSI circuit. Shift registers are
commonly used in many applications, such as digital filters, communication receivers,
and image processing ICs. Recently, as the size of the image data continues to increase
due to the high demand for high quality image data, the word length of the shifter register
increases to process large image data in image processing ICs. An image-extraction and
vector generation VLSI chip uses a 4K-bit shift register. A 10-bit 208 channel output
LCD column driver IC uses a 2K-bit shift register. A 16-megapixel CMOS image sensor

4
uses a 45K-bit shift register. As the word length of the shifter register increases, the area
and power consumption of the shift register become important design considerations. The
architecture of a shift register is quite simple. An N-bit shift register is composed of
series connected N data flip-flops. The speed of the flip-flop is less important than the
area and power consumption because there is no circuit between flip-flips in the shift
register.

The smallest flip-flop is suitable for the shift register to reduce the area and power
consumption. Recently, pulsed latches have replaced flip-flops in many applications,
because a pulsed latch is much smaller than a flip-flop. But the pulsed latch cannot be
used in a shift. A shift register is the basic building block in a VLSI circuit. Shift registers
are commonly used in many applications, such as digital filters, communication receivers,
and image processing ICs. Recently, as the size of the image data continues to increase
due to the high demand for high quality image data, the word length of the shifter register
increases to process large image data in image processing ICs. An image-extraction and
vector generation VLSI chip uses a 4K-bit shift register. A 10-bit 208 channel output
LCD column driver IC uses a 2K-bit shift register.

A 16-megapixel CMOS image sensor uses a 45K-bit shift register. As the word
length of the shifter register increases, the area and power consumption of the shift
register become important design considerations. The architecture of a shift register is
quite simple. An N-bit shift register is composed of series connected N data flip-flops.
The speed of the flip-flop is less important than the area and power consumption because
there is no circuit between flip-flips in the shift register. The smallest flip-flop is suitable
for the shift register to reduce the area and power consumption. Recently, pulsed latches
have replaced flip-flops in many applications, because a pulsed latch is much smaller than
a flip-flop. But the pulsed latch cannot be used in a shift register due to the timing
problem between pulsed latches. This paper proposes a low-power and area-efficient shift
register using pulsed latches.

The shift register solves the timing problem using multiple non-overlap delayed
pulsed clock signals instead of the conventional single pulsed clock signal. The shift
register uses a small number of the pulsed clock signals by grouping the latches to several
sub shifter registers and using additional temporary storage latches. Flip flops are the
basic storage elements used extensively in all kinds of digital designs. As the feature size

5
of CMOS technology process scaled down according to Moore’s Law, designers are able
to integrate many numbers of transistors onto the same die.

The more transistors there will be more switching and more power dissipated in
the form of heat or radiation. Heat is one of the phenomenon packaging challenges in this
epoch, it is one of the main challenges of low power design methodologies and practices.
Another driver of low power research is the reliability of the integrated circuit. More
switching implies higher average current is expelled and therefore the probability of
reliability issues occurring rises. We are moving from laptops to tablets and even smaller
computing digital systems. With this profound trend continuing and without a match
trending in battery life expectancy, the more low power issues will have to bead dressed.
The current trends will eventually mandate low power design automation on a very large
scale to match the trends of power consumption of today’s and future integrated chips.
Power consumption of Very Large Scale Integrated design is given by generalized
relation, P = CV2f. Since power is proportional to the square of the voltage as per the
relation, voltage scaling is the most prominent way to reduce power dissipation.

Fig.1. (a) Master-slave flip-flop (b) Pulsed latch

However, voltage scaling is results in threshold voltage scaling which bows to the
exponential increase in leakage power. Though several contributions have been made to
the art of single edge triggered flip-flops, a need evidently occurs for a design that further
improves the performance of single edge triggered flip-flops patterns. The architecture of
a shift register is quite simple. An N-bit shift register is composed of series connected N
data flip-flops.

The speed of the flip flop is less important than the area and power consumption
because there is no circuit between flip-flip sin the shift register. The smallest flip-flop is
suitable for the shift register to reduce the area and power consumption. Recently, pulsed

6
latches have replaced flip-flops in many applications, because a pulsed latch is much
smaller than a flip-flop. But the pulsed latch cannot be used in a shift register due to the
timing problem between pulsed latches that can transfer data in three different modes.

Like a parallel register it can load and transmit data in parallel. Like shift registers
it can load and transmit data in serial fashions, through left shifts or right shifts. In
addition, the universal shift register can combine the capabilities of both parallel and shift
registers to accomplish tasks that neither basic type of register can perform on its own.
For instance, on a particular job a universal register can load data in series (e.g. through a
sequence of left shifts) and then transmit/output data in parallel. Universal shift registers,
as all other types of registers, are used in computers as memory elements. Although other
types of memory devices are used for the efficient storage of very large volume of data,
from a digital system perspective when we say computer memory we mean registers.

In fact, all the operations in a digital system are performed on registers. Examples
of such operations include multiplication, division, and data transfer. Due to increasing
demand of battery operated portable handheld electronic devices like laptops, palmtops
and wireless communication systems (personal digital assistants and personal
communicators) the focus of the VLSI industry has been shifted towards low power and
high performance circuits. Flip-flops and latches are the basic sequential elements used
for realizing digital systems like Universal shift Register. The flip-flops used in digital
systems can be either dynamic or static based on their functionality when the clock is
stopped/grounded, but the power is maintained. From a low power perspective, flip-flops
are clocked at the operating frequency of the system and consume about 30%-70% of the
total power dissipation in the system which also includes the power dissipated in the
clocking network of latches and flip-flops is prime The maximum speed at which
synchronous systems can operate is determined by flip-flops since they are the starting
and ending points of signal delay paths.

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PROBLEM STATEMENT

The main challenges for designing low power area efficient shift registers using latches is
to optimize power & reduce the area without affecting the response or timing problem.

 Solving Timing Problem: Timing problem remains silent issue which stops the usage
of pulse latch in shift register. The output signal of first latch changes correctly
because input signal of first latch is constant during the clock pulse width T-Pulse. But
the second latch Q2 has uncertain output signal because input from Q1 changes during
clock pulse width. So to avoid this timing problem a delay circuit is introduced. As a
result, all latches have constant input signals during the clock pulse width and no
timing problem occurs between the latches.
 Reduced Area: Area required for Shift register using flip-flops is twice than that of
shift registers using latches because a flip-flop consists of two latches. Thus area is
reduced by 50% by replacing flip-flops with latches.
 Reduced Power: Flip-flop consumes near about 50% of total power because in
sequential circuit. By replacing flip-flops with latches in proposed shift register, the
power is saved by using clock pulsed instead of clock signal. Because of all these
reasons, static differential sense amplifier shared pulsed latch is an attractive choice for
efficient design of shift register.

8
 CHAPTER – 2

LITERATURE SURVEY

2.1 LITERATURE SURVEY

At present, by decreasing the CMOS technology process feature size based on

Moore’s law, more transistors can be integrated onto the same die [1- 2]. Applying more
transistors is accompanied with more switching which brings about more energy
dissipation in the form of heat and radiation [3]. As the packaging and cooling are not
able to remove the additional heat, the matter of heat is one of the significant issues in this
era [4]. The heat and the consistency of the integrated circuit are addressed as important
drivers of low power design procedures especially in RFID based applications [5-9].
Moreover, reaching to the mobile society can be reported as another important objective
of low power design [10-11].

As it goes further, it is expected that more low power systems being reported. This
expectancy requires an appropriate development in low power procedures and tools [12].
The procedure that is currently developing will guide us to the low power design
automation in integrated chips are flip-flop (FF) based designs [13]. FFs are addressed as
the fundamental storage elements that are applied vastly in whole types of digital designs
[14-16]. Majority of the digital designs are currently implemented by using FF-rich
modulus. One of the major design using FFs are shift registers [17]. In shift registers, the
power consumption of system clock is estimated to be half of the overall system power
[18]. Therefore, the FFs contribute a substantial percentage of the chip area and power
consumption in compare with whole system design [19-20].

In the last decades, radio frequency identification (RFID) technology has turned
out to be a discipline of predominant attention for wireless communication system. RFID
technology integrates portable wireless devices in order to detect both the nature and the
precise location of physical objects or persons [1,2]. The RIFD reader contributes to
transmitting the information and energy into the RFID tag where the tag is responsible for
providing feedback to the RFID reader for any kind of inquiry [3]. The fundamental
concern of this system is to protect the data privacy of the consumer. With the
advancement of modern technology, personal data privacy faces different kinds of threat.
The privacy of a consumer can be stolen or scanned without approval or even learning.

9
 The medical information of patients can be revealed and anybody can be a victim
of clandestine tracking by vendors [4,5]. In response to these issues, a lot of research has
been done aimed at the prevention of unauthorized access to RFID tags. To improve the
security system in active RFID tags most of them use a shift register for storing a key or
data [6,7]. The shift register is integrated into a modulator/demodulator in cryptographic
RFID tag. Figures 1 and 2 describe the integration of a shift register in a cryptographic
RFID tag precisely. The shift register is used in a modulator/demodulator to shift one bit
at the rising edge of the clock in one shift action. The four-bit shift register loads data in it
through the four-bit parallel input, and shifts it out through the serial output. Therefore,
designing an efficient shift register has become a more demanding goal in current RFID
security system.

The low-power and area-efficient shift register using pulsed latches is suggested,
the area and power consumption are compact by exchanging flip-flops with pulsed
latches. This technique solves the control problem between pulsed latches through the use
of various non-overlap delayed pulsed clock indicators in its place of the predictable
single pulsed clock signal.[1]This paper presents new techniques to assess the energy and
delay of flip-flop and latch plans and shows that no single present design makes well
across the wide range of operating rules present in complex systems we reduce total flip-
flop and latch energy by over 60% without increasing cycle time[4]] VLSI technology has
been growing to the large extent.

All credit for this goes to the increasing usage of integrated circuits for every
embedded system, mobile technologies, increasing systems, etc. Increasing growth and
use of knowledge has increased the thirst for low energy or power consumption [2].The
condition has changed and now developing of different circuit methods for low power
circuit design is an important research area. This situation has changed and now
developing of different circuit techniques for low power circuit design is an important
research area [5]

10
2.2 Sequential Logic Circuits:

Fig 2.1: Basic Sequential Design

This means that sequential logic circuits are able to take into account their
previous input state as well as those actually present, a sort of “before” and “after” effect
is involved with sequential circuits. In other words, the output state of a “sequential logic
circuit” is a function of the following three states, the “present input”, the “past input”
and/or the “past output”. Sequential Logic circuits remember these conditions and stay
fixed in their current state until the next clock signal changes one of the states, giving
sequential logic circuits “Memory”. Sequential logic circuits are generally termed as two
state or Bistable devices which can have their output or outputs set in one of two basic
states, a logic level “1” or a logic level “0” and will remain “latched” (hence the name
latch) indefinitely in this current state or condition until some other input trigger pulse or
signal is applied which will cause the bistable to change its state once again.

The word “Sequential” means that things happen in a “sequence”, one after
another and in Sequential Logic circuits, the actual clock signal determines when things
will happen next. Simple sequential logic circuits can be constructed from standard
Bistable circuits such as: Flip-flops, Latches and Counters and which themselves can be
made by simply connecting together universal NAND Gates and/or NOR Gates in a
particular combinational way to produce the required sequential circuit.

2.3 Classification of Sequential Logic:

As standard logic gates are the building blocks of combinational circuits, bistable
latches and flip-flops are the basic building blocks of sequential logic circuits. Sequential
logic circuits can be constructed to produce either simple edge-triggered flip-flops or
more complex sequential circuits such as storage registers, shift registers, memory

11
devices or counters. Either way sequential logic circuits can be divided into the following
three main categories:

 1. Event Driven – asynchronous circuits that change state immediately when

enabled.

 2. Clock Driven – synchronous circuits that are synchronised to a specific clock

signal.

 3. Pulse Driven – which is a combination of the two that responds to triggering

pulses.

Fig 2.2: Sequential operation

As well as the two logic states mentioned above logic level “1” and logic level
“0”, a third element is introduced that separates sequential logic circuits from
their combinational logic counterparts, namely TIME. Sequential logic circuits return
back to their original steady state once reset and sequential circuits with loops or feedback
paths are said to be “cyclic” in nature.

We now know that in sequential circuits changes occur only on the application of
a clock signal making it synchronous, otherwise the circuit is asynchronous and depends
upon an external input. To retain their current state, sequential circuits rely on feedback
and this occurs when a fraction of the output is fed back to the input and this is
demonstrated as:

12
2.4 Sequential Feedback Loop

Fig 2.3: Storing mechanism.

The two inverters or NOT gates are connected in series with the output at Q fed
back to the input. Unfortunately, this configuration never changes state because the output
will always be the same, either a “1” or a “0”, it is permanently set. However, we can see
how feedback works by examining the most basic sequential logic components, called
the SR flip-flop.

2.5 SR Flip-Flop

The SR flip-flop, also known as a SR Latch, can be considered as one of the most
basic sequential logic circuit possible. This simple flip-flop is basically a one-bit memory
bistable device that has two inputs, one which will “SET” the device (meaning the output
= “1”), and is labelled S and another which will “RESET” the device (meaning the output
= “0”), labelled R.

Then the SR description stands for “Set-Reset”. The reset input resets the flip-flop
back to its original state with an output Q that will be either at a logic level “1” or logic
“0” depending upon this set/reset condition. A basic NAND gate SR flip-flop circuit
provides feedback from both of its outputs back to its opposing inputs and is commonly
used in memory circuits to store a single data bit. Then the SR flip-flop actually has three
inputs, Set, Reset and its current output Qrelating to it’s current state or history. The term
“Flip-flop” relates to the actual operation of the device, as it can be “flipped” into one
logic Set state or “flopped” back into the opposing logic Reset state.

2.6 The NAND Gate SR Flip-Flop

The simplest way to make any basic single bit set-reset SR flip-flop is to connect
together a pair of cross-coupled 2-input NAND gates as shown, to form a Set-Reset
Bistable also known as an active LOW SR NAND Gate Latch, so that there is feedback
from each output to one of the other NAND gate inputs. This device consists of two

13
inputs, one called the Set, S and the other called the Reset, R with two corresponding
outputs Q and its inverse or complement Q (not-Q) as shown below.

2.7 The Basic SR Flip-flop

Fig 2.4: SR Flip-flops

The Set State: Consider the circuit shown above. If the input R is at logic level “0” (R =
0) and input S is at logic level “1” (S = 1), the NAND gate Y has at least one of its inputs
at logic “0” therefore, its output Q must be at a logic level “1” (NAND Gate principles).
Output Q is also fed back to input “A” and so both inputs to NAND gate X are at logic
level “1”, and therefore its output Q must be at logic level “0”.

Again NAND gate principals. If the reset input R changes state, and goes HIGH to
logic “1” with S remaining HIGH also at logic level “1”, NAND gate Y inputs are
now R = “1” and B = “0”. Since one of its inputs is still at logic level “0” the output
at Q still remains HIGH at logic level “1” and there is no change of state. Therefore, the
flip-flop circuit is said to be “Latched” or “Set” with Q = “1” and Q = “0”.

Reset State: In this second stable state, Q is at logic level “0”, (not Q = “0”) its inverse
output at Q is at logic level “1”, (Q = “1”), and is given by R = “1” and S = “0”. As
gate X has one of its inputs at logic “0” its output Q must equal logic level “1” (again
NAND gate principles). Output Q is fed back to input “B”, so both inputs
to NAND gate Y are at logic “1”, therefore, Q = “0”.

If the set input, S now changes state to logic “1” with input R remaining at logic
“1”, output Q still remains LOW at logic level “0” and there is no change of state.
Therefore, the flip-flop circuits “Reset” state has also been latched and we can define this
“set/reset” action in the following truth table.

14
Table 2.1 Truth Table for this Set-Reset Function

State S R Q Q Description

1 0 0 1 Set Q » 1
Set
1 1 0 1 no change

0 1 1 0 Reset Q » 0
Reset
1 1 1 0 no change

Invalid 0 0 1 1 Invalid Condition

It can be seen that when both inputs S = “1” and R = “1” the outputs Q and Q can be at
either logic level “1” or “0”, depending upon the state of the inputs S or R BEFORE this
input condition existed. Therefore the condition of S = R = “1” does not change the state
of the outputs Q and Q.

However, the input state of S = “0” and R = “0” is an undesirable or invalid

condition and must be avoided. The condition of S = R = “0” causes both
outputs Q and Q to be HIGH together at logic level “1” when we would normally
want Q to be the inverse of Q. The result is that the flip-flop looses control of Q and Q,
and if the two inputs are now switched “HIGH” again after this condition to logic “1”, the
flip-flop becomes unstable and switches to an unknown data state based upon the
unbalance as shown in the following switching diagram.

2.8 S-R Flip-flop Switching Diagram

15
This unbalance can cause one of the outputs to switch faster than the other resulting in the
flip-flop switching to one state or the other which may not be the required state and data
corruption will exist. This unstable condition is generally known as its Meta-stable state.

Then, a simple NAND gate SR flip-flop or NAND gate SR latch can be set by
applying a logic “0”, (LOW) condition to its Set input and reset again by then applying a
logic “0” to its Reset input. The SR flip-flop is said to be in an “invalid” condition (Meta-
stable) if both the set and reset inputs are activated simultaneously.

As we have seen above, the basic NAND gate SR flip-flop requires logic “0”
inputs to flip or change state from Q to Q and vice versa. We can however, change this
basic flip-flop circuit to one that changes state by the application of positive going input
signals with the addition of two extra NAND gates connected as inverters to
the S and R inputs as shown.

2.9 Positive NAND Gate SR Flip-flop

Fig 2.5: NAND based latch

As well as using NAND gates, it is also possible to construct simple one-bit SR

Flip-flops using two cross-coupled NOR gates connected in the same configuration. The
circuit will work in a similar way to the NAND gate circuit above, except that the inputs
are active HIGH and the invalid condition exists when both its inputs are at logic level
“1”, and this is shown below.

16
2.10 The NOR Gate SR Flip-flop

Fig 2.6: NOR based latch

Switch Debounce Circuits
Edge-triggered flip-flops require a nice clean signal transition, and one practical
use of this type of set-reset circuit is as a latch used to help eliminate mechanical switch
“bounce”. As its name implies, switch bounce occurs when the contacts of any
mechanically operated switch, push-button or keypad are operated and the internal switch
contacts do not fully close cleanly, but bounce together first before closing (or opening)
when the switch is pressed.
This gives rise to a series of individual pulses which can be as long as tens of
milliseconds that an electronic system or circuit such as a digital counter may see as a
series of logic pulses instead of one long single pulse and behave incorrectly. For
example, during this bounce period the output voltage can fluctuate wildly and may
register multiple input counts instead of one single count. Then set-reset SR Flip-flops or
Bistable Latch circuits can be used to eliminate this kind of problem and this is
demonstrated below.

2.11 SR Flip Flop Switch Debounce Circuit

\
Fig 2.7: Timing diagram

17
 Depending upon the current state of the output, if the set or reset buttons are
depressed the output will change over in the manner described above and any additional
unwanted inputs (bounces) from the mechanical action of the switch will have no effect
on the output at Q.

When the other button is pressed, the very first contact will cause the latch to
change state, but any additional mechanical switch bounces will also have no effect. The
SR flip-flop can then be RESET automatically after a short period of time, for example
0.5 seconds, so as to register any additional and intentional repeat inputs from the same
switch contacts, such as multiple inputs from a keyboards “RETURN” key.

Commonly available IC’s specifically made to overcome the problem of switch

bounce are the MAX6816, single input, MAX6817, dual input and the MAX6818 octal
input switch debouncer IC’s. These chips contain the necessary flip-flop circuitry to
provide clean interfacing of mechanical switches to digital systems.

Set-Reset bistable latches can also be used as Monostable (one-shot) pulse generators to
generate a single output pulse, either high or low, of some specified width or time period
for timing or control purposes. The 74LS279 is a Quad SR Bistable Latch IC, which
contains four individual NAND type bistable’s within a single chip enabling switch
debounce or monostable/astable clock circuits to be easily constructed.

2.12 Quad SR Bistable Latch 74LS279

Fig 2.8: DUAL gate IC

18
2.13 Gated or Clocked SR Flip-Flop

It is sometimes desirable in sequential logic circuits to have a bistable SR flip-flop

that only changes state when certain conditions are met regardless of the condition of
either the Set or the Reset inputs. By connecting a 2-input AND gate in series with each
input terminal of the SR Flip-flop a Gated SR Flip-flop can be created. This extra
conditional input is called an “Enable” input and is given the prefix of “EN“. The addition
of this input means that the output at Q only changes state when it is HIGH and can
therefore be used as a clock (CLK) input making it level-sensitive as shown below.

Gated SR Flip-flop

Fig 2.9: SR clocked latch

When the Enable input “EN” is at logic level “0”, the outputs of the
two AND gates are also at logic level “0”, (AND Gate principles) regardless of the
condition of the two inputs S and R, latching the two outputs Q and Q into their last
known state. When the enable input “EN” changes to logic level “1” the circuit responds
as a normal SR bistable flip-flop with the two AND gates becoming transparent to the Set
and Reset signals.

This additional enable input can also be connected to a clock timing signal (CLK)
adding clock synchronisation to the flip-flop creating what is sometimes called a
“Clocked SR Flip-flop“. So a Gated Bistable SR Flip-flop operates as a standard
bistable latch but the outputs are only activated when a logic “1” is applied to its EN input
and deactivated by a logic “0”.

2.14 SHIFT REGISTER:

The Shift Register is another type of sequential logic circuit that can be used for
the storage or the transfer of data in the form of binary numbers.

19
This sequential device loads the data present on its inputs and then moves or “shifts” it to
its output once every clock cycle, hence the name Shift Register.

A shift register basically consists of several single bit “D-Type Data Latches”, one
for each data bit, either a logic “0” or a “1”, connected together in a serial type daisy-
chain arrangement so that the output from one data latch becomes the input of the next
latch and so on.

Data bits may be fed in or out of a shift register serially, that is one after the other
from either the left or the right direction, or all together at the same time in a parallel
configuration.

The number of individual data latches required to make up a single Shift

Register device is usually determined by the number of bits to be stored with the most
common being 8-bits (one byte) wide constructed from eight individual data latches. Shift
Registers are used for data storage or for the movement of data and are therefore
commonly used inside calculators or computers to store data such as two binary numbers
before they are added together, or to convert the data from either a serial to parallel or
parallel to serial format. The individual data latches that make up a single shift register
are all driven by a common clock ( Clk ) signal making them synchronous devices. Shift
register IC’s are generally provided with a clear or reset connection so that they can be
“SET” or “RESET” as required. Generally, shift registers operate in one of four different
modes with the basic movement of data through a shift register being:

 Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at
a time, with the stored data being available at the output in parallel form.

 Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of the
register, one bit at a time in either a left or right direction under clock control.

 Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under
clock control.

 Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into

the register, and transferred together to their respective outputs by the same clock
pulse.

20
The effect of data movement from left to right through a shift register can be presented
graphically as:

Fig 2.10: Shift register

Also, the directional movement of the data through a shift register can be either to
the left, (left shifting) to the right, (right shifting) left-in but right-out, (rotation) or both
left and right shifting within the same register thereby making it bidirectional. In this
tutorial it is assumed that all the data shifts to the right, (right shifting).

2.15 Serial-in to Parallel-out (SIPO) Shift Register

4-bit Serial-in to Parallel-out Shift Register

Fig 2.11: Ring counter

The operation is as follows. Lets assume that all the flip-flops ( FFA to FFD )
have just been RESET ( CLEAR input ) and that all the outputs QA to QD are at logic
level “0” ie, no parallel data output. If a logic “1” is connected to the DATA input pin

21
of FFA then on the first clock pulse the output of FFA and therefore the resulting QA will
be set HIGH to logic “1” with all the other outputs still remaining LOW at logic “0”.
Assume now that the DATA input pin of FFA has returned LOW again to logic “0”
giving us one data pulse or 0-1-0. The second clock pulse will change the output
of FFA to logic “0” and the output of FFBand QB HIGH to logic “1” as its input D has the
logic “1” level on it from QA. The logic “1” has now moved or been “shifted” one place
along the register to the right as it is now at QA.

When the third clock pulse arrives this logic “1” value moves to the output
of FFC ( QC ) and so on until the arrival of the fifth clock pulse which sets all the
outputs QA to QDback again to logic level “0” because the input to FFA has remained
constant at logic level “0” The effect of each clock pulse is to shift the data contents of
each stage one place to the right, and this is shown in the following table until the
complete data value of 0-0-0-1is stored in the register. This data value can now be read
directly from the outputs of QAto QD. Then the data has been converted from a serial data
input signal to a parallel data output. The truth table and following waveforms show the
propagation of the logic “1” through the register from left to right as follows.

Table 2.2 Basic Data Movement Through A Shift Register

Clock Pulse No QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 0 0 0 0

22
 Note that after the fourth clock pulse has ended the 4-bits of data ( 0-0-0-1 ) are
stored in the register and will remain there provided clocking of the register has stopped.
In practice the input data to the register may consist of various combinations of logic “1”
and “0”. Commonly available SIPO IC’s include the standard 8-bit 74LS164 or the
74LS594.

2.16 Serial-in to Serial-out (SISO) Shift Register

This shift register is very similar to the SIPO above, except were before the data was
read directly in a parallel form from the outputs QA to QD, this time the data is allowed to
flow straight through the register and out of the other end. Since there is only one output,
the DATA leaves the shift register one bit at a time in a serial pattern, hence the
name Serial-in to Serial-Out Shift Register or SISO.

The SISO shift register is one of the simplest of the four configurations as it has
only three connections, the serial input (SI) which determines what enters the left hand
flip-flop, the serial output (SO) which is taken from the output of the right hand flip-flop
and the sequencing clock signal (Clk). The logic circuit diagram below shows a
generalized serial-in serial-out shift register.

4-bit Serial-in to Serial-out Shift Register

Fig 2.12: 4 bit register

23
 You may think what’s the point of a SISO shift register if the output data is
exactly the same as the input data. Well this type of Shift Register also acts as a
temporary storage device or it can act as a time delay device for the data, with the amount
of time delay being controlled by the number of stages in the register, 4, 8, 16 etc or by
varying the application of the clock pulses. Commonly available IC’s include the
74HC595 8-bit Serial-in to Serial-out Shift Register all with 3-state outputs.

2.17 Parallel-in to Serial-out (PISO) Shift Register

The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in
to parallel-out one above. The data is loaded into the register in a parallel format in which
all the data bits enter their inputs simultaneously, to the parallel input pins PA to PD of the
register. The data is then read out sequentially in the normal shift-right mode from the
register at Q representing the data present at PA to PD.

This data is outputted one bit at a time on each clock cycle in a serial format. It is
important to note that with this type of data register a clock pulse is not required to
parallel load the register as it is already present, but four clock pulses are required to
unload the data.

4-bit Parallel-in to Serial-out Shift Register

Fig 2.13: Parallel register

As this type of shift register converts parallel data, such as an 8-bit data word into
serial format, it can be used to multiplex many different input lines into a single serial
DATA stream which can be sent directly to a computer or transmitted over a
communications line. Commonly available IC’s include the 74HC166 8-bit Parallel-
in/Serial-out Shift Registers.

24
Parallel-in to Parallel-out (PIPO) Shift Register

The final mode of operation is the Parallel-in to Parallel-out Shift Register. This
type of shift register also acts as a temporary storage device or as a time delay device
similar to the SISO configuration above. The data is presented in a parallel format to the
parallel input pins PA to PD and then transferred together directly to their respective output
pins QA to QA by the same clock pulse. Then one clock pulse loads and unloads the
register. This arrangement for parallel loading and unloading is shown below.

4-bit Parallel-in to Parallel-out Shift Register

Fig 2.14: parallel data register

The PIPO shift register is the simplest of the four configurations as it has only
three connections, the parallel input (PI) which determines what enters the flip-flop, the
parallel output (PO) and the sequencing clock signal (Clk). Similar to the Serial-in to
Serial-out shift register, this type of register also acts as a temporary storage device or as a
time delay device, with the amount of time delay being varied by the frequency of the
clock pulses. Also, in this type of register there are no interconnections between the
individual flip-flops since no serial shifting of the data is required.

2.18 Effect of PVT variations on pulsed latches:

The operation of PLs is based on enabling the latch for a short time using a pulse
generated by the pulser circuit. Hence, to study the effect of variation on PL operation,
variation effects on both the latch write time and the pulser pulse width should be studied.
The effect of process variations is carried out for each of the latch and the pulser

25
independently and the same study is repeated for different voltage and temperature values
of interest. A. Process Variations Due to the extreme miniaturization of device parameters
in current and upcoming technology processes, even a small variation in the
manufacturing process may cause parameter variations that can lead to a failed circuit
operation [20]. Thus, one of the significant challenges in the design phase is the ability to
evaluate the effect of different sources of variations on the functionality of complex
circuits and to provide circuit solutions to guarantee correct functionality under different
sources of variations.

Process dependent sources of variability such as effective length variation, oxide

thickness variation, Line Edge Roughness (LER), and Random Dopant Fluctuation (RDF)
(for planar MOSFETs) result in variations in the value of the threshold voltages of
transistors, which in turn impact the timing and power of digital circuits [21]. The
threshold voltage variations due to RDF (which is usually the principal source of
threshold voltage variations in planar MOSFETs) are considered as zero-mean Gaussian
independent random variables with standard deviation denoted as σV th where Na is the
effective channel doping, Wd is the depletion region width, Tox is the oxide thickness,
Lmin and Wmin are the minimum channel length and width, respectively. While the
scaling down of CMOS technology reduces the nominal supply voltage, the threshold
voltages are not scaled by the same factor, leading to a significant reduction of the
transistor’s available voltage headroom (the difference between the supply voltage and
the threshold voltage).

Hence, even any small variation in the transistor threshold voltage can lead to a
significant degradation of the circuit behavior or can even cause complete circuit failure.
Studying the effect of process variations on PLs includes studying the effect of variations
on both the latch write time and the pulser pulse width. As shown in Fig. 2, this is
represented by the probability distribution functions (PDFs) of both the write time (Latch
WR Time) calculated as the CLK-to-Q delay and the pulse width (Pulser PW). To ensure
correct write operation, the pulse width should be larger than the required transparent
window for the latch (i.e. time needed to capture the input data and pass it through the
internal nodes to the storing cross coupled inverters).

The area under the intersection between the two PDFs represents the failure of
write operation, since this is the region where there is a high probability that the pulse
width will be smaller than the time needed by the latch. Alternatively, knowing the

26
information about the distribution of the latch write time and for easiness of timing
analysis, a maximum value for latch write time can be calculated for certain sigma value
of the designer choice. In this case, the probability of write failure can be calculated as the
probability of having the width of the pulser output smaller than this desired maximum
value. In both cases, depending on the target yield, the designer can determine the
minimum acceptable value for circuit failure, and hence, the transistors’ dimension can be
adjusted to reach the target yield.

Voltage Scaling

Voltage scaling is a popular run-time technique used for reducing the power
consumption of circuits. It significantly decreases both dynamic power (with its two
components of switching power and internal power) and leakage power. On the other
hand, the ability to reduce the operating supply voltage is limited by a minimum value
determined usually by some timing constrains (critical path delay as an example), in
addition to some margins for the PVT variations, and usually adding a margin for aging
effects [22]. As the supply voltage is scaled down, the available voltage headroom
decreases further and the transistors become more sensitive to any variations. The effect
of voltage scaling is naturally associated with the increase of timing delays for different
circuit components.

While this can be handled at design time for several circuit components, the case
may not be as easy for PLs. Since PL operation depends on two different components
(pulser and latches) of different micro-architectures, the timing of each of them is affected
differently. As shown in Fig. 3, voltage scaling affects the probability distribution of the
pulser and the latch differently. Hence, failure probability calculated at one voltage will
not be the same when applying voltage scaling. Indeed, PL reliability degrades
significantly when scaling down the supply voltage. As shown in Fig. 4, the probability of
write failure for a PL can increase by up to two order of magnitude when the supply
voltage is scaled down by around 30%.

Even if the PL circuit is designed to operate reliably at an intermediate supply

voltage (0.9V as an example), the reliability will still significantly degrade at lower
voltages, especially at low operating temperatures. One possible solution is to design the
PL circuit to operate with the needed level of reliability at the lowest possible operating
voltage. Since chips usually operate at different supply voltages with different operating

27
 modes, when pulsed latches are operating at a voltage higher than that minimum value,
they will be operating with extra timing margin (the pulse width will be larger than the
needed width to achieve the required level of reliability). Hence, this will negatively
affect one of the main advantage of PLs which is their low timing overhead, in addition to
increasing the risk of hold time violations. The proposed circuit approaches in this paper
will help in forcing PLs to reliably operate with just the needed timing margins at
different supply voltages. Hence, this will assure gaining the maximum benefits of pulsed
latches at different operating modes without any unnecessary waste in the design
performance.
Studying the effect of temperature variation on the design is very important. Not only does the
variation in temperature affect leakage power and performance, but it also affects the probability
of having an error during circuit operation, as well as impacting the life span of different chip
parts. Factors such as the increase of leakage power with technology process scaling, the
nonequivalent down scaling of the supply voltage when compared to geometry scaling, and the
increase in the dynamic power associated with the increase in performance
Required in current designs, all lead to the increase of the operating temperature. Careful study
of the effect of temperature is required especially for time-sensitive sequential elements.

Temperature Effect

The study of temperature effects on pulsed latches is much more critical, since each of the pulser
and the latches can have a different response to temperature variation. The study done in this
paper shows that both circuits become more sensitive to process variation with the decrease in
temperature.
However, the pulser is more significantly affected by temperature variations. In addition, the
entire PL would have high failure rates when operating at a lower temperature. When running at
nominal supply voltage, the transistors become faster as the temperature decreases. Since the
pulser is more timing sensitive than the latch, the timing margin between the latch write time and
the pulser output pulse width will decrease with the decrease in temperature hence, the
probability of write failure is expected to increase with the decrease of temperature.
The standard deviation for the latch distribution is doubled with the temperature decrease from
125◦C to −40◦C, while the standard deviation for the pulser distribution increases by more than
60%. This significant increase in the variation of the latch and pulser timing with the decrease in
temperature leads to the increase of the probability of write failure.
 Fig. 5. A diagram showing arbitrary PDFs for the pulser and the latch when (a) operating
at nominal supply voltage, (b) scaling down the supply voltage without configuring the pulser (or
having a fixed pulser), and (c) scaling down the supply voltage and configuring the pulser circuit
to generate a wider output pulse.

28
 CHAPTER – 3
PROPOSED TECHNIQUE

3.1 PROPOSED TECHNIQUE

The basic structure of a conventional pulser of the TGPL is shown in Fig., where
the delay unit, usually consisting of an even number of inverters, is responsible for
determining the width of the needed output pulse. To guarantee correct operation, the
pulser is designed to generate a pulse width that is larger than the latch write time.

Fig 3.1: The basic construction of a simple pulser.

As described in the previous section, it is not easy to design a non-configurable pulsed

latch circuit that can operate with just the needed timing margins at different supply
voltages in the presence of process and temperature variations, while keeping the needed
level of reliability. To be able to reach the needed reliability level, the pulser circuit
should be reconfigured at run time to generate an output pulse whose width can be
controlled based on the operating condition. Shown in Fig. 8(a) is a pulsed latch circuit
designed to operate correctly at nominal supply voltage with high level of reliability.

However, when scaling down the supply voltage as shown in Fig. 8(b), the circuit
become less reliable with higher probability of failure. The required level of reliability
can be achieved at the lower supply voltage by increasing the width of the generated
pulse. As shown in Fig. 8(c), this is equivalent to shifting the pulser probability
distribution to the right, compensating for the increased variation effects at lower voltages
and therefore, decreasing the probability of circuit failure. In this section, two design
approaches are proposed. Both approaches depend on controlling the delay path (the
delay unit and its following inverter) of the pulser circuit by using an external control
signal (CTRL) to generate a controllable pulsewidth.

29
 Fig. 3.2: The proposed header switches-based pulser design.

The first approach considers splitting the supply rail of the pulser circuit, and
applying an additional controllable level of voltage scaling on the delay path when
needed. The second approach relies on using multiple delay units in the pulser circuit and
choosing a certain delay unit at run-time according to the operating condition. Detailed
discussions of the two approaches are presented in the next two subsections. First
Approach This approach is based on using a virtual supply rail for the delay path of the
pulser, driven from the main supply rail used for the rest of the pulser circuit and the
latches. This can be accomplished using header PMOS switches for the delay path of the
pulser circuit, similar to the local power gating topology, where turning off some of these
switches will result in lowering the supply voltage of the delay path.

Since this delay path is the main part of the circuit that control the width of the
generated pulse, controlling the supply voltage of this path will result in controlling the
output pulse width. Separate control signals can be used for different switches, where at
least one of these switches must be always turned on (i.e, the gate of this PMOS switch
should be tied to the ground) giving the maximum output pulse width, while the other
switches can be turned on or off to achieve the required narrowing of the pulse width. The
number of these parallel switches and their sizes will depend on the number and values of
the virtual supply voltage levels, which corresponds to the needed pulse widths to achieve
the target reliability level at different operating conditions. Since the delay chain current
represents only 20-30% of the total pulser current, the sizes of these PMOS switches
should be reasonable, adding a small area overhead to the pulser circuit. During normal

30
 operation, when required to operate at the nominal supply voltage, all header switches are
on, driving the whole pulser circuit by nearly the same supply voltage value. When
scaling down the supply voltage, the needed margin for variations in the latch write time
increases. By turning off part of the pulser header switches, an additional down scaling of
the virtual supply of the delay path (VDI) is provided; i.e., the delay unit and its following
inverter is running at a slightly lower supply than the rest of the pulser circuit.

Fig. 3.3: The proposed MUX-based pulser design.

This additional voltage scaling of VDI will result in a small increase in the pulseroutput pulse
width. Since the circuit is already operating with small voltage headroom at this lower supply
voltage, a very small decrease in VDI will be sufficient to produce an adequate increase in the
pulse width without having a significant difference between the supply voltages of the delay
path and the rest of the pulser circuit. In addition, the remaining pulser circuit (the NAND
gate and the output inverter) will act as a voltage level shifter, driving the latches by the same
voltage level as their supply voltage.

As described in the previous section, it is not easy to design a non-configurable pulsed latch
circuit that can operate with just the needed timing margins at different supply voltages in the
presence of process and temperature variations, while keeping the needed level of reliability. To
be able to reach the needed reliability level, the pulser circuit should be reconfigured at run time
to generate an output pulse whose width can be controlled based on the operating condition.
Shown in Fig. 5(a) is a pulsed latch circuit designed to operate correctly at nominal supply
voltage with high level of reliability. However, when scaling down the supply voltage as shown
in Fig. 5(b), the circuit become less reliable with higher probability of failure. The required level
of reliability can be achieved at the lower supply voltage by increasing the width of the
generated pulse. As shown in Fig. 5(c), this is equivalent to shifting the pulser probability
distribution to the right, compensating for the increased variation effects at lower voltages and
therefore, decreasing the probability of circuit failure. In this section, two design approaches are
proposed. Both approaches depend on controlling the delay path (the delay unit and its following
inverter) of the pulser circuit by using an external control signal (CTRL) to generate a
controllable pulse width. The first approach considers splitting the supply rail of the pulser
circuit, and applying an additional controllable level of voltage scaling on the delay path when
needed. The second approach relies on using multiple delay units in the pulser circuit and
choosing a certain delay unit at run-time according to the operating condition. Detailed
discussions of the two approaches are presented in the next two subsections.

Second Approach

Since the pulse width depends on the delay unit, implementing multiple delayunits with
different delays can help in generating pulses with different widths. One important design
consideration is the ability to choose between these different units post silicon or at run-time.
The second proposed pulser design is shown in Fig. 10. Each delay unit represents a buffer
chain that can be implemented in different ways. It can be as simple as a very small delay
unit (i.e., just a wire) and up to multiple even number of inverters of different inverter sizes
and/or numbers. The output of the multiplexer is used to drive an odd number of inverters,
whose final output is connected to the NAND gate.

By selecting a longer delay chain, the latch transparency window can be increased at run time,
which is required when scaling down the supply voltage. The shortest delay unit is designed
such that, when operating at a nominal supply voltage, the circuit is verified to run with very
low probability of failure in the presence of different process and temperature
variations. The rest of the delay units are designed depending on the number and values of the
supply voltage scaling levels. Implementing multiple delay units with different delays can help
in generating pulses with different widths. One important design consideration is the ability to
choose between these different units post silicon or at run-time. The second proposed pulser
design is shown in Fig. 7. Each delay unit represents a buffer chain that can be implemented in
different ways. It can be as simple as a very small delay unit (i.e., just a wire) and up to multiple
even number of inverters of different inverter sizes and/or numbers. The output of the
multiplexer is used to drive an odd number of inverters, whose final output is connected to the
NAND gate.
 31

By selecting a longer delay chain, the latch transparency window can be increased at run time,
which is required when scaling down the supply voltage. The shortest delay unit is designed such
that, when operating at a nominal supply voltage, the circuit is verified to run with very low
probability of failure in the presence of different process and temperature variations. The rest of
the delay units are designed depending on the number and values of the supply voltage scaling
levels.
32
 CHAPTER – 4
EXISTING TECHNIQUE:

4.1 EXISTING TECHNIQUE

4.1.1 Clock gating based reconfigurable pulsed latches:

Clock gating is a popular technique used in many synchronous circuits for reducing
dynamic power dissipation. Clock gating saves power by adding more logic to a circuit to
prune the clock tree. Pruning the clock disables portions of the circuitry so that the flip-
flops in them do not have to switch states. Switching states consumes power. When not
being switched, the switching power consumption goes to zero, and only leakage
currents are incurred. Clock gating works by taking the enable conditions attached to
registers, and uses them to gate the clocks. A design must contain these enable conditions
in order to use and benefit from clock gating. This clock gating process can also save
significant die area as well as power, since it removes large numbers of muxes and
replaces them with clock gating logic. This clock gating logic is generally in the form of
"Integrated clock gating" (ICG) cells. However, note that the clock gating logic will
change the clock tree structure, since the clock gating logic will sit in the clock tree.

Clock gating logic can be added into a design in a variety of ways:

1. Coded into the RTL code as enable conditions that can be automatically translated
into clock gating logic by synthesis tools (fine grain clock gating).

2. Inserted into the design manually by the RTL designers (typically as module level
clock gating) by instantiating library specific ICG (Integrated Clock Gating) cells
to gate the clocks of specific modules or registers.

3. Semi-automatically inserted into the RTL by automated clock gating tools. These
tools either insert ICG cells into the RTL, or add enable conditions into the RTL
code. These typically also offer sequential clock gating optimisations.

Note: Any RTL modifications to improve clock gating will result in functional changes to
the design (since the registers will now hold different values) which need to be verified.

Sequential clock gating is the process of extracting/propagating the enable conditions to

the upstream/downstream sequential elements, so that additional registers can be clock
gated.

33
Although asynchronous circuits by definition do not have a "clock", the term perfect
clock gating is used to illustrate how various clock gating techniques are simply
approximations of the data-dependent behavior exhibited by asynchronous circuitry.

As the granularity on which you gate the clock of a synchronous circuit

approaches zero, the power consumption of that circuit approaches that of an
asynchronous circuit: the circuit only generates logic transitions when it is actively
computing.[2]Chip families such as OMAP3, with a cell phone heritage, support several
forms of clock gating. At one end is the manual gating of clocks by software, where a
driver enables or disables the various clocks used by a given idle controller. On the other
end is automatic clock gating, where the hardware can be told to detect whether there's
any work to do, and turn off a given clock if it is not needed. These forms interact with
each other and may be part of the same enable tree. For example, an internal bridge or bus
might use automatic gating so that it is gated off until the CPU or a DMA engine needs to
use it, while several of the peripherals on that bus might be permanently gated off if they
are unused on that board.

With the decrease of feature sizes and increase of clock frequencies in integrated
digital circuits, power consumption has become a major concern for modern integrated
circuit designs. Power dissipation has a dynamic component, due to the switching of
active devices, and a static component, due to the leakage of inactive devices. Since our
work targets dynamic power only, further references to “power” in this we will imply the
dynamic power. Clock gating is one of the most effective and widely used techniques for
saving clock power. The clock net is one of the nets with the highest switching density,
resulting in high power dissipation in the adders. A promising technique to reduce the
power dissipation of the clock net is selectively stopping the clock in parts of the circuit,
called “clock gating”. It is very well integrated into semi-custom design flows nowadays.
By gating the clock, the switching activity of the adders clock signal is reduced. However,
clock gating circuitry itself occupies chip area and consumes additional power; therefore
a judicious selection of circuit

34
4. 2 VLSI DESIGN - MOS TRANSISTOR:

Complementary MOSFET (CMOS) technology is widely used today to form

circuits in numerous and varied applications. Today’s computers, CPUs and cell phones
make use of CMOS due to several key advantages. CMOS offers low power dissipation,
relatively high speed, high noise margins in both states, and will operate over a wide
range of source and input voltages (provided the source voltage is fixed)

For the processes we will discuss, the type of transistor available is the Metal-
Oxide-Semiconductor Field Effect Transistor (MOSFET). These transistors are
formed as a ‘sandwich’ consisting of a semiconductor layer, usually a slice, or wafer,
from a single crystal of silicon; a layer of silicon dioxide (the oxide) and a layer of metal.

Structure of a MOSFET

Fig. 4.1: MOS structure contains three layers

As shown in the figure, −

 The Metal Gate Electrode

 The Insulating Oxide Layer (SiO2)

 P – type Semiconductor (Substrate)

MOS structure forms a capacitor, with gate and substrate are as two plates and
oxide layer as the dielectric material. The thickness of dielectric material (SiO2) is
usually between 10 nm and 50 nm. Carrier concentration and distribution within the
substrate can be manipulated by external voltage applied to gate and substrate terminal.

35
Now, to understand the structure of MOS, first consider the basic electric properties of P
– Type semiconductor substrate.

Concentration of carrier in semiconductor material is always following the Mass Action

Law. Mass Action Law is given by −

n.p=n2in.p=ni2

Where,

 n is carrier concentration of electrons

 p is carrier concentration of holes

 ni is intrinsic carrier concentration of Silicon

Now assume that substrate is equally doped with acceptor (Boron) concentration NA. So,
electron and hole concentration in p–type substrate is

npo=n2iNAnpo=ni2NA

ppo=NAppo=NA

Here, doping concentration NA is (1015 to 1016 cm−3) greater than intrinsic concentration
ni. Now, to understand the MOS structure, consider the energy level diagram of p–type
silicon substrate.

Fig 4.2: Band gap between conduction band and valance band

As shown in the figure, the band gap between conduction band and valance band
is 1.1eV. Here, Fermi potential ΦF is the difference between intrinsic Fermi level (Ei)
and Fermi level (EFP).

36
Where Fermi level EF depends on the doping concentration. Fermi potential ΦF is the
difference between intrinsic Fermi level (Ei) and Fermi level (EFP).

Mathematically,

ΦFp=EF−EiqΦFp=EF−Eiq

The potential difference between conduction band and free space is called electron
affinity and is denoted by qx.

So, energy required for an electron to move from Fermi level to free space is called work
function (qΦS) and it is given by

qΦs=(Ec−EF)+qxqΦs=(Ec−EF)+qx

The following figure shows the energy band diagram of components that make up the
MOS.

Fig 4.3: The energy band diagram of components that make up the MOS.

As shown in the above figure, insulating SiO2 layer has large energy band gap of 8eV
and work function is 0.95 eV. Metal gate has work function of 4.1eV. Here, the work
functions are different so it will create voltage drop across the MOS system. The figure
given below shows the combined energy band diagram of MOS system.

Fig 4.4: combined energy band diagram of MOS system

37
As shown in this figure, the fermi potential level of metal gate and semiconductor (Si)
are at same potential. Fermi potential at surface is called surface potential ΦS and it is
smaller than Fermi potential ΦF in magnitude.

Working of a MOSFET

MOSFET consists of a MOS capacitor with two p-n junctions placed closed to the
channel region and this region is controlled by gate voltage. To make both the p-n
junction reverse biased, substrate potential is kept lower than the other three terminals
potential.

If the gate voltage will be increased beyond the threshold voltage (V GS>VTO), inversion
layer will be established on the surface and n – type channel will be formed between the
source and drain. This n – type channel will carry the drain current according to the
VDSvalue.

For different value of VDS, MOSFET can be operated in different regions as explained
below.

Linear Region

At VDS = 0, thermal equilibrium exists in the inverted channel region and drain current
ID = 0. Now if small drain voltage, VDS > 0 is applied, a drain current proportional to the
VDS will start to flow from source to drain through the channel.

The channel gives a continuous path for the flow of current from source to drain. This
mode of operation is called linear region. The cross sectional view of an n-channel
MOSFET, operating in linear region, is shown in the figure given below.

Fig. 4.5: The cross sectional view of an n-channel MOSFET, operating in linear region

38
At the Edge of Saturation Region

Now if the VDS is increased, charges in the channel and channel depth decrease at the
end of drain. For VDS = VDSAT, the charges in the channel is reduces to zero, which is
called pinch – off point. The cross sectional view of n-channel MOSFET operating at
the edge of saturation region is shown in the figure given below.

Fig. 4.6: The cross sectional view of n-channel MOSFET operating at the edge of
saturation region

Saturation Region

For VDS>VDSAT, a depleted surface forms near to drain, and by increasing the drain
voltage this depleted region extends to source.

This mode of operation is called Saturation region. The electrons coming from the
source to the channel end, enter in the drain – depletion region and are accelerated
towards the drain in high electric field.

Fig 4.7: Drain – depletion region and are accelerated towards the drain in high electric
field

39
MOSFET Current – Voltage Characteristics

To understand the current – voltage characteristic of MOSFET, approximation for the

channel is done. Without this approximation, the three dimension analysis of MOS
system becomes complex. The Gradual Channel Approximation (GCA) for current –
voltage characteristic will reduce the analysis problem.

Gradual Channel Approximation (GCA)

Consider the cross sectional view of n channel MOSFET operating in the linear mode.
Here, source and substrate are connected to the ground. VS = VB = 0. The gate – to –
source (VGS) and drain – to – source voltage (VDS) voltage are the external parameters
that control the drain current ID.

Fig 4.8: Direction is perpendicular to the surface and y – direction is parallel to the
surface.

The voltage, VGS is set to a voltage greater than the threshold voltage VTO, to
create a channel between the source and drain. As shown in the figure, x – direction is
perpendicular to the surface and y – direction is parallel to the surface.

Here, y = 0 at the source end as shown in the figure. The channel voltage, with respect to
the source, is represented by VC(Y). Assume that the threshold voltage VTO is constant
along the channel region, between y = 0 to y = L. The boundary condition for the
channel voltage VC are −

Vc(y=0)=Vs=0andVc(y=L)=VDSVc(y=0)=Vs=0andVc(y=L)=VDS

We can also assume that

VGS≥VTOVGS≥VTO

40
and

VGD=VGS−VDS≥VTOVGD=VGS−VDS≥VTO

Let Q1(y) be the total mobile electron charge in the surface inversion layer. This electron
charge can be expressed as −

Q1(y)=−Cox.[VGS−VC(Y)−VTO]Q1(y)=−Cox.[VGS−VC(Y)−VTO]

The figure given below shows the spatial geometry of the surface inversion layer and
indicate its dimensions. The inversion layer taper off as we move from drain to source.
Now, if we consider the small region dy of channel length L then incremental resistance
dR offered by this region can be expressed as −

dR=−dyw.μn.Q1(y)dR=−dyw.μn.Q1(y)

Here, minus sign is due to the negative polarity of the inversion layer charge Q1 and
μn is the surface mobility, which is constant. Now, substitute the value of Q1(y) in the
dR equation −

dR=−dyw.μn.{−Cox[VGS−VC(Y)]−VTO}dR=−dyw.μn.{−Cox[VGS−VC(Y)]−VTO}

dR=dyw.μn.Cox[VGS−VC(Y)]−VTOdR=dyw.μn.Cox[VGS−VC(Y)]−VTO

Now voltage drop in small dy region can be given by

dVc=ID.dRdVc=ID.dR

Put the value of dR in the above equation

dVC=ID.dyw.μn.Cox[VGS−VC(Y)]−VTOdVC=ID.dyw.μn.Cox[VGS−VC(Y)]−VTO

w.μn.Cox[VGS−VC(Y)−VTO].dVC=ID.dyw.μn.Cox[VGS−VC(Y)−VTO].dVC=ID.dy

To obtain the drain current ID over the whole channel region, the above equation can be
integrated along the channel from y = 0 to y = L and voltages VC(y) = 0 to VC(y) = VDS,

Cox.w.μn.∫VDSVc=0[VGS−VC(Y)−VTO].dVC=∫LY=0ID.dyCox.w.μn.∫Vc=0VDS[VGS
−VC(Y)−VTO].dVC=∫Y=0LID.dy

Cox.w.μn2(2[VGS−VTO]VDS−V2DS)=ID[L−0]Cox.w.μn2(2[VGS−VTO]VDS−VDS2)
=ID[L−0]

ID=Cox.μn2.wL(2[VGS−VTO]VDS−V2DS)ID=Cox.μn2.wL(2[VGS−VTO]VDS−VDS2
)

41
For linear region VDS < VGS − VTO. For saturation region, value of VDS is larger than
(VGS − VTO). Therefore, for saturation region VDS= (VGS − VTO).

ID=Cox.μn.w2([2VDS]VDS−V2DSL)ID=Cox.μn.w2([2VDS]VDS−VDS2L)

ID=Cox.μn.w2(2V2DS−V2DSL)ID=Cox.μn.w2(2VDS2−VDS2L)

ID=Cox.μn.w2(V2DSL)ID=Cox.μn.w2(VDS2L)

ID=Cox.μn.w2([VGS−VTO]2L)ID=Cox.μn.w2([VGS−VTO]2L)

VLSI Design - MOS Inverter

The inverter is truly the nucleus of all digital designs. Once its operation and properties
are clearly understood, designing more intricate structures such as NAND gates, adders,
multipliers, and microprocessors is greatly simplified. The electrical behavior of these
complex circuits can be almost completely derived by extrapolating the results obtained
for inverters.

The analysis of inverters can be extended to explain the behavior of more complex gates
such as NAND, NOR, or XOR, which in turn form the building blocks for modules such
as multipliers and processors. In this chapter, we focus on one single incarnation of the
inverter gate, being the static CMOS inverter — or the CMOS inverter, in short. This is
certainly the most popular at present and therefore deserves our special attention.

Principle of Operation

The logic symbol and truth table of ideal inverter is shown in figure given below. Here A
is the input and B is the inverted output represented by their node voltages. Using
positive logic, the Boolean value of logic 1 is represented by Vdd and logic 0 is
represented by 0. Vth is the inverter threshold voltage, which is Vdd /2, where Vdd is the
output voltage.

The output is switched from 0 to Vdd when input is less than Vth. So, for
0<Vin<Vth output is equal to logic 0 input and Vth<Vin< Vddis equal to logic 1 input for
inverter.

42
 Fig 4.9: The characteristics shown in the figure are ideal.

The generalized circuit structure of an nMOS inverter is shown in the figure below.

Fig. 4.10: The generalized circuit structure of an nMOS inverter

From the given figure, we can see that the input voltage of inverter is equal to the gate to
source voltage of nMOS transistor and output voltage of inverter is equal to drain to
source voltage of nMOS transistor. The source to substrate voltage of nMOS is also
called driver for transistor which is grounded; so VSS = 0. The output node is connected
with a lumped capacitance used for VTC.

Resistive Load Inverter

The basic structure of a resistive load inverter is shown in the figure given below. Here,
enhancement type nMOS acts as the driver transistor. The load consists of a simple
linear resistor RL. The power supply of the circuit is VDD and the drain current ID is equal
to the load current IR.

43
 Fig. 4.11: The basic structure of a resistive load inverter

Circuit Operation

When the input of the driver transistor is less than threshold voltage VTH (Vin < VTH),
driver transistor is in the cut – off region and does not conduct any current. So, the
voltage drop across the load resistor is ZERO and output voltage is equal to the VDD.
Now, when the input voltage increases further, driver transistor will start conducting the
non-zero current and nMOS goes in saturation region.

Mathematically,

ID=Kn2[VGS−VTO]2ID=Kn2[VGS−VTO]2

Increasing the input voltage further, driver transistor will enter into the linear region and
output of the driver transistor decreases.

ID=Kn22[VGS−VTO]VDS−V2DSID=Kn22[VGS−VTO]VDS−VDS2

VTC of the resistive load inverter, shown below, indicates the operating mode of driver
transistor and voltage points.

44
 Fig. 4.12: Inverter with N type MOSFET Load

The main advantage of using MOSFET as load device is that the silicon area occupied
by the transistor is smaller than the area occupied by the resistive load. Here, MOSFET
is active load and inverter with active load gives a better performance than the inverter
with resistive load.

Enhancement Load NMOS

Two inverters with enhancement-type load device are shown in the figure. Load
transistor can be operated either, in saturation region or in linear region, depending on
the bias voltage applied to its gate terminal. The saturated enhancement load inverter is
shown in the fig. (a). It requires a single voltage supply and simple fabrication process
and so VOH is limited to the VDD − VT.

45
 Fig. 4.13: The linear enhancement load inverter is shown in the fig. (b). It always
operates in linear region; so VOH level is equal to VDD.

Linear load inverter has higher noise margin compared to the saturated enhancement
inverter. But, the disadvantage of linear enhancement inverter is, it requires two separate
power supply and both the circuits suffer from high power dissipation. Therefore,
enhancement inverters are not used in any large-scale digital applications.

Fig. 4.14: Depletion Load NMOS

46
Drawbacks of the enhancement load inverter can be overcome by using depletion load
inverter. Compared to enhancement load inverter, depletion load inverter requires few
more fabrication steps for channel implant to adjust the threshold voltage of load.

The advantages of the depletion load inverter are - sharp VTC transition, better noise
margin, single power supply and smaller overall layout area.

As shown in the figure, the gate and source terminal of load are connected; So, VGS = 0.
Thus, the threshold voltage of the load is negative. Hence,

VGS,load>VT,loadVGS,load>VT,load

is satisfied

Therefore, load device always has a conduction channel regardless of input and output
voltage level.

When the load transistor is in saturation region, the load current is given by

ID,load=Kn,load2[−VT,load(Vout)]2ID,load=Kn,load2[−VT,load(Vout)]2

When the load transistor is in linear region, the load current is given by

ID,load=Kn,load2[2|VT,load(Vout)|.(VDD−Vout)−(VDD−Vout)2]ID,load=Kn,load2[2|V
T,load(Vout)|.(VDD−Vout)−(VDD−Vout)2]

The voltage transfer characteristics of the depletion load inverter is shown in the figure
given below −

Fig. 4.15: The voltage transfer characteristics of the depletion load inverter

47
CMOS Inverter – Circuit, Operation and Description

The CMOS inverter circuit is shown in the figure. Here, nMOS and pMOS transistors
work as driver transistors; when one transistor is ON, other is OFF.

Fig. 4.16: The CMOS inverter circuit

This configuration is called complementary MOS (CMOS). The input is connected to

the gate terminal of both the transistors such that both can be driven directly with input
voltages. Substrate of the nMOS is connected to the ground and substrate of the pMOS is
connected to the power supply, VDD.

So VSB = 0 for both the transistors.

VGS,n=VinVGS,n=Vin

VDS,n=VoutVDS,n=Vout

And,

VGS,p=Vin−VDDVGS,p=Vin−VDD

VDS,p=Vout−VDDVDS,p=Vout−VDD

When the input of nMOS is smaller than the threshold voltage (Vin< VTO,n), the nMOS is
cut – off and pMOS is in linear region. So, the drain current of both the transistors is
zero.

ID,n=ID,p=0ID,n=ID,p=0

Therefore, the output voltage VOH is equal to the supply voltage.

Vout=VOH=VDDVout=VOH=VDD

48
When the input voltage is greater than the VDD + VTO,p, the pMOS transistor is in the
cutoff region and the nMOS is in the linear region, so the drain current of both the
transistors is zero.

ID,n=ID,p=0ID,n=ID,p=0

Therefore, the output voltage VOL is equal to zero.

Vout=VOL=0Vout=VOL=0

The nMOS operates in the saturation region if Vin > VTO and if following conditions are
satisfied.

VDS,n≥VGS,n−VTO,nVDS,n≥VGS,n−VTO,n

Vout≥Vin−VTO,nVout≥Vin−VTO,n

The pMOS operates in the saturation region if Vin < VDD + VTO,pand if following
conditions are satisfied.

VDS,p≤VGS,p−VTO,pVDS,p≤VGS,p−VTO,p

Vout≤Vin−VTO,pVout≤Vin−VTO,p

Table 4.1: For different value of input voltages, the operating regions are listed below
for both transistors.

Region Vin Vout nMOS pMOS

A < VTO, n VOH Cut – off Linear

B VIL High ≈ VOH Saturation Linear

C Vth Vth Saturation Saturation

D VIH Low ≈ VOL Linear Saturation

E > (VDD + VTO, p) VOL Linear Cut – off

49
 Fig. 4.17: The VTC of CMOS is shown in the figure below

Combinational MOS Logic Circuits

Combinational logic circuits or gates, which perform Boolean operations on multiple

input variables and determine the outputs as Boolean functions of the inputs, are the
basic building blocks of all digital systems. We will examine simple circuit
configurations such as two-input NAND and NOR gates and then expand our analysis to
more general cases of multiple-input circuit structures.

TANNER EDA

Tanner EDA is a suite of tools for the design of integrated circuits. Tanner EDA is mainly
used to analyze circuits at switch level & gate level. These are tool used to

 Enter schematics
 Perform SPICE simulations
 Do physical design (i.e., chip layout)
 Perform design rule checks (DRC) and layout versus schematic (LVS) checks.
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50
 W-edit - waveform formatting
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 Noise analysis.
 Monte Carlo analysis over unlimited variables and trials.
 Virtual measurements with functions for timing, error, and statistical analysis.
 Parameter sweeping using linear, log, discrete value, or external file data sweeps.
 Transient Analysis, Power-up Mode.

51
 CHAPTER – 5

RESULT

Fig: 5.1 pulsar used for the PL-SW based register.

Fig. 5.2. Simulated results of pulsar used for the PL-SW based register.

52
 Fig.5.3.pulser used for the PL-MUX based register.

Fig.5.4.simulated results of pulsar used for the PL-MUX based register.

53
 CONCLUSION
In this project, an analysis of the effect of PVT variations on the pulsed latch performance was
presented. The analysis considered both the pulsar and the latch to evaluate the reliability of the
entire pulsed latch circuit. In addition, the benefits of having a reconfigurable pulsed latch circuit
was discussed. Two novel modifications to add the reconfiguration ability to TGPL circuits were
proposed.

The benefits of using the proposed design approaches in enhancing the robustness of pulsed latch
circuits at different supply voltages were demonstrated using 16-bit registers. Both proposed
approaches were able to ensure reliable operation of the pulsed latch-based register under
different supply voltages in the presence of process and temperature variations, without any
unnecessary timing overhead. Both approaches have a very small area overhead of around 3% or
less. In addition, the power overhead of both approaches is minimal when compared to the
traditional pulsed latch based register at the same reliability level. Both approaches are easily
scalable to cover different levels of voltage scaling. In addition, they can be applied to any other
pulsed latches topology that depends on a delay path to generate the output pulse.

The benefits of using the proposed design approaches in enhancing the robustness of pulsed
latch circuits at different supply voltages were demonstrated using 16-bit registers. Both
proposed approaches were able to ensure reliable operation of the pulsed latch-based register
under different supply voltages in the presence of process and temperature variations,
without any unnecessary timing overhead. Clock gating based devices plays vita and
significant role in all type of circuits with improved performance. The analysis considered
both the pulser and the latch to evaluate the reliability of the entire pulsed latch circuit. In
addition, the benefits of having a reconfigurable pulsed latch circuit was discussed. Two novel
modifications to add the reconfiguration ability to TGPL circuits were proposed.

54
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