STUDENT ID NO

LECTURE SECTION STUDENT NAME

FACULTY OF COMPUTING AND INFORMATICS

MULTIMEDIA UNIVERSITY

SECOND TRIMESTER MID-TERM TEST 1, 2012/2013 SESSION

TSN 1101 – COMPUTER ARCHITECTURE AND

ORGANIZATION
(Section A: Digital Logic Design)

07 December 2012
8.00 pm – 9.00 pm
(1 Hour)

INSTRUCTIONS

1. This Question paper consists of TEN pages (excluding this page) with FOUR questions.

2. Attempt any THREE out of FOUR questions. Each question carries 10 marks and the
distribution of the marks for each subdivision is given. Maximum allotted are 30 marks.

3. Please write your answers in the Question paper itself in the space provided.
TSN1101 COMPUTER ARCHITECTURE AND ORGANIZATION 7 December 2012

Answer only THREE out of FOUR questions. Each question carries 10 marks and the
distribution of the marks for each subdivision is given. (𝟑 × 𝟏𝟎 = 𝟑𝟎 𝐦𝐚𝐫𝐤𝐬)

QUESTION 1:

a. An address of a memory location is represented in hexadecimal as (𝐂𝐀𝐃𝟑)𝟏𝟔 . Identify the

address in Binary and Octal representation. (𝟐 𝐦𝐚𝐫𝐤𝐬)

b. The arithmetic operation ([(25 + 46 + 67) − 45] = 115) is correct in one of the following
number systems, (i) Decimal (Base 10) (ii) Octal (Base 8), or (iii) Hexadecimal (Base
16). Identify the number system used. Show your calculations. (𝟐 𝐦𝐚𝐫𝐤𝐬)

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TSN1101 COMPUTER ARCHITECTURE AND ORGANIZATION 7 December 2012

c. Perform the following conversions and complete the table.

Binary Decimal Excess 3 code 2421 code Gray code

(𝟏𝟎𝟏𝟏. 𝟏𝟏)
(𝟒 𝐦𝐚𝐫𝐤𝐬)

d. Identify the parity bit (0 or 1) to be sent along with each of the following information bits.
Assume that transmitter and receiver have agreed upon odd parity protocol.
(i) 10101101
(ii) 11010010
(𝟐 𝐦𝐚𝐫𝐤𝐬)

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QUESTION 2:

a. Assume the decimal numbers given are

R = (5) and S = (−4)

(i) Represent the above decimal numbers in 4-bit twos complement representation.
(ii) Perform (𝐑) + (𝐒) With the represented 4-bit twos complement numbers.
(iii)Identify whether the overflow flag is set or not after performing addition as in (ii).
(𝟐 + 𝟏 + 𝟏 = 𝟒 𝐦𝐚𝐫𝐤𝐬)

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b. Perform the multiplication of two 4-bit two complement numbers given below. Use Booth’s
algorithm (Flowchart is given below).
Multiplicand (M) = (1110)2 or (−2)10
Multiplier (Q) = (0011)2 or (3)10
(𝟒 𝐦𝐚𝐫𝐤𝐬)

Solution:

A Q Q −1 M

Product = AQ =

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c. (i) Identify the bias used for IEEE 32-bit floating point representation. Note that 8 bits
are used for representing biased exponent.
(ii) If the true exponent is 6, then identify the biased exponent in this format and express it
in binary.
(𝟏 + 𝟏 = 𝟐 𝐦𝐚𝐫𝐤𝐬)

QUESTION 3:

a. Write down the truth table of 3-input OR gate. (𝟐 𝐦𝐚𝐫𝐤𝐬)

INPUTS OUTPUT
𝐀 𝐁 𝐂 𝐅
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

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b. Boolean expression (F) of two input XNOR gate is

̅B
F=A ̅ + AB

(i) Find the complement (F̅) and show that it is equivalent to two input XOR gate (Note:
Apply DeMorgan’s theorem and Boolean rules / laws for simplification)
(ii) Show that (FF̅) = 0 using Boolean algebra rules or by using truth tables for 2 input
XNOR and 2 input XOR gates.
(iii)Identify 𝐅 (XNOR output) if two inputs are 𝟏𝟎𝟏𝟎𝟏𝟏 and 𝟏𝟎𝟏𝟎𝟎𝟏.
(𝟐 + 𝟐 + 𝟏 = 𝟓 𝐦𝐚𝐫𝐤𝐬)

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c. (i) Identify the Boolean expression at the output 𝒀 for the combinational logic circuit given
below, if 𝐴, 𝐵 and 𝐶 are the inputs.
(ii) Identify the logic level at the output 𝒀, if the inputs 𝐀 = 𝟎, 𝐁 = 𝟏, and 𝐂 = 𝟎?
(𝟐 + 𝟏 = 𝟑 𝐦𝐚𝐫𝐤𝐬)

(i)

(ii)

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TSN1101 COMPUTER ARCHITECTURE AND ORGANIZATION 7 December 2012

QUESTION 4:

̅) + (BC̅) + (A
a. For the Boolean function, F = (AB ̅BC̅)

(i) Construct the appropriate truth table, and

(ii) Find the standard SOP and standard POS expressions.
(𝟐 + 𝟐 = 𝟒 𝐦𝐚𝐫𝐤𝐬)

(i)

INPUTS OUTPUT
𝐀 𝐁 𝐂 𝐅
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

(ii) STANDARD SOP EXPRESSION:

STANDARD POS EXPRESSION:

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b. Design a 3-input majority circuit. Assume that a 3-input majority circuit is one which
produces a HIGH (1) when two or more inputs are HIGH (1). Your design should include

(i) Truth table indicating all possible combinations for the inputs and the corresponding
output for each input combination. (𝟐 𝐦𝐚𝐫𝐤𝐬)

(ii) Simplified Sum-of-Products (SOP) Boolean expression using Karnaugh Map.

(𝟐 𝐦𝐚𝐫𝐤𝐬)

(iii)Logic diagram using only NAND gates. (𝟐 𝐦𝐚𝐫𝐤𝐬)

(i)

INPUTS OUTPUT
𝐀 𝐁 𝐂 𝐅
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

(ii) Simplified SOP Boolean expression:

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(iii)Logic Diagram using only NAND gates:

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