• PLDs

• Programmable Logic Devices (PLD)

• General purpose chip for implementing circuits
• Can be customized using programmable switches

• Main types of PLDs

• PLA
• PAL
• ROM
• CPLD
• FPGA

• Custom chips: standard cells, sea of gates

1
• PLD as a Black Box

Logic gates
Inputs and Outputs
(logic variables) programmable (logic functions)
switches

2
• Programmable Logic Array (PLA)

• Use to implement x1 x2 xn

circuits in SOP form

• The connections in Input buffers

and
the AND plane are inverters
programmable
x1 x1 xn xn

• The connections in P1
the OR plane are
AND plane OR plane
programmable Pk

f1 fm
3
 • Gate Level Version of PLA
x1 x2 x3

Programmable
connections

OR plane
P1
f1 = x1x2+x1x3'+x1'x2'x3
P2

f2 = x1x2+x1'x2'x3+x1x3
P3

P4

AND plane

f1 f2

4
 • Customary Schematic of a PLA
x1 x2 x3

f1 = x1x2+x1x3'+x1'x2'x3
OR plane
f2 = x1x2+x1'x2'x3+x1x3
P1

P2

P3

P4
x marks the connections
left in place after
programming AND plane

f1 f2

5
What is an FPGA?

Configurable
Logic
Blocks
Block RAMs

Block RAMs
I/O
Blocks

Block
RAMs

6
Other FPGA Advantages

• Manufacturing cycle for ASIC is very costly,

lengthy and engages lots of manpower
• Mistakes not detected at design time have
large impact on development time and cost
• FPGAs are perfect for rapid prototyping of
digital circuits
• Easy upgrades like in case of software
• Unique applications
• reconfigurable computing

7
Array-Based Programmable Wiring

Interconnect
Point
M

Programmed interconnection Input/output pin

Cell

Horizontal
tracks

Vertical tracks

8
Fuse-Based FPGA

antifuse polysilicon ONO dielectric

n+ antifuse diffusion

2l

Open by default, closed by applying current pulse

From Smith97 9
 XC4000 Architecture
Vcc
Slew Passive
CLB CLB Rate Pull-Up,
Control Pull-Down

Switch
Matrix D Q
Output Pad
Buffer

Input
CLB CLB Buffer
Q D
Delay

Programmable
Interconnect I/O Blocks (IOBs)
C1 C2 C3 C4

H1 DIN S/R EC
S/R
Control

G4 DIN
G3 G F'
SD

G2 Func. G' D Q

Gen. H'

G1
EC
RD
1

H G'
Y
Func. H'
S/R

F4 Gen. Control

F3 F DIN
Func. SD
F2 Gen.
F'
G' D Q

F1 H'

EC
RD
1
H'
F'
X
K

Configurable
Logic Blocks (CLBs)

10
XC4000E/X Configurable Logic Blocks

C1 C2 C3 C4
• 2 Four-input function
generators (Look Up H1 DIN S/R EC
Tables) S/R
Control

- 16x1 RAM or G4 DIN

SD
G3 G F'
D Q YQ
Logic function G2 Func.
G'
H'
Gen.
• 2 Registers G1 EC
RD
- Each can be H G'
1

Y
H'
configured as Flip Func S/R

.Gen.
Control

Flop or Latch F4
F3 F DIN
SD
- Independent Func. F'
D Q XQ
F2 Gen. G'
H'

clock polarity F1
EC
- Synchronous and H'
1
RD

X
asynchronous K
F'

Set/Reset

11
Look Up Tables

• Combinatorial Logic is stored in 16x1 SRAM Look Up

Tables (LUTs) in a CLB Look Up Table
• Example: 4-bit address
Combinatorial Logic
A B C D Z
A 4
0 0 0 0 0 (2 )
B
Z 0 0 0 1 0 2
C
D
0 0 1 0 0 = 64K !
0 0 1 1 1
0 1 0 0 1

Capacity is limited by number of 0 1 0 1 1
inputs, not complexity . . .

Choose to use each function 1 1 0 0 0
generator as 4 input logic (LUT) or 1 1 0 1 0
as high speed sync.dual port 1 1 1 0 0
RAM WE 1 1 1 1 1
G4
G3 G
G2 Func.
Gen.
G1
12
LUT (Look-Up Table) Functionality
x1
x2
y
• Look-Up tables
x1 x2 x3 x4 y x3 LUT x1 x2 x3 x4 y
0 0 0 0 1
x4
0 0 0 0 0 are primary
0 0 0 1 1 0 0 0 1 1
0 0 1 0 1 0 0 1 0 0 elements for
0 0 1 1 1 0 0 1 1 0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
0
1
0
1
logic
0
0
1
1
1
1
0
1
1
1
0
0
1
1
1
1
0
1
0
1 implementation
1 0 0 0 1 1 0 0 0 0
1
1
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
1
0 • Each LUT can
1 0 1 1 1 1 0 1 1 0
1 1 0 0 0 1 1 0 0 1 implement any
1 1 0 1 0 x1 x2 x3 x4 1 1 0 1 1
1
1
1
1
1
1
0
1
0
0
1
1
1
1
1
1
0
1
0
0
function of 4
inputs
x1 x2

13
5-Input Functions implemented using two LUTs
X5 X4 X3 X2 X1 Y
0 0 0 0 0 0
0 0 0 0 1 1
0 0 0 1 0 0
0 0 0 1 1 0
0 0 1 0 0 1
0 0 1 0 1 1
0 0 1 1 0 0
0 0 1 1 1 0 LUT
0 1 0 0 0 1
0 1 0 0 1 0
0 1 0 1 0 0
0 1 0 1 1 1 OUT
0 1 1 0 0 1
0 1 1 0 1 1
0 1 1 1 0 1
0 1 1 1 1 1
1 0 0 0 0 0
1 0 0 0 1 0
1 0 0 1 0 0
1 0 0 1 1 0
1 0 1 0 0 0
1 0 1 0 1 0
1 0 1 1 0 0
1 0 1 1 1 1
1 1 0 0 0 0
1 1 0 0 1 1
LUT
1 1 0 1 0 0
1 1 0 1 1 1
1 1 1 0 0 0
1 1 1 0 1 1
1 1 1 1 0 0
1 1 1 1 1 0

14
XC4000X I/O Block Diagram

15
Routing Resources

CLB CLB CLB

PSM PSM
Programmable
Switch
CLB CLB CLB Matrix

PSM PSM

CLB CLB CLB

16
Clock Distribution

17
RAM-based FPGA

Xilinx XC4000ex

Courtesy Xilinx 18