EEE 5 - ProblemSet#3

2.a Semester A.Y. 20-J.6-2077

Deadline: 11:30am May 02,2077

I nstructions:
. Write your ansr,vers on a 'yellow'pad paper(s). Staple on the upper left corner if using multiple
sheets of paper.
o Alwavs show vour comnlete solution.
. Put your name, student number, and section on the upper right corner of each page.
o Submit yourtime-stamped papers in the drop box on EEEI Rm.220.
o No late submission will be accepted.

Part 1 fFundamental laws ofBooleanAlgebra)

Provethat the followingidentities are equivalent using the fundamental laws of Boolean algebra. Show
t}le step-bv-step manipulation of the Boolean expressions until you come up with the desired
expression/form. (3 points each)
a) Prove fstep-by-step) that the Boolean expression (A +B + C)(A + B + C')(A'+ B + C)(A'+ B + C')
can be simplified into a liaralterm.
b) Prove (step-by-step) that ,48(l'B + A' B' + AB') can be simplified into an OR of two literals.

al , [(err-cXa.e 'c:)ar'*a,c)<D''B'c'))" l) (r''l')(a'a 't'o'*ta')

. [6r.o.c),.(r ts.c),t(e.+sqc).,'.-e-"'r'J' Ii:r]ll;;:if;;""'
' I r'a'c'. ddc . rac'. rr'c ]' ( a'l
*'+o')(eb+ ,..t
. ['ed("'..). ,916.c))' i;:3][,,,r,._,.r{i,,1j',t
'[r'o(r)+ re'r,)]' (t,rCiii!.'l
' 1p'i* rdl'[s'(D'.a)]t'[t'crl]' ( a.tt,)
'tu'l'
.D

Part 2 (Implementation of Boolean Expressiors using Logic Gates)

Answer the followingby directly fanslating the Boolean expression into its equivalent logic circuit
withoutsimpliftcation.You are not limited to the use of NOT, AND, OR, and XORgates. You may also
use NAND, NOR, and XNORgates as yousee appropriate. You may also use logic gates with more than 2
inputs. (2 points each)
(BONUS: Indicate the equivalent simplified expression)

a') M(A,B,C) - (A OC)BA + B

b) N(A,B,C,D) = (1c .. 6;64;;1t * ,,
should have no circle
e)O !4 b) A
N
e 6
c
c 0
 Part 3 (Analysis of Combinatioml Circuits)
Answer by direcdy translating the logic circuit withoutsimplification.
a) Complete the table below by providing the logic expression for the followingvariables in the circuit
in Figure 3a. [1.5 points)
Logic Expression
x(A,B,C) loD
Y(A,8, C') ,6C
z(A,8, C',) (roc)+(cA-o1.7

bJ Complete the table below by providing the logic expression for the followingvariables in the circuit
in Figure 3b. (1.5 poinal
Logic Expression
R(A,B,c,D) (t.c)
s(A, B,C,D) C(netr 7..Y 1'
ru,B,c,D) f (rrxr{c)'l'c

I o
A S
A
B a
B Z T
C
c
D
Figure 3a Figure 3b

Part 4 (Karnaugh Maps)

Determine the simplified POS and SOP for the logical expressions below.Show the 2 K-maps foreach
letter withthe groupings to determine the minimized POSand SOP. [21points)
a) f (A, B, c, D) = Z@j,2,3,s,6,7,10,14,1s)
b) g(w,x,Y,z) = II M(s,7,13,1s)
c) rr(Q, R,s) = o(nsl + oR(s + R') + R(s + s?)

a') C'
r0
4 (d+crr).(C'c).( I'ta' r' ) c)( G .3)* 6,ns + a8( . &5 ' o(c
0al
=
'a I. -l,i.1[1r')Rs+o't*s
Ct J = a'B'r ,O t gC n cPt -a i.dE.x5+Qci
It
tc ofrr,D- a(
s

I
0l

o)
CtIYEI 1, (4, c)
! a ,(r'r J) r-vJAF)
h'o'+
ao
0r
tl
H rd LI
x

s
)r'r+
R

I
Part 5 (Design Problem 1)
An AND gate's output is 1 ifall inputs are 1. An 0R gate's output is 1 if at least one ofits input is 1. A 2-
input XoRgate's output is one ifone of its input is 1 but the other is 0. However, in general, an XOR
gate's output is 1 ifthe number of 1's in its input is odd. Design a logic circuitthat acts behaves like a 4-
input XOR The inputs of the XORgate are A, B, C, and D while is output is X.
Meanwhile a multiplexer is a logic circuitthat switches a single output to a set ofinputs based on a
control signal. Desigr a 2-input multiplexer with enable. The output is Y. The enable sigral is A" When A
is 0 the output is always zero; otherwise, the output will be dependent on B, C, and D. B is the control
signal while C and D are the input sigaals. IfB is 0, the output Y takes the value ofC. If B is 1, the output
Y takes the value ofD.

al Using the descriptions above, complete the table below. (4 points) x

9
Input Ouhut cA ,t tt
a0 0 I o !
A B C D X [xor) Y [mux)
o
0r o I
0 0 0 0 o
Ir 0 0 I
0 0 0 1 I o
ro I o o
0 0 1 0 , o
o 0 1 1 o D
r, A,O'c;g + A'dcd +
0 1 0 0 I o e'aci > e'oco +
0 I 0 1 o 0 hgc'0 r CgCr'{
0 1 1 0 o o t o'- eica
o 1 1 1 t
0 Y
I 0 0 0 I o CD o
1 0 0 l o a 00 I o
o ot 0 o
1 0 1 0 I 0

1 0 1 1 I !t 0 0

I t 0 0 o @ 0 0

1 1 0 1 t I

1 1 I 0 ! o 'f?DODreob
1 1 1 1 o I

b) Draw the equivalent K-map for X and highlight the groupings to needed to come up with a simplified
SOP expression forX. (3 poins)

c) What is the simplified SOP expression for X. (3 points)

c) Draw the equivalent K-map forY and highlight the groupings to needed to comeup with a simplified
SOP expression forY. (3 points)

c) What is the simplified SOP expression for Y. (3 points)

Part 6 (Design Problem 2)

A 7-segment display has 8 input pins aside from either the ground (forcommon cathodes) or VCC ffor
common anodes). The I inputs correspond to the 7 segments and the dot that light up depending on the
input and type of 7-segment display. For common cathodes, each segment/dot lights up whenever its
corresponding input is at a high voltage which we will consider a '1'. ln this exercise, we disregard the
doL
 Common Cathodr Common Anode
, I d. b

'I

Suppose we are to create a logic blockto interface a common cathode 7-segment display so that it can
display the numbers 0-9, depending on an input Z which is a 4-bit number. lfthe input Z exceeds the
number 9, then an 'X' should be displayed where only top and bottom segments are NOT lit up fdisplay
is similar to 'H'J, The table below shows an example for the input-to-output correspondence for
segment a.

Z Displayed Output
Zt Zz Zt Zo Number/Charactsr a
0 0 0 0 0 1
0 0 0 1 1 0
0 0 1 0 Z 1
0 0 1 1
) 1
0 I t, 0 4 0
0 1 0 1 5 1
0 1 7 0 6 1
0 1 1 1 7 1
1 0 0 0 I 1
1 0 0 1 9 L
L 0 1 0 'x' 0
1 0 I 1 'x' 0
,x,
1 1 0 0 0
7 1 0 1 'x' 0
,x,
1 1 1 0 0
1 1 1 1 'x' 0

7 a
a a
b b b
23
LOGIC c c
z Zt d d I
Zt
Zo
oc K e
t e
g
 Eachsegment lights up whenever its corresponding signal is high. For example, to display the number
9, <a,b,c,...,g> should be <1111011> where only segment e is off.The way the numbers are displayed
should follow the image below:

NEEHS
ENfEEE
The real bonus exercise: Determining the digital circuify forsegment d.
a) Complete the tnrth table for the output for segment d only, be sure to include t}re input combination
Z. [4 pointsJ

bJ Create a K-map for the logic for segment d. (3 points)

cJ Determine the simplest SOP expression for it. [3 points)

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