D12S

Hardware Description

HUAWEI TECHNOLOGIES CO., LTD.

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1.1 D12S
This topic describes the version, functions, working principle, front panel,
valid slots, and technical specifications of the D12S (32xE1/T1 switching
access board).

1.1.1 Version Description

The D12S is available in one functional version, namely, N1.

1.1.2 Application
The D12S is a PDH interface switching board. The D12S can be used on the
OptiX OSN equipment series to transmit and receive signals for the PDH
processing board. In addition, when the corresponding PDH processing board
is configured with the TPS protection, the interface switching board is
required to perform the TPS protection.

1.1.3 Functions and Features

The D12S receives and transmits 32xE1/T1 electrical signals. The D12S must
work with the PQ1, or PQM.

1.1.4 Working Principle and Signal Flow

The D12S consists of the interface module, switch matrix module, and power
access circuit.
Figure 11-55 shows the functional block diagram of the D12S by describing
how to process 1xE1/T1 signals.

Figure 1-1 Functional block diagram of the D12S

Backplane
Cross-connect board

E1/T1 electrical
signal PQ1/PQM/PO1
Interface Switch
matrix
module
module
E1/T1 electrical PQ1/PQM/PO1
signal

+3.3 V Fuse
+3.3 V power

Interface Module
The interface module receives and transmits the E1/T1 electrical signals.
Switch Matrix Module
In the receive direction, the switch matrix module receives the signal sent
from the interface module and selects the output direction of the signal
according to the TPS protection control signal sent from the cross-connect
board. When the TPS is not performed, the switch matrix module transmits
the signal to the PQ1 or PQM. When the TPS is performed, the switch matrix
module transmits the signal to the protection board for bridging.
In the transmit direction, the switch matrix module performs the reverse
process.

Power Access Circuit

The power access circuit provides all the modules of the D12S with the
required DC voltages.

1.1.5 Front Panel

The front panel of the D12S has interfaces and a bar code.

Diagram of the Front Panel

Figure 11-56 shows the appearance of the front panel of the D12S.
 Figure 1-2 Front panel of the D12S

D12S

1~8
9~16
17~24
25~32

D12S

Interfaces
The front panel of the D12S has four DB44 interfaces. Table 11-49 describes
the types and usage of the interfaces of the D12S.

Table 1-1 Interfaces of the D12S

Interface Type of Usage

Interface

1–8 DB44 Receives the 1st to the 8th channels of E1/T1

signals.
9–16 DB44 Receives the 9th to the 16th channels of E1/T1
signals.
17–24 DB44 Receives the 17th to the 24th channels of E1/T1
signals.
25–32 DB44 Receives the 25th to the 32nd channels of E1/T1
 Interface Type of Usage
Interface
signals.

Table 11-50 provides the pin assignments of the DB44 interface.

Table 1-2 Pin assignments of the DB44 interface

Front View Pin Usage Pin Usage

30
15 38 Receives the 1st 34 Receives the 5th
channel of signals channel of signals
44 23 19
(R1). (R5).
37 Receives the 2nd 33 Receives the 6th
channel of signals channel of signals
22 (R2). 18 (R6).
36 Receives the 3rd 32 Receives the 7th
channel of signals channel of signals
21 (R3). 17 (R7).
35 Receives the 4th 31 Receives the 8th
31 channel of signals channel of signals
1
20 (R4). 16 (R8).
16

15 Transmits the 1st 11 Transmits the 5th

channel of signals channel of signals
30 (T1). 26 (T5).
14 Transmits the 2nd 10 Transmits the 6th
channel of signals channel of signals
29 (T2). 25 (T6).
13 Transmits the 3rd 9 Transmits the 7th
channel of signals channel of signals
28 (T3). 24 (T7).
12 Transmits the 4th 8 Transmits the 8th
channel of signals channel of signals
27 (T4). 7 (T8).

1.1.6 Valid Slots

The D12S can be installed in slots 19–26 and 29–36 in the main subrack. The
D12S works as the interface board of the PQ1, or PQM.
Table 11-51 lists the slots valid for the PQ1/PQM and the corresponding slots
for the D12S. The D12S installed in the slot with a smaller number
transmits/receives the 1st to the 32nd channels of E1/T1 electrical signals. The
D12S installed in the slot with a larger number transmits/receives the 33rd to
the 63rd channels of E1/T1 electrical signals.
 Table 1-3 Slots valid for the PQ1/PQM and the corresponding slots for the D12S

Slot Valid for the PQ1/PQM Corresponding Slot for the D12S

Slot 2 Slots 19 and 20

Slot 3 Slots 21 and 22
Slot 4 Slots 23 and 24
Slot 5 Slots 25 and 26
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

1.1.7 Technical Specifications

The technical specifications of the D12S include the parameters specified for
the electrical interfaces, mechanical specifications and power consumption.

Parameters Specified for Electrical Interfaces

Table 1-4 Parameters specified for the electrical interfaces of the D12S

Nominal bit rate 1544 kbit/s 2048 kbit/s

Line code pattern B8ZS and AMI HDB3

Waveform at the output Complies with ITU-T G.703.
interface
Signal bit rate at the output
interface
Allowed attenuation at the
input interface
Allowed frequency deviation at Complies with ITU-T G.823.
the input interface
Input jitter tolerance Complies with ITU-T Complies with ITU-T
G.824. G.823.
Anti-interference capability at - Complies with ITU-T
the input interface G.703.
Reflection attenuation at the
input/output interface
Output jitter Complies with ITU-T G.823 and G.824.
Mapping jitter Complies with ITU-T G.783.
Combined jitter
 Nominal bit rate 1544 kbit/s 2048 kbit/s

Jitter transfer function - Complies with ITU-T

G.742.
Impedance (ohm) 120 (E1), 100 (T1)

Mechanical Specifications
The mechanical specifications of the D12S are as follows:
 Dimensions (mm): 22.0 (W) x 125.2 (D) x 261.4 (H)
 Weight (kg): 0.4

Power Consumption
At room temperature (25°C), the maximum power consumption of the D12S
is 0 W.