ECE 429 – Introduction to VLSI Design

Lecture 01 Introduction, CMOS Inverter

Professor Jia Wang

Department of Electrical and Computer Engineering
Illinois Institute of Technology

August 26, 2010

ECE 429 – Introduction to VLSI Design Fall 2010 1/90

Outline

Administrative Issues

Introduction

Semiconductor Basics

MOS Transistors

Ideal I-V Characteristics

Pulling Up/Down Characteristics

Complementary CMOS Inverter

Back to Reality: Non-Ideal I-V Effects and Noises

ECE 429 – Introduction to VLSI Design Fall 2010 2/90

Homework and Lab

I Homework 1
I Due 6:25pm 09/16 Chicago time (before class)
I Problems from textbook will be posted to Blackboard
I Lab 2
I Inverter schematic by Sue and simulation by IRSIM
I Software tutorials are posted on Blackboard
I Due 10:00am 09/17 Chicago time

ECE 429 – Introduction to VLSI Design Fall 2010 3/90

Reading Assignment (3rd ed.)

I This lecture: 1.1–1.3, 2.1–2.5.3

I Next lecture: 2.5.4, 1.4, 1.5, 3.1–3.6

ECE 429 – Introduction to VLSI Design Fall 2010 4/90

Outline

Administrative Issues

Introduction

Semiconductor Basics

MOS Transistors

Ideal I-V Characteristics

Pulling Up/Down Characteristics

Complementary CMOS Inverter

Back to Reality: Non-Ideal I-V Effects and Noises

ECE 429 – Introduction to VLSI Design Fall 2010 5/90

Instructor

I Professor Jia Wang

I Office: 317 Siegel Hall
I Phone: 312 567-3696
I E-Mail: jwang@ece.iit.edu
I Please start your email subject line with [ECE429].
I Office hours:
I Weds. 3:00 PM – 5:00 PM, SH 317
I Or by appointment

ECE 429 – Introduction to VLSI Design Fall 2010 6/90

TAs (Tentative)

I Xingliang Yuan: xyuan3@iit.edu

I Available in SH 310A during lab hours.
I Office hours: Mon. & Wed. 1:00 PM – 2:00 PM, SH 306A
I Li Li: lli9@iit.edu
I Homework and lab grading.

ECE 429 – Introduction to VLSI Design Fall 2010 7/90

Lecture Information

I Time: Thur. 6:25 PM – 9:05 PM

I Location: Life Science – Room 111
I Home Page: http://blackboard.iit.edu/
I Important messages will also be delivered through your IIT
email.
I Please always make sure your IIT email is not over quota.
I Required Textbook: “CMOS VLSI DESIGN: A Circuits and
Systems Perspective” (3rd ed.)
Neil H.E. Weste, and David Harris, Addison-Wesley, 2005.
ISBN: 0321149017
Or 4th ed. of the book

ECE 429 – Introduction to VLSI Design Fall 2010 8/90

Prerequisite

ECE 218 and ECE 311

I Familiarity with circuits, logic and digital system design.
I Experience with CAD tools and UNIX is a plus.

ECE 429 – Introduction to VLSI Design Fall 2010 9/90

Course Outline

Main topic: VLSI digital design, from RTL to layout

I VLSI digital design
I MOS transistors: I-V curves
I Gates and interconnects: delay and power
I Circuit netlists: circuit families and static timing
I RTL subsystems: adders, memories, etc.
I CMOS layout and fabrication
I RTL specification with structural Verilog
I Standard cell ASIC design flow
I Design issues and trends

ECE 429 – Introduction to VLSI Design Fall 2010 10/90

Homeworks/Labs/Project

I 5 Homeworks: every other week, usually due in 2 weeks

I 9 Labs: every week, usually due in 1 to 2 weeks
I Check Blackboard for “Lab Report Writing Guide”.
I Final project: two parts, plus oral demonstration
I Late homeworks and lab/project reports will not be graded.
I Submit online in the Assignments section or by paper. We are
NOT going to use digital dropbox.
I Email submissions are NOT recommended and may delay your
grading.
I Email Prof. and TAs 24hrs BEFORE deadlines if you need
more time.

ECE 429 – Introduction to VLSI Design Fall 2010 11/90

ECE UNIX Network for Labs/Project

I Available depending on your registration

I In SH 310A: Mon. 8:35 AM – 11:15 AM, Wed. 8:35 AM –
11:15 AM and 6:25 PM – 9:05 PM
I Remotely: 24 × 7, mandatory for online students,
recommended for main campus students
I Remote lab access
I Check Blackboard for “Remote Lab Access Guide”
I Unix servers currently available: vulcan.ece.iit.edu (the one in
the guide), skew.ece.iit.edu, jupiter.ece.iit.edu,
mercury.ece.iit.edu
I Accounts for most students are activated now.
I Login name: first char of first name + up to 8 chars of last
name
I Password: ss + last four digits of CWID
I Please follow Lab 1 instructions remotely.
I Email me with your fullname and CWID for any login issue.

ECE 429 – Introduction to VLSI Design Fall 2010 12/90

Polices (Very Seriously)

I Discussions on homeworks/labs/projects are encouraged.

I All writings, results, and screen shots should be BY
YOURSELF.
I Figures and tables can be copied with PROPER CITATION.
I All other material in your submissions will be treated as
PLAGIARISM and called for DISCIPLINARY ACTION.
I Check the CODE OF ACADEMIC HONESTY section in the
student handbook for possible consequences.
http://www.iit.edu/student_affairs/handbook/
I NEVER share your documents with others.
I It is not possible to determine WHO COPIES FROM WHOM.
I All parties involved will be subject to punishment.

ECE 429 – Introduction to VLSI Design Fall 2010 13/90

Exams

I Midterm: Thur. 10/14, 6:30 PM – 8:30 PM

I Final exam: Wed. 12/8, 7:30 PM – 9:30 PM
I Closed book/notes, cheat sheet allowed
I Main campus students and Internet students staying at main
campus should take exams in this room.
I Check http://www.iit.edu/registrar/important_
dates/final_exam_schedule.shtml for other issues.
I Makeup exams will NOT be given.

ECE 429 – Introduction to VLSI Design Fall 2010 14/90

Grading

I Percentage
I Homeworks: 2%*5=10%
I Labs 2-9: 3%*8=24%
I Project: 4%+8%+4%=16%
I Exams: 20%+30%=50%
I Class Participation: extra 5%
I Complete all homeworks/labs/project
I Make progress during the semester
I Letter grade
I A: 90
I B: 75
I C: 60
I D (undergraduate only): 55

ECE 429 – Introduction to VLSI Design Fall 2010 15/90

Outline

Administrative Issues

Introduction

Semiconductor Basics

MOS Transistors

Ideal I-V Characteristics

Pulling Up/Down Characteristics

Complementary CMOS Inverter

Back to Reality: Non-Ideal I-V Effects and Noises

ECE 429 – Introduction to VLSI Design Fall 2010 16/90

History

I Vacuum Tube: first 1/2 of 20th century

I Large, expensive, consume a lot of power, unreliable
I Bipolar Transistor: first transistor – 1947
I First integrated circuit – 1957
I More reliable and power-efficient (than vacuum tubes)
I As current is required for operation, limited device density on a
single chip.
I MOSFET: Metal–Oxide–Semiconductor Field–Effect Transistor
I Consume much less power/current than bipolar
I nMOS or pMOS: still consume power when idle
I Intel 4004 – 1971: nMOS process
I CMOS: Complementary Metal–Oxide–Semiconductor
I Gates use both nMOS and pMOS
I Widely adopted since 80s for almost all digital ICs
I Consume negligible power when idle

ECE 429 – Introduction to VLSI Design Fall 2010 17/90

History

I Vacuum Tube: first 1/2 of 20th century

I Large, expensive, consume a lot of power, unreliable
I Bipolar Transistor: first transistor – 1947
I First integrated circuit – 1957
I More reliable and power-efficient (than vacuum tubes)
I As current is required for operation, limited device density on a
single chip.
I MOSFET: Metal–Oxide–Semiconductor Field–Effect Transistor
I Consume much less power/current than bipolar
I nMOS or pMOS: still consume power when idle
I Intel 4004 – 1971: nMOS process
I CMOS: Complementary Metal–Oxide–Semiconductor
I Gates use both nMOS and pMOS
I Widely adopted since 80s for almost all digital ICs
I Consume negligible power when idle

ECE 429 – Introduction to VLSI Design Fall 2010 17/90

History

I Vacuum Tube: first 1/2 of 20th century

I Large, expensive, consume a lot of power, unreliable
I Bipolar Transistor: first transistor – 1947
I First integrated circuit – 1957
I More reliable and power-efficient (than vacuum tubes)
I As current is required for operation, limited device density on a
single chip.
I MOSFET: Metal–Oxide–Semiconductor Field–Effect Transistor
I Consume much less power/current than bipolar
I nMOS or pMOS: still consume power when idle
I Intel 4004 – 1971: nMOS process
I CMOS: Complementary Metal–Oxide–Semiconductor
I Gates use both nMOS and pMOS
I Widely adopted since 80s for almost all digital ICs
I Consume negligible power when idle

ECE 429 – Introduction to VLSI Design Fall 2010 17/90

History

I Vacuum Tube: first 1/2 of 20th century

I Large, expensive, consume a lot of power, unreliable
I Bipolar Transistor: first transistor – 1947
I First integrated circuit – 1957
I More reliable and power-efficient (than vacuum tubes)
I As current is required for operation, limited device density on a
single chip.
I MOSFET: Metal–Oxide–Semiconductor Field–Effect Transistor
I Consume much less power/current than bipolar
I nMOS or pMOS: still consume power when idle
I Intel 4004 – 1971: nMOS process
I CMOS: Complementary Metal–Oxide–Semiconductor
I Gates use both nMOS and pMOS
I Widely adopted since 80s for almost all digital ICs
I Consume negligible power when idle

ECE 429 – Introduction to VLSI Design Fall 2010 17/90

Moore’s Law

Process scaling enables the production of integrated circuits (ICs)

with millions of transistors – the number grows exponentially.

Thereafter, power consumption becomes a bottleneck again.

ECE 429 – Introduction to VLSI Design Fall 2010 18/90

Applications

VLSI chips are essential for digital and mixed-signal systems:

consumer electronics, medical equipments,
networking/communication systems, automobiles, etc.

ECE 429 – Introduction to VLSI Design Fall 2010 19/90

Electronic Design Automation (EDA)

I Design is a must to turn transistors into functional systems.

I Same applies even if VLSI is replaced by some technique in
future.
I Manual design is simply beyond what human beings can
handle for complex systems.
I Trial-and-error approaches won’t work as transistors become
extremely small.
I Very costly (money and time) to manufacture one chip
I When you find a real chip fails, very difficult to tell why.
I Design automation comes to the rescue
I Computer-aided design (CAD) tools not only assist designers
for simulation and debugging but actually define the design
flow.

ECE 429 – Introduction to VLSI Design Fall 2010 20/90

Electronic Design Automation (EDA)

I Design is a must to turn transistors into functional systems.

I Same applies even if VLSI is replaced by some technique in
future.
I Manual design is simply beyond what human beings can
handle for complex systems.
I Trial-and-error approaches won’t work as transistors become
extremely small.
I Very costly (money and time) to manufacture one chip
I When you find a real chip fails, very difficult to tell why.
I Design automation comes to the rescue
I Computer-aided design (CAD) tools not only assist designers
for simulation and debugging but actually define the design
flow.

ECE 429 – Introduction to VLSI Design Fall 2010 20/90

Electronic Design Automation (EDA)

I Design is a must to turn transistors into functional systems.

I Same applies even if VLSI is replaced by some technique in
future.
I Manual design is simply beyond what human beings can
handle for complex systems.
I Trial-and-error approaches won’t work as transistors become
extremely small.
I Very costly (money and time) to manufacture one chip
I When you find a real chip fails, very difficult to tell why.
I Design automation comes to the rescue
I Computer-aided design (CAD) tools not only assist designers
for simulation and debugging but actually define the design
flow.

ECE 429 – Introduction to VLSI Design Fall 2010 20/90

Electronic Design Automation (EDA)

I Design is a must to turn transistors into functional systems.

I Same applies even if VLSI is replaced by some technique in
future.
I Manual design is simply beyond what human beings can
handle for complex systems.
I Trial-and-error approaches won’t work as transistors become
extremely small.
I Very costly (money and time) to manufacture one chip
I When you find a real chip fails, very difficult to tell why.
I Design automation comes to the rescue
I Computer-aided design (CAD) tools not only assist designers
for simulation and debugging but actually define the design
flow.

ECE 429 – Introduction to VLSI Design Fall 2010 20/90

The Whole Picture of System Design (ITRS 2009)

ECE 429 – Introduction to VLSI Design Fall 2010 21/90

Why take this course?

I So is VLSI design as simple as Verilog (or VHDL, etc)

programming with all those CAD tools?
I No: Garbage In, Garbage Out
I You need to specify more than the functionality.
I A chip design shown to be working by a tool is not necessary
working in reality if you cannot provide correct specifications.
I Making further improvements requires to understand the
details of the tool outputs.
I Learn all design aspects besides system functionality in this
course.

ECE 429 – Introduction to VLSI Design Fall 2010 22/90

Why take this course?

I So is VLSI design as simple as Verilog (or VHDL, etc)

programming with all those CAD tools?
I No: Garbage In, Garbage Out
I You need to specify more than the functionality.
I A chip design shown to be working by a tool is not necessary
working in reality if you cannot provide correct specifications.
I Making further improvements requires to understand the
details of the tool outputs.
I Learn all design aspects besides system functionality in this
course.

ECE 429 – Introduction to VLSI Design Fall 2010 22/90

Why take this course?

I So is VLSI design as simple as Verilog (or VHDL, etc)

programming with all those CAD tools?
I No: Garbage In, Garbage Out
I You need to specify more than the functionality.
I A chip design shown to be working by a tool is not necessary
working in reality if you cannot provide correct specifications.
I Making further improvements requires to understand the
details of the tool outputs.
I Learn all design aspects besides system functionality in this
course.

ECE 429 – Introduction to VLSI Design Fall 2010 22/90

Why take this course?

I So is VLSI design as simple as Verilog (or VHDL, etc)

programming with all those CAD tools?
I No: Garbage In, Garbage Out
I You need to specify more than the functionality.
I A chip design shown to be working by a tool is not necessary
working in reality if you cannot provide correct specifications.
I Making further improvements requires to understand the
details of the tool outputs.
I Learn all design aspects besides system functionality in this
course.

ECE 429 – Introduction to VLSI Design Fall 2010 22/90

Challenges in VLSI Design

I System complexity: more functionality within short

time-to-market.
I Silicon complexity: physical effects can no longer be ignored,
e.g., interconnects, power, thermal, process variations,
manufacturability.

ECE 429 – Introduction to VLSI Design Fall 2010 23/90

Challenges in VLSI Design

I System complexity: more functionality within short

time-to-market.
I Silicon complexity: physical effects can no longer be ignored,
e.g., interconnects, power, thermal, process variations,
manufacturability.

ECE 429 – Introduction to VLSI Design Fall 2010 23/90

System Complexity: Mobile Systems (ITRS 2009)

ECE 429 – Introduction to VLSI Design Fall 2010 24/90

System Complexity: Desktops and Servers (ITRS 2009)

ECE 429 – Introduction to VLSI Design Fall 2010 25/90

System Complexity: Cyber-Physical Systems (ITRS 2007)

ECE 429 – Introduction to VLSI Design Fall 2010 26/90

Silicon Complexity: Feature Size (ITRS 2007)

ECE 429 – Introduction to VLSI Design Fall 2010 27/90

Silicon Complexity: Power Density

ECE 429 – Introduction to VLSI Design Fall 2010 28/90

Outline

Administrative Issues

Introduction

Semiconductor Basics

MOS Transistors

Ideal I-V Characteristics

Pulling Up/Down Characteristics

Complementary CMOS Inverter

Back to Reality: Non-Ideal I-V Effects and Noises

ECE 429 – Introduction to VLSI Design Fall 2010 29/90

Silicon Lattice

I Balls: silicon atoms

I Sticks: covalent bonds (Group IV element – 4 per atom)
I Atomic/covalent radius of silicon: 0.111nm
ECE 429 – Introduction to VLSI Design Fall 2010 30/90
Silicon Lattice

I Balls: silicon atoms

I Sticks: covalent bonds (Group IV element – 4 per atom)
I Atomic/covalent radius of silicon: 0.111nm
ECE 429 – Introduction to VLSI Design Fall 2010 30/90
Silicon Lattice

I Shown in plane for ease of drawing

I Poor conductor.
I Improve conductivity by doping impurities.

ECE 429 – Introduction to VLSI Design Fall 2010 31/90

n-type Semiconductor

I Group V dopants: Phosphorus (P), Arsenic (As), etc

I Free electrons as (current) carriers: negetive charge

ECE 429 – Introduction to VLSI Design Fall 2010 32/90

p-type Semiconductor

I Group III dopants: Boron (B), Aluminum (Al), etc

I Holes as carriers: positive charge
I Serve as potential slots for migrating electrons

ECE 429 – Introduction to VLSI Design Fall 2010 33/90

Relevant Semiconductor Structures

I Diode: pn junction
I Gate: utilizing electric field to control current

ECE 429 – Introduction to VLSI Design Fall 2010 34/90

pn Junction – Diode

I Depletion region prevents current flow

ECE 429 – Introduction to VLSI Design Fall 2010 35/90

pn Junction – Forward-bias

I Depletion region shrinks: current flow forms

ECE 429 – Introduction to VLSI Design Fall 2010 36/90

pn Junction – Reverse-bias

I Depletion region widens: no current flow

ECE 429 – Introduction to VLSI Design Fall 2010 37/90

Gate – Accumulation

(Fig 2.2, Weste and Harris, 2005)

ECE 429 – Introduction to VLSI Design Fall 2010 38/90

Gate – Depletion

(Fig 2.2, Weste and Harris, 2005)

I Vt : threshold voltage, depending on

I # dopants in the body
I tox : gate oxide (SiO2 layer below gate) thickness

ECE 429 – Introduction to VLSI Design Fall 2010 39/90

Gate – Inversion

(Fig 2.2, Weste and Harris, 2005)

I Free electrons form a conductive layer.

ECE 429 – Introduction to VLSI Design Fall 2010 40/90

Outline

Administrative Issues

Introduction

Semiconductor Basics

MOS Transistors

Ideal I-V Characteristics

Pulling Up/Down Characteristics

Complementary CMOS Inverter

Back to Reality: Non-Ideal I-V Effects and Noises

ECE 429 – Introduction to VLSI Design Fall 2010 41/90

MOSFET

Metal-Oxide-Semiconductor Field-Effect Transistor

(Weste and Harris, 2005)

Look into theory of nMOS, pMOS is similar.

ECE 429 – Introduction to VLSI Design Fall 2010 42/90

MOSFET

Metal-Oxide-Semiconductor Field-Effect Transistor

(Weste and Harris, 2005)

Look into theory of nMOS, pMOS is similar.

ECE 429 – Introduction to VLSI Design Fall 2010 42/90

nMOS Operation – Cutoff

(Fig 2.3, Weste and Harris, 2005)

I Vgs < Vt
I No channel. Ids = 0

ECE 429 – Introduction to VLSI Design Fall 2010 43/90

nMOS Operation – Linear

(Fig 2.3, Weste and Harris, 2005)

I Vgs = Vgd ⇒ Vds = Vgs − Vgd = 0

I Channel formed. Ids = 0 since Vds = 0
I What happens if we keep Vgs unchanged and increase Vds ?

ECE 429 – Introduction to VLSI Design Fall 2010 44/90

nMOS Operation – Linear

(Fig 2.3, Weste and Harris, 2005)

I Vgs = Vgd ⇒ Vds = Vgs − Vgd = 0

I Channel formed. Ids = 0 since Vds = 0
I What happens if we keep Vgs unchanged and increase Vds ?

ECE 429 – Introduction to VLSI Design Fall 2010 44/90

nMOS Operation – Linear

(Fig 2.3, Weste and Harris, 2005)

I Vgs > Vgd > Vt ⇒

0 = Vgs − Vgs < Vds = Vgs − Vgd < Vgs − Vt
I Channel formed.Ids ↑ when Vds ↑
I Carriers (electrons) move from source to drain.
I What happens if we keep Vgs unchanged and increase Vds
further more?
ECE 429 – Introduction to VLSI Design Fall 2010 45/90
nMOS Operation – Linear

(Fig 2.3, Weste and Harris, 2005)

I Vgs > Vgd > Vt ⇒

0 = Vgs − Vgs < Vds = Vgs − Vgd < Vgs − Vt
I Channel formed.Ids ↑ when Vds ↑
I Carriers (electrons) move from source to drain.
I What happens if we keep Vgs unchanged and increase Vds
further more?
ECE 429 – Introduction to VLSI Design Fall 2010 45/90
nMOS Operation – Linear

(Fig 2.3, Weste and Harris, 2005)

I Vgs > Vgd > Vt ⇒

0 = Vgs − Vgs < Vds = Vgs − Vgd < Vgs − Vt
I Channel formed.Ids ↑ when Vds ↑
I Carriers (electrons) move from source to drain.
I What happens if we keep Vgs unchanged and increase Vds
further more?
ECE 429 – Introduction to VLSI Design Fall 2010 45/90
nMOS Operation – Saturation

(Fig 2.3, Weste and Harris, 2005)

I Vgs > Vt > Vgd ⇒ Vds = Vgs − Vgd > Vgs − Vt

I Channel pinched off. Ids independent of Vds .

ECE 429 – Introduction to VLSI Design Fall 2010 46/90

Outline

Administrative Issues

Introduction

Semiconductor Basics

MOS Transistors

Ideal I-V Characteristics

Pulling Up/Down Characteristics

Complementary CMOS Inverter

Back to Reality: Non-Ideal I-V Effects and Noises

ECE 429 – Introduction to VLSI Design Fall 2010 47/90

How to obtain current (I) - voltage (V) relationship?

I How accurate?
I Shockley first-order model: averaging
I Given voltages at G/D/S, determine the current
I Electrons move in channel

Channel Charge
Current = Time to Cross Channel

ECE 429 – Introduction to VLSI Design Fall 2010 48/90

How to obtain current (I) - voltage (V) relationship?

I How accurate?
I Shockley first-order model: averaging
I Given voltages at G/D/S, determine the current
I Electrons move in channel

Channel Charge
Current = Time to Cross Channel

ECE 429 – Introduction to VLSI Design Fall 2010 48/90

How to obtain current (I) - voltage (V) relationship?

I How accurate?
I Shockley first-order model: averaging
I Given voltages at G/D/S, determine the current
I Electrons move in channel

Channel Charge
Current = Time to Cross Channel

ECE 429 – Introduction to VLSI Design Fall 2010 48/90

nMOS Dimensions

(Weste and Harris, 2005)

ECE 429 – Introduction to VLSI Design Fall 2010 49/90

Channel Charge

Qchannel = Cg (Vgc − Vt )

ox
I Gate to channel capacitance: Cg = tox WL
I Permittivity: ox = 3.90 for SiO2
ox
I Capacitance per unit area for gate oxide: Cox = tox
Vgs +Vgd Vds
I Average gate to channel voltage: Vgc = 2 = Vgs − 2

ECE 429 – Introduction to VLSI Design Fall 2010 50/90

Channel Charge

Qchannel = Cg (Vgc − Vt )

ox
I Gate to channel capacitance: Cg = tox WL
I Permittivity: ox = 3.90 for SiO2
ox
I Capacitance per unit area for gate oxide: Cox = tox
Vgs +Vgd Vds
I Average gate to channel voltage: Vgc = 2 = Vgs − 2

ECE 429 – Introduction to VLSI Design Fall 2010 50/90

Channel Charge

Qchannel = Cg (Vgc − Vt )

ox
I Gate to channel capacitance: Cg = tox WL
I Permittivity: ox = 3.90 for SiO2
ox
I Capacitance per unit area for gate oxide: Cox = tox
Vgs +Vgd Vds
I Average gate to channel voltage: Vgc = 2 = Vgs − 2

ECE 429 – Introduction to VLSI Design Fall 2010 50/90

Time to Cross Channel

L
Time to Cross Channel = v

I Average carrier velocity for linear region: v = µE

I That’s why it is called linear: v ∝ E
I Mobility: µ, assumed to be a constant
I Electric field: E = VLds

ECE 429 – Introduction to VLSI Design Fall 2010 51/90

nMOS Ideal I-V – Linear 0 < Vds < Vgs − Vt

 Vds  L L2
Qchannel = Cox WL Vgs − Vt − and =
2 v µVds
Qchannel W Vds 
⇒ Ids = = µCox Vgs − Vt − Vds
L/v L 2

ECE 429 – Introduction to VLSI Design Fall 2010 52/90

Ideal I-V Parameters

 
Vds
Ids = µCox W
L Vgs − Vt − 2 Vds

I Technology-dependent:
 k0 = µCox
0 W Vds
Ids = k L Vgs − Vt − 2 Vds
I Technology
 and geometry-dependent:
 β = µCox W
L
Ids = β Vgs − Vt − V2ds Vds

ECE 429 – Introduction to VLSI Design Fall 2010 53/90

Ideal I-V Parameters

 
Vds
Ids = µCox W
L Vgs − Vt − 2 Vds

I Technology-dependent:
 k0 = µCox
0 W Vds
Ids = k L Vgs − Vt − 2 Vds
I Technology
 and geometry-dependent:
 β = µCox W
L
Ids = β Vgs − Vt − V2ds Vds

ECE 429 – Introduction to VLSI Design Fall 2010 53/90

nMOS Ideal I-V – Saturation 0 < Vgs − Vt < Vds

I Ids will remain the same as if Vds = Vgs − Vt

µCox W
Ids = (Vgs − Vt )2
2 L
k0 W
= (Vgs − Vt )2
2 L
β
= (Vgs − Vt )2
2

ECE 429 – Introduction to VLSI Design Fall 2010 54/90

nMOS Ideal I-V

I Cutoff: Vgs < Vtn

Ids = 0
I Linear: 0 < Vds < Vgs − Vtn

W Vds 
Ids = µn Cox Vgs − Vtn − Vds
L 2
I Saturation: 0 < Vgs − Vtn < Vds

µn Cox W
Ids = (Vgs − Vtn )2
2 L

ECE 429 – Introduction to VLSI Design Fall 2010 55/90

nMOS Ideal I-V in terms of k 0



 0, if Vgs < Vt , cutoff



  
Vds
Ids = k0 W
L Vgs − Vt − 2 Vds , if 0 < Vds < Vgs − Vt , linear




 k0 W

2
2 L (Vgs − Vt ) , if 0 < Vgs − Vt < Vds , saturation

ECE 429 – Introduction to VLSI Design Fall 2010 56/90

nMOS Ideal I-V in terms of β



 0, if Vgs < Vt , cutoff



  
Ids = β Vgs − Vt − V2ds Vds , if 0 < Vds < Vgs − Vt , linear





 β 2
2 (Vgs − Vt ) , if 0 < Vgs − Vt < Vds , saturation

ECE 429 – Introduction to VLSI Design Fall 2010 57/90

nMOS Ideal I-V Curves

(Weste and Harris, 2005)

ECE 429 – Introduction to VLSI Design Fall 2010 58/90

pMOS Ideal I-V

I Cutoff: Vsg < |Vtp |

Isd = 0
I Linear: 0 < Vsd < Vsg − |Vtp |

W Vsd 
Isd = µp Cox Vsg − |Vtp | − Vsd
L 2
I Saturation: 0 < Vsg − |Vtp | < Vsd

µp Cox W
Isd = (Vsg − |Vtp |)2
2 L

ECE 429 – Introduction to VLSI Design Fall 2010 59/90

Outline

Administrative Issues

Introduction

Semiconductor Basics

MOS Transistors

Ideal I-V Characteristics

Pulling Up/Down Characteristics

Complementary CMOS Inverter

Back to Reality: Non-Ideal I-V Effects and Noises

ECE 429 – Introduction to VLSI Design Fall 2010 60/90

Capacitances and Computational Model

I A capacitor charged to high voltage (usually VDD ) represents

“1”.
I A capacitor discharged to low voltage (usually GND)
represents “0”.
I MOS transistors act as switches to charge/discharge
capacitors.
I Amount of current and capacitances of capacitors determine
speed of circuits.
I Where are the capacitors?

ECE 429 – Introduction to VLSI Design Fall 2010 61/90

MOS Capacitances

I Gate capacitance
ox
Cg = Cox WL = WL
tox
I Parasitic capacitances
I Diodes between source/drain and body
Csb ≈ Cdb ≈ Cg

ECE 429 – Introduction to VLSI Design Fall 2010 62/90

Circuit Analysis: nMOS Pulling Up

I “0” → “1”
I Initially Vs (0) = 0
I Charge in saturation region: Vds = Vgs > Vtn
I Until eventually cutoff when Vgs drops to Vtn
I Vs (∞) = VDD − Vtn : threshold voltage drop

ECE 429 – Introduction to VLSI Design Fall 2010 63/90

Circuit Analysis: nMOS Pulling Up

I “0” → “1”
I Initially Vs (0) = 0
I Charge in saturation region: Vds = Vgs > Vtn
I Until eventually cutoff when Vgs drops to Vtn
I Vs (∞) = VDD − Vtn : threshold voltage drop

ECE 429 – Introduction to VLSI Design Fall 2010 63/90

Circuit Analysis: nMOS Pulling Up

I “0” → “1”
I Initially Vs (0) = 0
I Charge in saturation region: Vds = Vgs > Vtn
I Until eventually cutoff when Vgs drops to Vtn
I Vs (∞) = VDD − Vtn : threshold voltage drop

ECE 429 – Introduction to VLSI Design Fall 2010 63/90

Circuit Analysis: pMOS Pulling Up

I “0” → “1”
I Initially Vd (0) = 0
I Always not cutoff: Vsg = VDD > |Vtp |
I First charge in saturation, then in linear region
I Until Vsd drops to 0
I Vd (∞) = VDD : no threshold voltage drop
I Pull up faster than nMOS

ECE 429 – Introduction to VLSI Design Fall 2010 64/90

Circuit Analysis: pMOS Pulling Up

I “0” → “1”
I Initially Vd (0) = 0
I Always not cutoff: Vsg = VDD > |Vtp |
I First charge in saturation, then in linear region
I Until Vsd drops to 0
I Vd (∞) = VDD : no threshold voltage drop
I Pull up faster than nMOS

ECE 429 – Introduction to VLSI Design Fall 2010 64/90

Circuit Analysis: pMOS Pulling Up

I “0” → “1”
I Initially Vd (0) = 0
I Always not cutoff: Vsg = VDD > |Vtp |
I First charge in saturation, then in linear region
I Until Vsd drops to 0
I Vd (∞) = VDD : no threshold voltage drop
I Pull up faster than nMOS

ECE 429 – Introduction to VLSI Design Fall 2010 64/90

Circuit Analysis: pMOS Pulling Up

I “0” → “1”
I Initially Vd (0) = 0
I Always not cutoff: Vsg = VDD > |Vtp |
I First charge in saturation, then in linear region
I Until Vsd drops to 0
I Vd (∞) = VDD : no threshold voltage drop
I Pull up faster than nMOS

ECE 429 – Introduction to VLSI Design Fall 2010 64/90

Circuit Analysis: nMOS Pulling Down

I “1” → “0”
I Initially Vd (0) = VDD
I Always not cutoff: Vgs = VDD > Vtn
I First discharge in saturation, then in linear region
I Until Vds drops to 0
I Vd (∞) = 0: no threshold voltage drop

ECE 429 – Introduction to VLSI Design Fall 2010 65/90

Circuit Analysis: nMOS Pulling Down

I “1” → “0”
I Initially Vd (0) = VDD
I Always not cutoff: Vgs = VDD > Vtn
I First discharge in saturation, then in linear region
I Until Vds drops to 0
I Vd (∞) = 0: no threshold voltage drop

ECE 429 – Introduction to VLSI Design Fall 2010 65/90

Circuit Analysis: nMOS Pulling Down

I “1” → “0”
I Initially Vd (0) = VDD
I Always not cutoff: Vgs = VDD > Vtn
I First discharge in saturation, then in linear region
I Until Vds drops to 0
I Vd (∞) = 0: no threshold voltage drop

ECE 429 – Introduction to VLSI Design Fall 2010 65/90

Circuit Analysis: pMOS Pulling Down

I “1” → “0”
I Initially Vs (0) = VDD
I Discharge in saturation region: Vsd = Vsg > Vtn
I Until eventually cutoff when Vsg drops to |Vtp |
I Vs (∞) = |Vtp |: threshold voltage drop
I Pull down slower than nMOS

ECE 429 – Introduction to VLSI Design Fall 2010 66/90

Circuit Analysis: pMOS Pulling Down

I “1” → “0”
I Initially Vs (0) = VDD
I Discharge in saturation region: Vsd = Vsg > Vtn
I Until eventually cutoff when Vsg drops to |Vtp |
I Vs (∞) = |Vtp |: threshold voltage drop
I Pull down slower than nMOS

ECE 429 – Introduction to VLSI Design Fall 2010 66/90

Circuit Analysis: pMOS Pulling Down

I “1” → “0”
I Initially Vs (0) = VDD
I Discharge in saturation region: Vsd = Vsg > Vtn
I Until eventually cutoff when Vsg drops to |Vtp |
I Vs (∞) = |Vtp |: threshold voltage drop
I Pull down slower than nMOS

ECE 429 – Introduction to VLSI Design Fall 2010 66/90

Circuit Analysis: pMOS Pulling Down

I “1” → “0”
I Initially Vs (0) = VDD
I Discharge in saturation region: Vsd = Vsg > Vtn
I Until eventually cutoff when Vsg drops to |Vtp |
I Vs (∞) = |Vtp |: threshold voltage drop
I Pull down slower than nMOS

ECE 429 – Introduction to VLSI Design Fall 2010 66/90

Pulling Up and Down

I nMOS is good for pulling down but bad for pulling up

I Slower when pulling up than when pulling down
I pMOS is good for pulling up but bad for pulling down
I Slower when pulling down than when pulling up

ECE 429 – Introduction to VLSI Design Fall 2010 67/90

Outline

Administrative Issues

Introduction

Semiconductor Basics

MOS Transistors

Ideal I-V Characteristics

Pulling Up/Down Characteristics

Complementary CMOS Inverter

Back to Reality: Non-Ideal I-V Effects and Noises

ECE 429 – Introduction to VLSI Design Fall 2010 68/90

Inverter

I Functionality:
I Input “0” then output “1”
I Input “1” then output “0”
I Use VDD to represent “1” and GND to represent “0”
I Recall nMOS is good for pulling down and pMOS is good for
pulling up

ECE 429 – Introduction to VLSI Design Fall 2010 69/90

Complementary CMOS Inverter

Combine the advantage of nMOS and pMOS transistors

ECE 429 – Introduction to VLSI Design Fall 2010 70/90

Static Behavior

I How to obtain Vout as a function of Vin ?

I Solve the equation: Ip = In
I Both Ip and In are functions of Vin and Vout
I Can be solved graphically

ECE 429 – Introduction to VLSI Design Fall 2010 71/90

Static Behavior

I How to obtain Vout as a function of Vin ?

I Solve the equation: Ip = In
I Both Ip and In are functions of Vin and Vout
I Can be solved graphically

ECE 429 – Introduction to VLSI Design Fall 2010 71/90

Static Behavior

I How to obtain Vout as a function of Vin ?

I Solve the equation: Ip = In
I Both Ip and In are functions of Vin and Vout
I Can be solved graphically

ECE 429 – Introduction to VLSI Design Fall 2010 71/90

DC Transfer Characteristics
Assume Vtn ≈ |Vtp | and βn = βp

(Fig. 2.24, Weste and Harris, 2005)

Vin pMOS nMOS Vout

A [0, Vtn ) linear cutoff VDD
B [Vtn , VDD
2
) linear sat. > VDD2
C ≈ VDD2
sat. sat.
D ( VDD
2
, VDD −|Vtp |] sat. linear < VDD
2
E (VDD −|Vtp |, VDD ] cutoff linear 0

ECE 429 – Introduction to VLSI Design Fall 2010 72/90

β Ratio Effects

(Weste and Harris, 2005)

βp
I Change W to adjust βn
β
I HI-skewed inverter ( βpn > 1) requires higher Vin for transition
β
I LO-skewed inverter ( βpn < 1) requires lower Vin for transition

ECE 429 – Introduction to VLSI Design Fall 2010 73/90

Outline

Administrative Issues

Introduction

Semiconductor Basics

MOS Transistors

Ideal I-V Characteristics

Pulling Up/Down Characteristics

Complementary CMOS Inverter

Back to Reality: Non-Ideal I-V Effects and Noises

ECE 429 – Introduction to VLSI Design Fall 2010 74/90

Velocity Saturation

I We assumed v = µE and µ being constant in ideal model.

I However, that is only true when E is small.
I v tends to be smaller at higher E and so does Ids .

(Weste and Harris, 2005)

ECE 429 – Introduction to VLSI Design Fall 2010 75/90

α-Power Law Model for Velocity Saturation

I Velocity saturation index: α

β α
Idsat = Pc (Vgs − Vt )α , Vdsat = Pv (Vgs − Vt ) 2
2
I Linear: when Vds < Vdsat
Vds
Ids = Idsat
Vdsat
I Saturation: when Vds > Vdsat

Ids = Idsat

I For α = 2, similar to ideal model

I Larger E results in smaller α (close to 1)

ECE 429 – Introduction to VLSI Design Fall 2010 76/90

Example of α-Power Law Model

(Weste and Harris, 2005)

ECE 429 – Introduction to VLSI Design Fall 2010 77/90

Channel Length Modulation

I We assumed a fixed channel length L for saturation in ideal

model.
I However, the p-n junction between drain and body is
reverse-biased in saturation region.
I Larger Vds results in shorter effective channel length and then
larger E and Ids .

ECE 429 – Introduction to VLSI Design Fall 2010 78/90

Channel Length Modulation Factor

(Weste and Harris, 2005)

I Empirical channel length modulation factor: λ

I Saturation:
β
Ids = (Vgs − Vt )2 (1 + λVds )
2
ECE 429 – Introduction to VLSI Design Fall 2010 79/90
Body Effect

I Vt is affected by the potential difference Vsb between source

and body.
p p

Vt = Vt0 + γ φs + Vsb − φs

I φs : technology/temperature-dependent parameter
Also check textbook 2.3.3 for the meaning of the parameters
that determine φs
I Designer may alter Vt by changing Vsb

ECE 429 – Introduction to VLSI Design Fall 2010 80/90

Subthreshold Leakage

I Ids 6= 0 for cutoff region (Vgs < Vt )

I Non-zero power consumption even when the transistors are
off.
I Assume Vgs = 0 and Vds = VDD ,
Vt ·q
Ids = Ids0 e − T ·n·k

I Grow exponentially as Vt decreases or T rises

Note Vt decreases as T rises
I Thermal runaway:
High leakage power → high chip temperature → even higher
leakage power and temperature → burn the chip!

ECE 429 – Introduction to VLSI Design Fall 2010 81/90

Gate Leakage

I An atomic layer of SiO2 is about 0.3nm thick

Gate oxide is only a handful of atomic layers thick
I Due to quantum effects, electrons/holes may “tunneling”
through gate oxide, means jumping from one side to the
other, form current and consume power
I Tunneling is an useful feature for flash memory devices: SD
cards, USB keys, SSD drives

ECE 429 – Introduction to VLSI Design Fall 2010 82/90

Current Density for Gate Leakage

(Weste and Harris, 2005)

ECE 429 – Introduction to VLSI Design Fall 2010 83/90
Temperature Dependence

I Thermal runaway: positive feedback among temperature,

threshold voltage, and subthreshold leakage
I Carrier mobility improves as temperature drops
I Chip reliability improves as temperature drops
I Thermal variations over chip may affect transistor
characteristics unevenly

ECE 429 – Introduction to VLSI Design Fall 2010 84/90

Process Variations

I Though transistors can be fabricated quite precisely as

designed, at such small feature size now, variations could be
quite significant.
I Variations in geometry: W and L
I Variations in doping: Vt

ECE 429 – Introduction to VLSI Design Fall 2010 85/90

Noise

I Perfect “0” and “1” are 0 and VDD respectively

I However, noise may result in non-perfect “0” and “1”s, e.g.
I Supply voltage seen at pMOS source can be less than VDD
I Ground seen at nMOS source can be greater than 0
I Noise may be propagated and amplified

ECE 429 – Introduction to VLSI Design Fall 2010 86/90

Non-Perfect Input/Output

I Non-perfect “0” to “1”

I VIL : maximum voltage for “0” at input
I VOH : minimum voltage for “1” at output
I If input is at most VIL , output should be at least VOH
I Non-perfect “1” to “0”
I VIH : minimum voltage for “1” at input
I VOL : maximum voltage for “0” at output
I If input is at least VIH , output should be at most VOL

ECE 429 – Introduction to VLSI Design Fall 2010 87/90

Non-Perfect Input/Output

I Non-perfect “0” to “1”

I VIL : maximum voltage for “0” at input
I VOH : minimum voltage for “1” at output
I If input is at most VIL , output should be at least VOH
I Non-perfect “1” to “0”
I VIH : minimum voltage for “1” at input
I VOL : maximum voltage for “0” at output
I If input is at least VIH , output should be at most VOL

ECE 429 – Introduction to VLSI Design Fall 2010 87/90

Noise Margin

(Weste and Harris, 2005)

I Fluctuation in input voltages should result in smaller

fluctuation in output voltages to avoid noise amplification
I VIL /VOH and VOL /VIH are the unity gain points, i.e. with
slope= −1, on the DC transfer curve
ECE 429 – Introduction to VLSI Design Fall 2010 88/90
Noise Margin Definition

I Since outputs will be used as inputs for next stage,

VOH > VIH , and VOL < VIL

I Use noise margin to capture the amount of the difference,

NMH = VOH − VIH , and NML = VIL − VOL

I Inverters usually have βn = βp to achieve NMH = NML

I Circuits with larger noise margin are less affected by noise,
though could be slower.

ECE 429 – Introduction to VLSI Design Fall 2010 89/90

Summary

I Know what to learn in this course

I Ideal MOSFET operations
I The first CMOS gate: inverter
I Non-Ideal I-V effects and noises

ECE 429 – Introduction to VLSI Design Fall 2010 90/90