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DATA SHEET
TDA1305T
Stereo 1fs data input up-sampling
filter with bitstream continuous dual
DAC (BCC-DAC2)
Preliminary specification 1995 Dec 08
Supersedes data of September 1994
File under Integrated Circuits, IC01
Philips Semiconductors Preliminary specification
FEATURES
• Easy application
• 16fs Finite-duration Impulse-Response (FIR)
filter incorporated
• Selectable system clock (fsys) 256fs or 384fs
• I2S-bus serial input format (at fsys = 256fs) or LSB fixed
16, 18 or 20 bits serial input mode (at fsys = 384fs)
• Slave-mode clock system
• Cascaded 4-stage digital filter incorporating 2-stage FIR bitstream converter for low signals while large signals are
filter, linear interpolator and sample-and-hold generated using the dynamic continuous calibration
technique, thus resulting in low power consumption, small
• Smoothed transitions before and after muting chip size and easy application.
(soft mute)
The TDA1305T is a dual CMOS DAC with up-sampling
• Digital de-emphasis filter for three sampling rates of
filter and noise shaper. The combination of high
32 kHz, 44.1 kHz and 48 kHz
oversampling up to 16fs, 2nd order noise shaping and
• 12 dB attenuation via the attenuation input control continuous calibration conversion ensures that only simple
• Double speed mode 1st order analog post filtering is required.
• 2nd order noise shaper The TDA1305T supports the I2S-bus data input mode with
• 96 (fsys = 384fs) or 128 (fsys = 256fs) times oversampling word lengths of up to 20 bits (at fsys = 256fs) and the LSB
in normal speed mode fixed serial data input format with word lengths of 16, 18
and 20 bits (at fsys = 384fs). Four cascaded FIR filters
• 48 (fsys = 384fs) or 64 (fsys = 256fs) times oversampling
increase the oversampling rate to 16 times. A
in double speed mode
sample-and-hold function increases the oversampling rate
• Bitstream continuous calibration concept to 96 times (fsys = 384fs) or 128 times (fsys = 256fs). A
• Small outline SO28 package 2nd order noise shaper converts this oversampled data to
• Voltage output 1.5 V (RMS) at line drive level a bitstream for the 5-bit DACs.
• Low total harmonic distortion The DACs are of the continuous calibration type and
incorporate a special date coding. This ensures an
• No zero crossing distortion
extremely high signal-to-noise ratio, superior dynamic
• Inherently monotonic range and immunity to process variation and component
• No analog post filtering required ageing.
• Superior signal-to-noise ratio Two on-board operational amplifiers convert the
• Wide dynamic range (18-bit) digital-to-analog current to an output voltage. Externally
connected capacitors perform the required 1st order
• Single rail supply (3.4 to 5.5 V).
filtering so that no further post filtering is required.
The unique combination of bitstream and continuous
GENERAL DESCRIPTION
calibration techniques, together with a high degree of
The TDA1305T is a new generation of filter-DAC which analog and digital integration, results in a single filter-DAC
features a unique combination of bitstream and continuous with 18-bit dynamic range, high linearity and simple low
calibration techniques. The converter functions as a cost application.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
TDA1305T SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1
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Philips Semiconductors Preliminary specification
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Philips Semiconductors Preliminary specification
BLOCK DIAGRAM
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Philips Semiconductors Preliminary specification
PINNING
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Philips Semiconductors Preliminary specification
FUNCTIONAL DESCRIPTION provide a system clock of 256 or 384fs (fs = 32, 44.1 or
48 kHz). The system frequency is selectable by means of
The TDA1305T CMOS digital-to-analog bitstream
pin CLKS1 and pin CLKS2. The SYSCLKO output (pin 16)
converter incorporates an up-sampling filter and noise
provides the system clock for external use.
shaper which increase the oversampling rate of 1fs input
data to 96fs (fsys = 192fs) or 128fs (fsys = 256fs) in the The TDA1305T supports the following data input modes:
normal speed mode. In the double speed mode the • I2S-bus with data word lengths of up to 20 bits
oversample rate of 1fs input data is increased to 48fs (at fsys = 256fs).
(fsys = 384fs) or 64fs (fsys = 256fs). This oversampling,
• LSB fixed serial format with data word lengths of 16, 18
together with the 5-bit DAC, enables the filtering required
and 20 bits (at fsys = 384fs). As this format idles on the
for waveform smoothing and out-of-band noise reduction
MSB it is necessary to know how many bits are being
to be achieved by simple 1st order analog post filtering.
transmitted.
System clock and data input format The input format is shown in Fig.3. Left and right
data-channel words are time-multiplexed.
The TDA1305T accommodates slave mode only, this
means that in all applications the system devices must
Note
1. Number of clock pulses within half an audio sample.
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Philips Semiconductors Preliminary specification
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Philips Semiconductors Preliminary specification
1995 Dec 08 8
Philips Semiconductors Preliminary specification
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDDD digital supply voltage − 7.0 V
VDDA analog supply voltage − 7.0 V
VDDO operational amplifier supply voltage − 7.0 V
Txtal maximum crystal temperature − +150 °C
Tstg storage temperature −65 +150 °C
Tamb ambient operating temperature −30 +85 °C
Ves electrostatic handling note 1 −2000 +2000 V
note 2 −200 +200 V
Notes
1. Human body model; C = 100 pF, R = 1500 Ω, V = 2000 V, 3 pulses positive and 3 pulses negative.
2. Machine model; C = 200 pF, R = 10 Ω, L = 0.5 µH.
THERMAL CHARACTERISTICS
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Philips Semiconductors Preliminary specification
QUALITY SPECIFICATION
In accordance with “SNW-FQ-611E”. The number of this quality specification can be found in the “Quality Reference
Handbook”. The handbook can be ordered using the code 9398 510 63011.
DIGITAL CHARACTERISTICS
VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = −40 to +85 °C; unless otherwise specified.
1995 Dec 08 10
Philips Semiconductors Preliminary specification
ANALOG CHARACTERISTICS
VDD = VDDA = VDDO = 5 V; VSS = 0 V; Tamb = 25 °C; unless otherwise specified.
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Philips Semiconductors Preliminary specification
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Philips Semiconductors Preliminary specification
Double-speed characteristics
Table 5 Double-speed filter characteristics.
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Philips Semiconductors Preliminary specification
APPLICATION INFORMATION
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Philips Semiconductors Preliminary specification
A typical application diagram is illustrated in Fig.5. The left measurement values of a small amount of engineering
and right channel outputs can drive a line output directly. samples. No guarantee for typical values is implied.
The series inductor (L) in the digital supply line, though not
In Fig.6 measurements were taken with an 18-bit sine
strictly necessary, helps to reduce crosstalk between the
wave generated at a sampling rate of 48 kHz. The
digital and analog circuits.
(THD + N)/S was measured over a bandwidth of
In Fig.6 measurements were taken with an 18-bit sine 20 Hz to 20 kHz and filtered with A-weighted
wave generated at a sampling rate of 48 kHz. The characteristics. The graph was constructed from average
(THD + N)/S was measured over a bandwidth of measurement values of a small amount of engineering
20 Hz to 20 kHz. The graph was constructed from average samples. No guarantee for typical values is implied.
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Philips Semiconductors Preliminary specification
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Philips Semiconductors Preliminary specification
PACKAGE OUTLINE
SO28: plastic small outline package; 28 leads; body width 7.5 mm SOT136-1
D E A
y HE v M A
28 15
Q
A2 A
A1 (A 3)
pin 1 index
θ
Lp
L
1 14 detail X
e w M
bp
0 5 10 mm
scale
0.30 2.45 0.49 0.32 18.1 7.6 10.65 1.1 1.1 0.9
mm 2.65 0.25 1.27 1.4 0.25 0.25 0.1
0.10 2.25 0.36 0.23 17.7 7.4 10.00 0.4 1.0 0.4 8o
0.012 0.096 0.019 0.013 0.71 0.30 0.42 0.043 0.043 0.035 0o
inches 0.10 0.01 0.050 0.055 0.01 0.01 0.004
0.004 0.089 0.014 0.009 0.69 0.29 0.39 0.016 0.039 0.016
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
91-08-13
SOT136-1 075E06 MS-013AE
95-01-24
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Philips Semiconductors Preliminary specification
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Philips Semiconductors Preliminary specification
DEFINITIONS
1995 Dec 08 19
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