Proceeding of the IEEE 28th

Canadian Conference on Electrical and Computer Engineering

Halifax, Canada, May 3-6, 2015

Design of a 50nW , 0.5VDD Sub-Threshold OTA Amplifier with Indirect

Compensation Technique and Class AB Output Stage
Ranga Babu Ganta
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal,India
Email: rangababu.ganta@gmail.com
Mengye Cai, Kyle Fricke and Robert Sobot
School of Electrical and Computer Engineering
Western University
London, Ontario, Canada
Email: (mcai9, kfricke, rsobot)@uwo.ca

Abstract— We present analysis and design of a 0.5VDD two

stage OTA amplifier with current-buffer compensation and class
AB output stage in 90nm CMOS technology. All transistors
in the amplifier operate in the sub-threshold region while
achieving 86dB DC gain and unity gain frequency 40.5kHz


with a load capacitor of 30pF. The total power dissipation is
50nW with bias current of 10nA.

I. I NTRODUCTION
Operational amplifiers (op-amp) circuits are commonly
used in the analog front-end of implantable medical telemetry


and other low-power consumption systems where it is critical 

 
      
to reduce power consumption in order to extend the system’s
operational lifetime [1]. An obvious and efficient method to
reduce power consumption is to lower the associated power
supply voltage, however, this approach creates significant
challenges in the design of the analog circuits [2] as the
available signal voltage swing reduces. To address the issue,
various methods are proposed for the design of low-power
analog sub-blocks, e.g. op-amps. For instance, one can re-
duce the threshold voltage (Vth ) of each transistor by basing
the body terminal at a specific point, thus lower Vth [3]; or,
alternatively use the lower gmb of the input transistor body
terminal rather than the higher gm of gate terminal in order
to avoid the Vth barrier [4].
Based on designs reported in literature, the use of transis-
tors biased in the sub-threshold region appears to be more
efficient approach. However, in this region, the op-amp’s
compensation technique and output stages play critical roles
in the overall performance and power-consumption of the
analog block. Since the classical Miller compensation tech-
nique employs a nulling resistor that, when this technique
is used in the sub-threshold region, becomes very large [5],
the indirect compensation method is developed in [6], [7]. In
both cases, however, all transistors are biased in saturation.
At the same time, a typical op-amp employs a Class AB
output, which is essential for driving heavy capacitive loads.
Nevertheless, in sub-threshold designs Class A output stages
are more common due to their lower biasing current [2].
However, this approach leads to reduced slew rate (SR),
which further impacts the op-amp’s performance.
In this work, we address the above issues and show design
of a two-stage op-amp with all transistors biased in the sub-
threshold region while, in order to remove the large nulling
432
978-1-4799-5829-0/15/$31.00 ©2015 IEEE
    ! 
  
Fig. 1. Relationship between log ID versus Vgb with inversion regions
shown (Weak, Moderate, Strong.)
resistor, the indirect method (i.e. current buffer compensation
loop) is applied rather than the classic compensation method.
Finally, a Class AB output stage is used to improve the op-
amp’s slew rate. The overall result is the increased gain and
reduced power consumption of the amplifier.
The rest of the paper is organized as follows. In Section II
a brief background theory of MOSFET sub-threshold region
is presented; in Section III the design details of the sub-
threshold two stage op-amp are outlined. Conclusions are in
Section IV.
II. MOS TRANSISTOR IN SUB - THRESHOLD
In the sub-threshold region, the inversion charge Q
changes with gate voltage (VG ), Fig. 1. The value of sub-
threshold slope parameter m and process parameter I0 ,
which are functions of technology and temperature, are
calculated as
 
W Vgs −Vth
−
Vds W Vgs −Vth
Id = I0 e mVT 1−e VT
 I0 e mVT (1)
L L
Generally, the value of |Vgb − Vth | should be a minimum
of 50mV in order to keep the transistor in weak inversion
of the sub-threshold region, Fig. 1. Since the substrate is
weakly doped, there are not enough charges in the channel
 TABLE I VDD Input Stage Biasing Compensation Class AB
for output Stage Output Stage
S UBTHRESHOLD PARAMETERS FOR NMOS AND PMOS TRANSISTORS
IN 90nm CMOS PROCESS (W/L = 4μm/2μm) M12 M8 M9 M6
M3 M4

Vth0 (mV) Io (nA) m Vin-

M1 M2
Vin+ MC
CC
CL
IRef VP
NMOS 136 34 2.5
M5 M13 M7
PMOS 227.5 60 3.5 MBias M10 M11

that form the electric field to pull electrons from the source Fig. 2. Schematic diagram of sub-threshold Two-Stage op-amp with
to drain, thus the current flows by diffusion, not drift. indirect compensation (current buffer) and class AB output stage.
In the sub-threshold saturation region the drain to source
  
current Id of the NMOS transistor, when Vds > 4VT 0 , is
given by (1), that is to say, in this region transistor behaves
as a voltage controlled current source. The transconductance
   

   
gm and drain-source resistance rd are derived by (2) and   

(3). The specific NMOS and PMOS sub-threshold process

parameters for W/L = 4μm/2μm are given in Table I.

∂ID ID
gm = = (2) Fig. 3. Proposed Two-Stage op-amp Small Signal Model
∂Vgs mVT
 −1
∂ID mVT
rd = = (3) uration. Thus, the nulling resistance r0 required to cancel
∂Vds λID
the right half plane (RHP) zero in a two-stage op-amp that
In the following section we present design and simulation is Miller compensated should be greater than
results of a two-stage op-amp with indirect compensation
1
(current buffer) and Class AB output stage, Fig. 2. r0 > (6)
Gm2
III. T WO S TAGE OP - AMP D ESIGN where Gm2 is the effective transconductance of second
The proposed two-stage op-amp contains a differential stage, which then becomes in the order of MΩ [2]. This
input stage, compensation stage, and a class AB output stage, large resistance value is rather difficult to achieve in IC
Fig. 2. We adopted the design methodologies in [8], [9] for technology as it drastically increases the circuit area, in
the design of a two-stage op-amp, while the DC gain of the addition to its increased sensitivity to temperature variations.
two-stage op-amp is based on equation (4). Due to the fact For example, a 1MΩ polysilicon resistor in 90nm technology
that transistor length is inversely proportional to λ length of is approximately 25μm by 100μm large and typically has
NMOS and PMOS transistors is modified to adjust the gain a ±30% variation over temperature and process variations,
Av of the two-stage op-amp (5). which makes it is not suitable for applications in low-power
sub-threshold circuits.
   
rd1 rd6 A more suitable approach to cancel the RHP zero is to
Av = gm1 gm6
rd3 rd7 use the indirect compensation method, new pole and zero
1 1 location are summarized in Table (II) [7]. The non-dominant
= (4) pole P2 of the indirect compensation method moves farther
mVT (λ1 + λ3 )(λ6 + λ7 )
away by a factor of approximately CC /C1 over the non-
dominant pole of the Miller compensation method.
To achieve better frequency response, the parasitic ca-
1 pacitance at the output of the first stage (C1 ) should be
Av ∝ (5)
1 1 minimized, i.e., Cgs of M6 , Fig. 2, can be minimized by
+
LP LN the reduction in channel length. However, the channel length
In addition, the small-signal model of the proposed two- of the output transistors also effects the DC gain of the
stage op-amp is shown, Fig. 3, where Gm1 the effective input op-amp, thus a trade-off must occur between these two
stage transconductance, gmc is transistor MC ’s transconduc- specifications. The indirect compensation method of pole
tance and gm6 is M6 ’s transconductance. splitting and zero relocating allows only transistors to be
used for compensation rather than the large (MΩ) nulling
A. Indirect Compensation resistor.
When a transistor operates in sub-threshold region, its In order to demonstrate this compensation method in
transconductance (gm ) value is much smaller than in sat- the context of the designed 0.5V two-stage op-amp, we

433
 TABLE II
100
a) P OLES AND ZERO LOCATION
80 b)

60 Miller Compensation Indirect Compensation

40
1 1
− −
Magnitude [dB]

Dominant Pole
20 Gm2 R1 R2 CC Gm2 R1 R2 Cc
0 −Gm2 Gm2 Cc
Second Pole −
-20 C L + C1 C1 C L
-40 1 gmc
Zero Location −
-60 1 CC
( − Rz )Cc
Gm2
-80

-100
1 10 100 1000 104 105 106 107 108 109
Freq, [Hz] 360
a)
b)
Fig. 4. Simulated frequency response of two different compensation 340
methods: (a) Miller compensation (with a 6MΩ resistance) and (b) Indirect
compensation
320

Voltage, [mV]
0
a) 300
b)
-50
280
-100

-150 260
Degree [°]

-200
240
0 100 200 300 400 500 600 700 800
-250
Time, [μs]

-300
Fig. 6. Slew Rate comparison between (a) Class A and (b) Class AB
-350 output stages.

-400
1 10 100 1000 104 105 106
Freq, [Hz]
Fig. 5. Simulated phase response of two different compensation methods:
(a) Miller compensation (with a 6MΩ resistance) and (b) Indirect compen-
sation.
show comparison between the indirect and Miller-nulling
resistance. The frequency and phase response of each com-
pensation technique is shown in Fig. 4 and Fig. 5, where
a 6MΩ nulling resistor is used in order to realize a similar
frequency-phase response. Meanwhile, common mode reject
ratio(CMRR) is 76dB, Fig. 7.
B. Class AB Output
To reduce the power consumption when operating in sub-
threshold region with a small gm value, current in each
branch is set to a low value (IREF = 10nA in this design).
Consequently, this limited branch current effects the slew
rate of the op-amp. The rising (SR+ ) and falling (SR− )
edge slew rates are calculated as
IREF
SR+ = ; and SR− =
CC CC + CL
which is reduced when there is a large load capacitance CL
connected. To improve the negative slew rate, we propose to
use the Class AB output stage rather than the traditional
Class A output stage, Fig. 2. After that modification, an
additional advantage of the proposes architecture is that the
107 108 109
effective Gm2 increases from gm6 to gm6 +gm7 , [11]. This
additional advantage allows for a reduction in power con-
sumption by reducing the output branch current. Typically,
the power consumption remains the same with an increase
in negative slew rate. A slew rate comparison between the
designed op-amp connected in unity gain negative feedback
with a Class A and Class AB output stage, with the same
compensation method is shown in Fig. 6, and the frequency
and phase response of the designed op-amp are shown in
Fig. 4 and Fig. 5. In addition, CMRR of the designed op-
amp in shown in Fig. 7.
Complete op-amp specifications along with a compari-
son to other published works is summarized in Table III.
As expected, GBW product and slew-rate of our design
are increased while power consumption is decreased in
comparison with similar designs. At the same time, for
example, work [4] demonstrates that very wide bandwidth
0.5V design is achieved at the cost of somewhat lower
load and appropriately increased power consumption and
the respective slew-rate. We should emphasize that by no
I7
(7) means one op-amp is considered “better” or “worse” than
the other, simply because there is no meaningful way to
create a unified all inclusive FOM for op-amps, when each
op-amp is designed and optimized for a specific application,
which in return demands that one or two of its parameters are
given preferred status at expense of the others and therefore
completely skew any FOM attempt. Our goal is to design an

434
 TABLE III
C OMPARISON OF P UBLISHED W ORKS

This Work [2] [10] [4]

Gain [dB] 86 70 69.4 62
GBW [kHz] 40.5 18 11 10,000
Phase Margin [deg] 72 55 65 60
Cload [pF] 30 30 15 20
Power [nW ] 50 75 540 75,000
SR+ [mV/μs] 14 3 15 2,000
SR- [mV/μs] 11 — — —
CMRR [dB] 75 — 74.5 —
ICMR [V] 0.18 - 0.40 — — —
Output Swing [V] 0.3 0.3 0.6 —
Supply Voltage [V] 0.5 0.5 0.6 0.5
Region of operation subthreshold subthreshold subthreshold bulk-driven saturation body-bias

 V. ACKNOWLEDGMENTS
 The authors would like to express their sincere gratitude
to Transonic Scisense Inc., NSERC, OCE, CFI and CMC

Microsystems for supporting our research and for providing
the design technology.














 [3] L. H. Ferreira, T. C. Pimenta, and R. L. Moreno, “An ultra-low-voltage
Fig. 7. Common Mode Reject Ratio
op-amp with ultra-low power consumption that is suitable for
analog signal processing in implantable telemetry systems.
IV. C ONCLUSION
In this work, an example design of a 50nW sub-threshold
op-amp with GBW = 40.5kHz and VDD = 0.5V is given.
Combination of the current buffer compensation loop and
class AB output stage are adopted to realize a better phase
margin and to improve the negative slew rate. In addition,
the integrated circuit area is reduced by the removal of the
nulling resistor. A comparison with several published works
that also operate on a 0.5V supply and in sub-threshold
shows that this work is comparable. The proposed design
consumes the least power with higher gain bandwidth, phase
margin and slew rate. With the achieved reduction in power
consumption, this op-amp design is well suited for long-
term implantable devices in various bio-medical applications
where the power consumption is one of the major constrains.
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