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(AUTONOMOUS)
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING
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Day/Time 09:30 10:20 11:10 12:00 01:30 02:20 03:10
10:20 11:10 12:00 12:50 02:20 03:10 04:00
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*- SEMINAR
B.Tech. IV year First Semester, Academic Year: 2018-19
LIST OF EXPERIMENTS
2. Fault Analysis – I
LG Fault
LL Fault
3. Fault Analysis – II
LLG Fault
LLLG Fault
10.Develop a Simulink model for a single area load frequency control problem
CHADALAWADA RAMANAMMA ENGINEERING COLLEGE, TIRUPATI
(AUTONOMOUS)
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING
LESSON PLAN
Date
Actual
Lecture (As per
Topics to be covered Date of Remarks
No. Academic
completion
calendar)
Date
Actual
Lecture (As per
Topics to be covered Date of Remarks
No. Academic
completion
calendar)