A Novel FPGA-based LVDT Signal Conditioner
Kumardeb Banerjee, Bivas Dam, Kalyan Majumdar
Dept. of Instrumentation & Electronics Engineering
Jadavpur University, Salt Lake Campus
Kolkata, India, PIN - 700098
kdb@iee.jusl.ac.in
Abstract — This paper presents a phase compensated novel
signal conditioner for a linear variable differential transformer
(LVDT) and its FPGA based implementation. The LVDT output
signal is a double-sideband suppressed-carrier amplitude-
modulated (DSB-SC-AM) waveform, where the LVDT sinusoidal
excitation is the carrier signal and the LVDT core position is the
modulating signal. The proposed signal conditioner locates the
carrier peaks in the LVDT output signal and provides a direct
digital demodulation of the same at the said instants. Since the
carrier component at the sampling instants equals the carrier
amplitude, a simple gain scaling converts the read data to the
LVDT core position measurement. The peak sensitive
demodulation is insensitive to sensor induced phase lag and does
not require external phase compensation network. This
conditioner has better dynamic response than existing LVDT
signal conditioners. Its overall error figures are also comparable
with those of the existing solutions.
Keywords: Linear variable differential transformer; signal
conditioner; FPGA based implementation; direct digital
demodulation; peak sensitive demodulation.
I. INTRODUCTION
The LVDT is a displacement sensor that gives an accurate
measurement of position. Detailed description of an LVDT and
its operation can be found in [1-2]. Commercially available
LVDTs are either the 4-wire type or the 5-wire type and work
with a primary excitation that varies from a few kHz (iron
core) to hundreds of kHz (ferrite core).
There are two existing and well documented approaches
for LVDT signal conditioning – the ratio-based method [3] and
the synchronous demodulation method [4]. The ratio-based
method directly computes position as the ratio of the LVDT
secondary output and input primary excitation. However,
ratio-based methods are inherently noisy and in case there is a
sensor induced phase lag in the secondary differential
waveform, the secondary to primary ratio does not give an
exact measure of position, and a phase correction becomes
mandatory to produce the correct output. The strength of this
method is that the measurement is insensitive to the variations
in the amplitude of the primary excitation.
The second approach applies the standard phase-sensitive
demodulation technique to the LVDT secondary output, a
double-sideband suppressed-carrier amplitude modulated
(DSB-SC-AM) waveform. Various well documented variants
of the synchronous demodulation technique are available but
the more popular variant is the in-phase/quadrature (I/Q)
synchronous demodulator [5]. The work in [6] reports a DSP-
based implementation of a typical I/Q demodulator for LVDT
signal conditioning. The scheme accommodates both 4-wire
and 5-wire LVDTs, is insensitive to sensor induced phase
errors, and its performance is comparable with the
commercially available LVDT signal conditioner ICs.
However, this scheme necessitates the use of high
performance floating point DSPs, and hence, may not be
commercially viable for single channel LVDT signal
conditioning. The DSP-based approach reported in [7] and the
implementation of a multi-channel DSP-based Instrument for
displacement measurement using differential variable
reluctance transducers (DVRT) reported in [8], both use
spectral estimation technique to estimate sensor primary and
secondary amplitudes. The final position measurement is
obtained from ration of the two. However, spectral estimation
technique works with a large number of signal samples,
thereby compromising the system bandwidth. The work
reported in [9] uses a system-on-chip microcontroller
MSP43OF149 from Texas Instruments to build a precision
LVDT signal conditioner. However, driving the LVDT primary
winding with a square wave necessitates incorporation of
additional filter chains to suppress the higher harmonics.
It is also worth noting the salient features of the two
commercially available monolithic LVDT signal conditioners -
AD598 and AD698 from Analog Devices. The AD598 and
AD698 employ the ratio-based method and their
implementation details are documented in their respective
datasheets [10-11]. Both implementations generate a low
distortion primary excitation that varies from 20 Hz to 20 kHz,
and generates a dc voltage proportional to the LVDT core
position. The AD598 works only with 5-wire LVDTs and is
insensitive to sensor induced phase errors. The AD698 can
work with both 4-wire and 5-wire LVDTs. However, it
requires external RC network to eliminate sensor induced
phase lag.
In this paper we propose a robust phase-compensated
LVDT signal conditioner that implements a modified
homodyne detector that carries out a phase compensated
synchronous demodulation of the LVDT secondary differential
output. The proposed scheme implements a direct digitization
of the DSB-SC-AM output at the carrier peaks, as seen in the
LVDT output signal. This makes the process insensitive to
sensor induced phase lags and less hardware intensive than
existing solutions. An FPGA-based prototype of the proposed
signal conditioner is also implemented and tested on a standard
test bench. The results show linearity and bandwidth figures
comparable with existing commercial solutions.
II. THE PROPOSED LVDT SIGNAL CONDITIONER
A. Principle of operation
The proposed LVDT signal conditioner implements a
modified version of the standard synchronous demodulator that
eliminates the necessity of implementing multipliers, low pass
filters (LPFs), and subsequent signal processing for the
extraction of the core position. The basic idea behind the
proposed demodulation scheme is based on a technique
reported in [12].
The proposed demodulation scheme implements a carrier
peak synchronous direct readout method. At any instant of
time, the LVDT secondary output, a DSB-SC-AM waveform is
the product of the instantaneous values of the carrier signal and
the modulating signal. If the waveform is read at the carrier
peaks, as seen in the modulated signal, the carrier component is
simply its amplitude that can be removed by appropriate
scaling of the read data. Moreover, this readout mechanism
also eliminates the phase error that creeps in due to phase
mismatch between the carrier and the modulated signals. To
instrument this, one has to identify the carrier-peaks in the
modulated signal, read the modulated signal at the said instants
and scale them properly to remove the carrier amplitude
component. The final output is thus the modulating signal, read
at the carrier-peaks in the modulated signal.
However, the following features need to be embedded in
the said demodulator to ensure an error-free peak synchronous
demodulation:
• The LVDT secondary output is first converted to a
digital pulse train for subsequent signal conditioning
by comparators with built-in hysteresis. High level
noise glitches present in the sensor output, however,
generates short duration pulses at the output of the
comparator. These noise pulses may corrupt the peak-
detection mechanism and hence must be filtered out.
• The LVDT secondary output signal, read at the carrier
peaks, needs to the scaled. Since the scaling factor is
proportional to the amplitude of the primary
excitation, a tight tracking of the same is essential to
maintain measurement accuracy and repeatability.
• The proposed demodulator regenerates the primary
excitation from the modulated signal. Moreover, it
requires a periodic updating of the process to track
any drift in the frequency of the same. If the LVDT
core is at the null position, the secondary differential
voltage is zero. Hence, if the peak detection process of
the carrier, as seen in the modulated signal, is initiated
at this time, it fails. A watch-dog mechanism is thus
necessary that, during start-up, will start the said
process only after sensing a non-zero LVDT output
and will hold the last period data if the same incident
occurs during periodic updating of the same.
Fig. 1: Functional block diagram of the proposed LVDT signal conditioner.
The proposed LVDT signal conditioner first converts the
LVDT output to an equivalent digital pulse train, the modulated
pulse train. As the primary excitation is available locally, a
carrier pulse train, coherent with the primary excitation, is
generated. Both pulse trains are then passed through two
identical digital noise filters (DNFs). The filters remove noise
glitches from the pulse trains but add some time lag, Tf, to
each. Next, to ascertain the phase mismatch between the carrier
and the modulated pulse trains, it measures the time lags, Td1
and Td2, between the rising edge of the filtered carrier pulse
train and the subsequent rising and falling edges of the filtered
modulated pulse train, and computes Td, the minimum of Td1
and Td2. In DSB-SC-AM waveforms, whenever the modulating
signal becomes negative, the carrier component in the
modulated signal suffers a phase inversion. In such cases, for
the filtered modulated pulse train, the falling edge precedes the
rising edge. Therefore, finding the minimum between the two
time lags ensures a correct measure of the LVDT primary to
secondary phase lag. It then generates a quadrature pulse train
with a period that equals Tc, the carrier signal time period, with
rising edges delayed by (Td + Tc /4 – Tf) from the
corresponding rising edges of the filtered carrier pulse train. A
delay of Td from the carrier rising edge finds the corresponding
carrier edge in the LVDT output signal. A further delay of (Tc /4
– Tf) finds the corresponding carrier peak, as seen in the LVDT
output signal. The LVDT output signal, if sampled and
digitized at the rising edges of the said quadrature pulse-train,
gives a direct digital read-out of the LVDT core position with
correct sign.
B. Design Overview
Fig. 1 illustrates a functional block diagram of the
proposed LVDT signal conditioner. The outer section consists
of an analog front-end hardware necessary for sensor
interfacing. The inner core is the block level implementation
of the proposed demodulator along with a serial interface for
uploading the measurement data to a host processor. The
sensor interface section consists of a digital to analog
converter (DAC) driven by SW, the output of the
SW_GENERATOR block that uses direct digital synthesis
(DDS) technique [13] to implement a sinusoidal waveform.
The output of the DAC is the LVDT primary excitation signal.
The SW is a 12-bit sine data in 2’s compliment form. The MSB
of SW is buffered and taken out as CLKA, the carrier pulse
train. CLKA is coherent with the carrier signal, with its rising

Fig. 2: Functional block diagram of the PHASE_DELAY_LATCH
and falling edges matching exactly with the positive and
negative zero crossing points of the carrier signal. A zero-
crossing detector (ZCD) circuit converts the LVDT secondary
output signal into modulated signal pulse train CLKB.
A functional block diagram of the
PHASE_DELAY_LATCH, as presented in Fig. 2, shows the
sub-blocks that implement the aforesaid functionalities. Two
identical digital noise filters DNF1 and DNF2 remove noise
glitches from CLKA and CLKB, the incoming pulse trains and
generate the filtered equivalents, viz. CLK1 and CLK2. Noise
glitches are very short duration spikes, with pulse widths
negligible compared to that of the pulse train CLKA or CLKB.
The DNFs are designed to reject pulses of width below a
preset time period, PD_FILT. The CNT_POS_EDGE block
starts a counter at the rising edge of CLK1, stops the same at
the rising edge of CLK2, and latches the same as DCNT1. The
CNT_NEG_EDGE block starts another counter at the rising
edge of CLK1, stops the same at the subsequent falling edge of
CLK2, and latches the same as DCNT2. The WATCH_DOG
block checks whether a valid rising edge and a falling edge of
CLK2 occur prior to the next rising edge of CLK1. If yes, it
latches the count values DCNT1 and DCNT2. If no, it clears
both the counters and restarts the delay count process from the
next rising edge of CLK1. The MIN_COUNT block finds the
minimum of DCNT1 and DCNT2, PD_FILT is subtracted
from it, and finally latched as DCNT.
The CARRIER_PRD_GEN block counts the period of
CLK1 and latches the same as PD_CNT on an output latch.
The next block in the chain, QDR_PULSE_GEN, takes as its
inputs DCNT and PD_CNT to generate CLK3, a pulse train
whose time period equals that of CLK2 but is in quadrature
with CLK2. This is done by delaying the rising edges of CLK3
by DCNT and a quarter of PD_CNT from those of CLK1.
The final block, STB_GEN generates sampling pulses,
STB, whose falling edges coincide with the rising edges of
CLK3. STB drives a sample and hold amplifier, SHA. The on-
time of STB depends upon the acquisition time of the SHA and
should be designed accordingly. The input to the SHA is the
LVDT secondary output signal. The SHA output, SH0, is fed to
the input of a successive approximation (SA) type ADC, which
digitizes the LVDT secondary output signal at the carrier
peaks. Block RD_ADC_DATA generates the ADC handshake
signal R/C~, reads the status signal EOC, and latches the
converted data, DATA12, on an output latch.
Block SPI_SLAVE implements a 16-bit SPI slave channel,
a synchronous serial interface of the signal conditioner with
the host processor. The module converts DATA12 to a 16-bit
data and loads the same on a 16-bit parallel-input serial-output
shift register, PISO_16. On receipt of sixteen serial clocks at
SCLK from the host processor, it outputs the 16-bit data,
serially, through SDO, to the host processor. Data bits are
shifted at every rising edge of SCLK, with the LSB transmitted
first. The serial clock frequency is decided by the host
processor; but from the design point of view, the maximum
permissible clock frequency is set to be 1 MHz.
III. IMPLEMENTATION ISSUES
This section documents a brief overview of the
implementation of the analog front-end hardware and the
mapping of the functional blocks of the inner core on the
target FPGA board.
A. Analog front-end hardware
The sensor interface comprises of a low-distortion sine
wave generator to drive the LVDT primary winding and an
ADC to read the secondary differential voltage. The sine wave
generator consists of a 12-bit full four quadrant multiplying
DAC, AD7541A driven by the FPGA-based DDS module.
Since the DAC provides a unipolar current output, a dual
JFET-input op-amp IC, TL082 is used for current to voltage
conversion and level-shifting to generate a bipolar sinusoid of
5.0V peak-to-peak excursion. The VREF of the DAC is taken
from the on-chip VREF of the ADC. The ADC used in this setup
is a 12-bit SA-type ADC, AD574A that comes with an on-chip
stable 10.0V VREF (maximum 0.2% error and typical
temperature coefficient of 15ppm/°C) which is available
externally and can drive up to 1.5 mA. As a single stable
voltage reference source is used to drive both the DAC and
ADC, any drift in the same will introduce changes in the DAC
and ADC outputs such that one nullifies the other. This, in
effect, implements an auto correction mechanism that keeps the
scaling factor independent of the drifts in the carrier amplitude
due to changes in the reference voltage.
The ADC does not come with a SHA and hence a SHA unit
is implemented using the monolithic sample-and-hold IC,
LF398. The input to the SHA is the LVDT secondary
differential output and the sample-and-hold pulse comes as
STB. The SHA output, SH0, is fed to the input of the ADC,
calibrated for a ± 5.0V bipolar input.
In addition to the ADC and DAC, the signal conditioner
requires a ZCD unit for converting the LVDT secondary output
to a pulse train. In this setup the ZCD unit is implemented
using the monolithic comparator IC, LM311. Adequate
hysteresis (≈150 mV) is provided in the ZCD unit for input
noise rejection. By design, the rising edges of the pulse train at
the ZCD output occur at the positive zero crossing points of
the input analog waveform.
B. FPGA mapped blocks
The inner core of the LVDT signal conditioner is designed
and implemented on a MEMEC FPGA Evaluation Board that
uses a Xilinx XC2S100 SPARTAN-II FPGA chip using the
Xilinx PC-based ISE 9.1i Design Development System. The
system clock fCLK is derived from the on-board 25.0 MHz
crystal and the I/O pins are made LVTTL compatible. The gate
 TABLE I: GATE UTILIZATION OF THE DEVICE
Target Device xc2s100-6pq208
Total equivalent gate count 19,656
f utilization
Gate d i 19.656%
Fig. 3: Functional block diagram of the DNF
complexity of the design, as generated by design software
tool, is reported in Table I. As the implementation details of
the basic demodulator are documented in [12], this section
explains the implementation of the additional blocks necessary
to implement the proposed LVDT signal conditioner.
• The Digital Noise Filter: Implementation details of
the DNF block is illustrated in Figure 3. At every
power-on reset the N-bit shift register and the T flip-
flop are reset. The input pulse train at FIN is
compared with the DNF output, FOUT. If the input is
initially 0, the shift register remains reset. Whenever
the input changes to logic 1, the transition propagates
to the output only if the input level remains high for
at least N rising edges of SYS_CLK. However, if the
input changes to 0 prior to the Nth rising edge, the
register CLR logic is asserted and all stages of the
shift register are reset. Thus any pulse train at FIN
with on-time/off-time less than N periods of the
SYS_CLK will not propagate to the filter output. In
this setup N is chosen to be 5, and since the on board
system clock is 25 MHz, the DNF eliminates all
noise glitches of width less than 200 nsec. This,
however, sets the maximum frequency limit for the
primary excitation signal. Since generation of the
quadrature pulse train, CLK3, fails if the filter delay
Tf is greater than Tc/4, the quarter period of the
carrier signal, the maximum carrier frequency fMAX
that the implementation can handle is fMAX = 1/(4*Tf)
= 1.25 MHz.
• The Watch-Dog Circuit: The WATCH_DOG unit, as
illustrated in Figure 4, resolves two constraints in the
generation mechanism of the CLK3 pulse, (i) if
during start-up the LVDT core is at the null position,
a zero secondary differential voltage is obtained and
(ii) if the same incident occurs during the periodic
update of the frequency and phase information of
CLK3. In both cases the ZCD fails to generate CLK2
and hence the phase and frequency information of
CLK3 cannot be generated and hence updated. At a
preset update rate set up by a timer module (60 sec in
this setup), the GEN_START_PULSE circuit
generates a ST_UP pulse. Triggered by ST_UP a
Fig. 4: Functional block diagram of the WATCH_DOG
binary counter in CARRIER_PRD_GEN block counts
the SYS_CLK between two successive rising edges of
CLK1, the carrier pulse train, and latches the same as
PD_CNT. The binary counter in
CARRIER_PRD_GEN block is implemented as a 16-
bit counter. Hence, the minimum carrier frequency it
can handle is fMIN = fCLK / 216 ≈ 381 Hz. So, the
minimum carrier frequency the implemented LVDT
signal conditioner can tune to is 381 Hz. On the next
rising edge of CLK1, the GEN_START_PULSE
circuit generates a ST_DELAY pulse. Triggered by
the ST_DELAY pulse, two binary counters in
CNT_POS_EDGE and CNT_NEG_EDGE blocks
start counting the SYS_CLK. The binary counters stop
counting – the first one at the rising edge of CLK2
and the second one at the falling edge of CLK2, and
hold the corresponding count values DCNT1 and
DCNT2 respectively. Triggered by the same
ST_DELAY pulse, The EDGE_DETECT circuit waits
for one CLK1 period for occurrence of a rising as
well as a falling edge of CLK2. On receipt of both, it
generates a LE pulse and a two SYS_CLK delayed
LE1 pulse. LE latches the delay counts DCNT1 and
DCNT2 and LE1 latches DCNT, the difference of the
minimum of these two counts (i.e. DCNT1 and
DCNT2) and PD_FILT, at the output of
PHASE_DELAY_LATCH block. If either of the edges
of CLK2 is missing within one period of CLK1, the
EDGE_DETECT unit generates a CLR pulse instead
that resets the two binary counters in
CNT_POS_EDGE and CNT_NEG_EDGE blocks.
So, if during start-up, CLK2 edges are missing
(condition (i)), DCNT1 and DCNT2 are zeros, and
hence DCNT is not updated and holds the initial
value of zero. CLK1 and CLK3 are in coherence and
the pulse train generated by the QDR_PULSE_GEN
block is in quadrature with CLK1. Hence the LVDT
secondary output is read at the primary excitation
peaks. Similarly, if during the periodic update of the
frequency and phase information of CLK3, CLK2
edges are missing (condition (ii)), DCNT1 and
DCNT2 are zeros, but the output of
PHASE_DELAY_LATCH block holds DCNT, the
delay count as generated in the previous update cycle.
• The DDS module in the SW_GENERATOR block in
the proposed LVDT conditioner needs to be
programmed to generate a sinusoid of frequency fSW
that satisfies the condition fMIN ≤ fSW ≤ fMAX. The DDS
 block can be programmed to any frequency in the
said range in steps of 1 Hz, and the performance of
the signal conditioner is independent of this choice.
For the implementation reported in this paper, the
primary excitation frequency is arbitrarily chosen to
be 12.5 kHz.

IV. TEST RESULTS

The prototype setup for the proposed LVDT signal
conditioner is tested for:
• Design verification of the proposed demodulator:
These tests verify the design of the peak synchronous
demodulation scheme implemented in the proposed
LVDT signal conditioner. First we evaluate the design
of the phase-compensated synchronous demodulation
process. This is done for two test cases – (i) with no
sensor induced phase lag and (ii) with sensor induced
phase lag.
• Computation of the overall error: This test is to
compute the overall error of the proposed LVDT
signal conditioner for comparison of the same with
those of the commercially available solutions. The
transfer characteristics of the system is first obtained
by driving its input over its entire range in small steps
and then the maximum and average deviations of the
same from the ideal transfer characteristics are
computed.
• Bandwidth estimation: This test evaluates the
dynamic characteristics of the LVDT signal
conditioner. A magnitude and phase plot of the LVDT
signal conditioner output, for simulated sinusoidal
core movements to ascertain the –3dB is presented
for estimation of the system bandwidth.
The test setup required for performance analysis of the
demodulator and bandwidth estimation of the proposed signal
conditioner necessitates the generation of sinusoidal vibrations
of the LVDT core position. In absence of one such setup, we
worked with an LVDT emulator, built in line with [14],
involving linear ICs, a programmable dc power supply and an
arbitrary waveform generator.
A. Design verification of the proposed demodulator
In the first test run, the LVDT emulator is set to generate a
7.0V peak-to-peak DSB-SC-AM waveform with zero sensor
induced phase lag, which is subsequently used to drive the
LVDT signal conditioner. The test results are shown in Fig. 5;
the LVDT emulator output (V_MOD) and the demodulator
output (V_DMOD). The plot shows V_DMOD, a 50 Hz
sinusoid with a peak-to-peak excursion of 7.02V, to be a
perfect envelope detected form of V_MOD.
In the second test run, the LVDT emulator is set to generate a
7.0V peak-to-peak DSB-SC-AM waveform with a sensor
induced phase lag of 18°. Fig. 6 shows the LVDT emulator
output (V_MOD) and the demodulator output (V_DMOD).
The plot shows a perfect synchronous demodulation of
V_MOD with no phase lag between the envelope of the
modulated waveform and the demodulated output. Also note
Fig 5: LVDT Emulator and demodulator outputs for zero
sensor induced phase lag
Fig. 6: LVDT Emulator and demodulator outputs for 18°
sensor induced phase lag
that there is no attenuation in the peak-to-peak excursion of
V_DMOD, which ensures a true phase insensitive detection.
B. Computation of overall error
Although it is customary to specify the linearity error of an
LVDT signal conditioner, in this setup it is impossible to
decouple the same from the linearity, gain and offset errors of
the commercial grade analog amplifiers, analog multiplier,
SHA, ADC and DAC chips. So, the overall error is computed
instead by comparing the actual transfer characteristics of the
signal conditioner with its ideal transfer curve. The LVDT
emulator is set to generate a DSB-SC-AM waveform with zero
sensor induced phase lag, with modulating signal (core
position) varying from –12V to +12V in steps of 0.5V
(resulting in 49 data points). Each step thus emulates an
incremental change in the LVDT core position. The
demodulator analog outputs for the corresponding signal
conditioner inputs generate the actual transfer characteristics.
Finally for each measured data, the deviation from the ideal
transfer characteristics is computed. The maximum deviation
(maximum overall error) and the average deviation
(average/typical overall error) are computed and listed in
Table II. The overall errors of the monolithic LVDT signal
conditioners are also included in Table II for ready reference.
The overall error figures of the proposed solution are slightly
on the higher side but are comparable with those of the
monolithic solutions.
C. Bandwidth Estimation
The LVDT responds very fast to changes in its core position.
The dynamic response of an LVDT sensor itself is actually
limited by the characteristics of the signal conditioner. As
reported in [6], the –3dB bandwidths of AD598 and AD698 are
 TABLE II: OVERALL ERROR FIGURES OF LVDT SIGNAL CONDITIONERS
Proposed
AD598 AD698
scheme
Maximum Overall
2.35 1.64 2.6
Error (%of FS)
Average/Typical 0.6 0.4 0.7
Overall Error (%of FS)
Fig. 7: Frequency Response of the proposed LVDT signal conditioner
around 100 Hz and that for the DSP based COSTAS receiver is
more than 250 Hz.
For this test run, the LVDT emulator is used to generate a
DSB-SC-AM where the modulating signal (core position) is
varied from 10 Hz to 400 Hz in steps of 10 Hz to simulate
sinusoidal core motion. The proposed signal conditioner is
driven by the LVDT emulator output and the magnitude and
phase of the demodulator output are measured and recorded to
generate the frequency response as shown in Fig. 7. The input
of the DAC, whose output is the analog demodulated
waveform, is updated at a rate of 12.5 kHz. It thus behaves
like a zero order hold circuit with a hold time of one sampling
interval, i.e. 80 μsec. The reconstructed waveform,
conventionally obtained by joining the central points of the
held values, thus shows an average delay of half the hold
time, i.e. 40 μsec. The phase lag at individual frequency points
is, therefore, obtained by multiplying the average delay by the
corresponding angular frequency. The system bandwidth, as is
obvious from the magnitude plot is well above 400 Hz. The
phase plot is a straight line plot, with a slope of –0.0144°/Hz,
resulting in a phase lag of –5.76° at 400 Hz. The dynamic
characteristics of the proposed LVDT signal conditioner is thus
better than the existing monolithic and processor based
solutions.
V. CONCLUSIONS
A novel FPGA-based LVDT signal conditioner is designed
and implemented. It implements a phase insensitive
demodulator with direct digital readout of the demodulated
data at the carrier peaks of the modulated waveform. The
input digital filter chain and watch-dog circuit add to the
robustness of the signal conditioner. The range of primary
excitation frequency that it can generate makes it suitable for
iron core as well as ferrite core LVDTs, that too for both the 4-
wire and 5-wire variants.
Performance analysis of the proposed scheme shows that
the total error figure of the same is comparable with the
monolithic LVDT signal conditioners. Its dynamic
characteristic is better than those of the monolithic LVDT
signal conditioners and processor based solutions. Moreover,
cost wise, it is more economical than standard processor based
solutions. The minimal analog hardware requirement makes
the process suitable for integration into a complete system
including the sensor, operating from a dual dc power supply.
ACKNOWLEDGMENT
The authors wish to thank the members of the Centre for
Embedded Systems in Instrumentation, Dept. of
Instrumentation & Electronics Engineering, Jadavpur
University for the facilities made available to them for
fabricating and testing the hardware setups.
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