Data - Clock Setup and Hold Times Margins

Correction Method in High Speed Serial Links

Vazgen Sh. Melikyan#, Arthur S. Sahakyan*, Aram H. Shishmanyan#,
Nazeli V. Melikyan#, Grigor Y. Zargaryan#
#
Department of Microelectronics Circuits and Systems, State Engineering University of Armenia
105, Teryan str., 0009 Yerevan, Republic of Armenia
Synopsys Armenia CJSC
1
vazgenm@synopsys.com
3
aramsh@synopsys.com
4
nazeli@synopsys.com
5
grigorz@synopsys.com
*
VLSI Design Specialization, Synopsys Armenia Educational Department
41, Arshakunyants Avenue, 0009 Yerevan, Republic of Armenia
Synopsys Armenia CJSC
2
arthurs@synopsys.com

Abstract— A method of serial links output data and clock signals

setup and hold times correction presented in this paper. The
proposed architecture produces corrected clock which have
enough setup/hold time margins respect data signal over PVT,
which is needed to avoid data errors and setup/hold violations
during further operation with data. The presented correction
mechanism can be used in the special input/output circuits of
several standards such as Peripheral Component Interconnect
(PCI), Universal Serial Bus (USB), Double Data Rate (DDR) etc.

Keywords—Serializer, Voltage Controlled Delay Line (VCDL),

PVT, Clock Corrector (CC).
Fig. 1 High Speed Serial link

I. INTRODUCTION
It will cause to exclude data lost and setup/hold violations.
In high speed systems (Fig. 1) and interfaces [1], where As a result of the mentioned phenomena, the system may fail
signal pulse width becomes small, it needs data sampling clock to function under some operating conditions such as high
to be in middle of data signal for prevent setup/hold times temperatures or over-voltages.
violations and hence data errors. For high speed signal
processing setup/hold times are important factor and its effects
cannot be ignored. When data signals in the inputs of
Serialaizer (Fig. 2) come with different delays as a result in the
output can lose the data, because data and clock paths are
different and it can cause setup/hold violations. In general
setup/hold time is the minimum amount of time the data signal
should be held steady before/after the clock event so that the
data are reliably sampled by the clock. One of the main factors
data/clock signals spreading over PVT of high speed devices is
rise/fall times and propagation delays distribution due to
process variation.

Fig. 2 Serializer/Corrector circuit structure

In Fig.3 shown clock/data timing diagrams from which its

clear that data frequancy is two time slower than clock signal.
 Fig. 3 Timing diagrams with Setup/Hold times

where PW is the pulse width of signal, tsu is setup and thd is

hold times. The proposed method dynamically corrected
setup/hold times between Serializer clock and data signals.

II. SETUP/HOLD TIMES CORRECTION CIRCUIT

Fig. 5 Delay Control Amplifier
ARCHITECTURE
The structure of proposed setup/hold times Correction As we need to have an amplifier that is noise stable and
Method is presented in Fig.4. provides integrated voltages on the outputs depended of its
inputs, we chose the following architecture in Fig.5.
For that purpose the input diff pairs have a large channel
lengths which is implemented using sequential transistors
connected with each other. To have integrated outputs
capacitance loads are connected to the outputs of amplifier
(Fig.5). Delay elements (Fig.6) are controlled by Diff amp
outputs Vsh_p and Vsh_n.

Fig. 4 Setup/Hold time correction circuit structure

In this architecture Replica part, needs corrected clocks,

which dynamically fix data signal setup/hold times in the
Serializer. For this goal we use Replica in the loop of CC
circuit.
Fig. 6 VCDL circuit structure
Correction circuit contains both analog and digital blocks.
In this structure analog blocks are Low Pass Filters (LPF), As controlled clocks are differential signals the represented
Amplifier and VCDL. Digital parts are presented with MUXes MUXes are operating with 2 control inputs.
in replica of CC loop and in Serializer stage.
 output currents when Delay control amplifier changes its
output voltages (Vsh_p and Vsh_m). After several iterations,
when loop is locked, VCDL generates fixed clock signals
which is middle of data signal and have no setup/hold
violations.
The output signals of XOR gates are passing through the
LPF and so the DC component of this data is used as inputs of
Delay Control Amplifier (DCA). As it was said formerly the
DCA input diff pair has sequentially connected transistors with
large lengths and widths. Large lengths are for noise stability
and large widths are for high gain. Besides as LxW are is large
enough, and taking in account the fact that external capacitor
need much are, the capacitor of LPF is implemented here using
the input diff pair of DCA.

IV. SIMULATION RESULTS

Fig. 7 2x1 MUX Serializer
III. OPERATION PRINCIPLE AND CORECTION
Block diagram on Fig.8 has been proposed to attain
a corrected clock signal nearly to middle of data signal. As it is
known the average DC value of a signal is proportional to
its Duty Cycle. Before applying PLL clocks to the Serializer
Simulations have been performed using circuit level
simulator Hspice[4] for 20 PVT corners, including SS (slow-
slow), TT (typical-typical), FF (fast-fast), SF (slow-fast), FS
(fast-slow) with supply voltage and temperature variations to
estimate accuracy (Setup/Hold time margins (tsu/thd )) and the
settlement time (tset).
Fig.10 (a) shows CC settlement results for TT (55 ) typical
O

and Deserializer, they are being corrected with the negative corner. It is seen that amplifier’s outputs is going to be settled
feedback system. after 42ns when setup time is about 98ps (from 100ps). In this
case Vsh_p=0.512V and Vsh_n=0.510V.
Transmitter
Fig.10 (b) and Fig.10 (c) show simulation results for,
Parallel data PLL clocks respectively, FF(-40O) and SS(125O) main PVT corners.
Taking into consideration that USB3.0 protocol works with
the 5 Gb/s data rate signal, which means that Data have 400ps
VCDL pulse period and 200ps pulse width, we have put internal
specification for tsu/thd the 25% of period, i.e. after clock can be
considered as corrected, when tsu/thd is less near 100ps. In
Serializer DIV2 DFF USB3.0 specification book tsu/thd min value defined as 20ps.
The next important parameter is Settling time (ST), which
shows the time when CC is locked. Table 1 shows results for 3
Transmitter Replica of main corners.
Serial data Serializer
TABLE I. Simulation results of the three main corners
tsu/thd Settling
XOR Corner
N P time

Low Pass Filters ps ps ns

Unit
(DC components of clocks)
98.05/100. 98.7/100.1
42
TT(55) 93 2
Delay Control Amplifier
108.08/90. 107.5/91.3
40
FF(-40) 7 2
88.05/110.
89.7/112.3 46
Fig. 8 Block diagram of correction method SS(125) 7

As it was mentioned above the clocks that are needed for

serializing data are coming from Phase Locked Loop (PLL)
through lines that can affect propagation delays of these
clocks over PVT and it can brings setup/hold violations.
CC process starts from VCDL block (Fig.8). VCDL has 2
voltage controlled delay inverters that are changing their
 SS (c)
Fig. 9 Simulation results in TT case with setup violation
Fig. 10 CC settlement results for TT (a), FF (b) and SS (c) corners

Fig. 9 shows simulation results before setup/hold

correction for TT. Table 1 shows duty cycle improvement after
correction.

V. CONCLUSIONS
A circuit designed for Serializer final serializing stage
output data and clock setup/hold signal correction. The closed
loop system with negative feedback integrates clock signals
and provides stable signals. Average Deviation for TT corner
is equal to 0.085%, after 42ns of settling time, the tsu/thd has
the value of 98ps, where the minimum spec of setup/hold time
margins from the USB3.0 specification book is 20ps.
The approached method can be implemented for
input/output protocols such as USB, PCI and etc.
TT (a)
This work was supported by State Committee Science MES RA, in
frame of the research project 13-21130.

REFERENCES
[1] S. Patil and S. B. Rudraswamy, “Duty cycle correction using
negative feedback loop”, 16th International Conference "Mixed
Design of Integrated Circuits and Systems", June 25-27, pp. 424 -
426, 2009.
[2] A. Reddy Chada and B. Mutnury, “Simulation challenges in
designing high speed serial links”, IEEE 62nd Electronic
Components and Technology Conference (ECTC), pp. 153 - 159,
2012
[3] R. Jacob Baker, CMOS Circuit Design, Layout, and Simulation,
Second Edition, 2008 .
[4] Hspice Application Manual, Synopsys Inc. , 2010.

FF (b)
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Oalll • Cloc k Setup and Hold Times Margins Correction Method ill High Speed Serial Links
CQ,"lPLETE LTST OF AUTIIORS:
Vazg en Melikyan. ArthurSahakyan , 1\1'8111 Sh is hrn anyan , Naze li Me likyan and Gri gor Zargaryan
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