Application Note AN-1043

Stabilize the Buck Converter with Transconductance Amplifier

By Michael (Chongming) Qiao, Parviz Parto and Reza Amirani

1. Introduction..................................................................................... 1

2. Loop Gain of System ...................................................................... 2

3. Typical Procedure of Compensator Design .................................................... 2

4. Type II (PI) Compensator Design ................................................... 3

4.1 Introduction to PI Compensator.................................................... 3

4.2) Design Example of PI Compensator ........................................... 4

5. Type III (PID) Compensator............................................................ 5

5.1) Introduction to Type III Compensators ........................................ 5
5.2) Type III (PID) Compensator Design Method A............................ 6
5.3) Design Example of PID Compensator Method A ........................ 7
5.4) Type III (PID) Compensation Design Method B .......................... 8
5.5) Design Example of IRU3037 with Ceramic Capacitor
and PID Compensator Method B...................................................... 10

6. Conclusion.................................................................................... 10

Synchronous DC-DC buck converters have high efficiency, and International Rectifier has
developed a series of PWM voltage mode controllers for synch buck converters, including single
and multi-phase controllers such as IRU3037, IRU3038, IRU3046 and IRU3055. One feature of
these controllers is that transconductance amplifiers are employed as voltage feedback error
amplifiers.
 APPLICATION NOTE AN-1043

Stabilize the Buck Converter with Transconductance Amplifier

Michael (Chongming) Qiao, Parviz Parto and Reza Amirani, International Rectifier
Synchronous buck converters have received great at- and ESR is the Equivalent Series Resistance of output
tention in low power, low voltage DC-DC converter appli- capacitor. There are three sections. One is synchronous
cations in recent years due to their high efficiency. Inter- buck converter including output inductor and capacitor.
national Rectifier Inc. has developed a series of PWM The controller such as IRU3037 provides the basic func-
voltage mode controllers for synchronous buck convert- tion block such as PWM generator and transconduc-
ers, including single phase and multi-phase controllers tance amplifier. The resistor and capacitor with the
such as IRU3037, IRU3038, IRU3046, IRU3055, etc. One transconductance amplifier, function as a compensator
feature of these controllers is that transconductance am- to stabilize the system. From control system point of
plifiers are employed as voltage feedback Error Amplifi- view, the three blocks are shown in Figure 2.
ers. Theoretically, a transconductance amplifier is an
equivalent voltage controlled current source. It multiplies G(s)
the difference of input voltage with a certain gain and PWM Buck
Compensator
generates a current into the output node. It features high Generator Converter
output impedance and it is stable by most of the output VREF
1
D(s) VOSC GP (s) VOUT
compensation components. The output short circuit pro-
tection and internal compensation is not required. This
results in a smaller die size and simple design. In this
application note, how to stabilize the buck converter with
transconductance Error amplifier is discussed. The goal Figure 2 - The control diagram for the synchronous
of the design is to provide a loop gain function with a buck converter with transconductance amplifier.
high bandwidth (high zero-crossover frequency) and ad-
equate phase margin. As a result, fast load response The transfer function of the PWM generator is basically
and good steady state output can be achieved. 1/VOSC , where VOSC is the peak to peak voltage of oscil-
lator listed in the datasheet. The transfer function of the
1. Introduction to Synchronous Buck Converter with buck converter can be simplified as follows:
Transconductance Amplifier
1+ESR3COUT3s
GP(s)= 3VIN
Q1 L RL

Output Inductor
1+s3 (R L
LOAD )
+ESR3COUT +s 23L3COUT
---(1)
ESR
Output V OUT
+
V IN Capacitor
R LOAD The (s) indicates that the transfer function varies as a
Q2 COUT function of frequency.

Buck Converter For simplification, we can combine the transfer function

V REF of PWM generator and buck converter. This results in
gm Rf1
power stage of buck converter and is expressed as:
Rc1 1
PWM generator G(s) = GP(s)3 ---(2)
Cc2 VOSC
Rf2
Cc1
Compensator with Basically, the transfer function of the power stage is a
Transconductance Amplifier second order system and the Bode plot is shown in Fig-
ure 3. The resonance of the output LC filter introduces a
Figure 1 - Simplified diagram for synchronous buck double pole and -40dB Gain Slope (see Figure 3). The
converter with transconductance amplifier. resonance frequency of the LC filter is expressed as
follows:
The simplified diagram for synchronous buck converter 1
with transconductance amplifier is shown in Figure 1, FPO = ---(3)
23p3 L3COUT
where RL is the inherent resistance of output inductor

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APPLICATION NOTES AN-1043

The ESR of the output capacitor and capacitance intro-

duces one zero for the system. The zero is given as:
1 Power Stage
FZO = ---(4)
23p3ESR3COUT
-40dB
Where FZO is a character parameter and dependent on
the characteristic of what capacitor is chosen. Typically, f
for an electrolytic capacitor, the F ZO is in a few KHz range. -20dB

FPO FZO
VIN
-20dB
VOSC Desired
Loop Gain
Magnitude
Fo
-40dB

f 0 f
Phase
-20dB -90
Phase Margin
-180

Fpo Fzo
Figure 4 - Bode plot of desired loop gain function.

0 f 3. Typical Procedure of Compensator Design

Phase In order to realize the desired loop gain with high enough
-90 zero-cross over frequency and proper phase margin, a
compensator has to be designed. A typical procedure is
-180
as follows:

Figure 3 - The Bode plot of buck converter Step 1 - Collect system parameters such as input volt-
power stage. age, output voltage, etc. and determine switching fre-
quency.
2. Loop Gain of System Step 2 - Determine the power stage poles and zeros.
The loop gain of system is defined as the product of Step 3 - Determine the zero crossover frequency and
transfer function along the closed control loop. From Fig- compensation type. The compensation type is deter-
ure 2, the loop gain is defined as: mined by the location of zero crossover frequency and
characteristics of output capacitor as shown in Table 1.
1
H(s) = D(s)3 3GP(s) = D(s)3G(s) ---(5)
VOSC
Compensator Location of Zero Typical
The Bode plots of desired loop gain and power stage is Type Crossover Frequency Output
shown in Figure 4, where FO is the zero crossover fre- (FO) Capacitor
quency defined as the frequency when loop gain equals Type II (PI) FPO < FZO < FO < fS/2 Electrolytic,
unity. Typically, FO can be chosen to be 1/10~1/5 of the Tantalum
switching frequency. F O determines how fast the dynamic Type III (PID) FPO < FO < FZO < fS/2 Tantalum,
load response is. The higher FO is, the faster dynamic Method A Ceramic
response will be. The slope rate of loop gain around FO Type III (PID) FPO < FO < fS/2 < FZO Ceramic
should be –20dB in order to get a stable system. The Method B
phase margin is shown in Figure 4. Typically, 458 or more
phase margin is desired for a stable system. Table 1 - The compensation type and location
of zero crossover frequency.

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 APPLICATION NOTE AN-1043

Step 4 - Determine the desired location of zeros and A PI compensator can be used as shown in Figure 5.
poles for the selected compensator. Overall, the Bode plots of power stage, desired loop gain
Step 5 - Calculate the real parameters-resistor and ca- and PI compensator are displayed in Figure 6.
pacitors for the selected compensator. Choose the re-
sistors and capacitors from standard catalog such that A PI compensator has one zero at:
they are as close to the calculated value as possible. 1
FZ1 = ---(6)
2p3RC13CC1
4. Type II (PI) Compensator Design
Resistors Rf1 and Rf2 are used to determine the output
4.1) Introduction to PI Compensator voltage. The output voltage is determined as:
VOUT VREF Rf2
= ---(7)
VOUT Rf1 + Rf2
Rf1
The output voltage can be directly connected to the feed-
Ve back pin of the Error amplifier. This is shown as:
Rf2 gm
VOUT = VREF
Rc1
The resistor RC1 determines the zero crossover frequency.
It can be calculated as:
VREF Cc1
2p3FO3L3VOSC Rf1 + Rf2
RC1 = 3
ESR3VIN3gm Rf2
Figure 5 - PI Compensator configuration.
When the above equation is combined with equation (7),
it results to:
-40dB 2p3FO3L3VOSC VOUT
RC1 = 3 ---(8)
Power ESR3VIN3gm VREF
Stage
Set the zero of PI compensator to 75% of FPO:
Fpo fs/2 1
FZ1 = = 0.753FPO ---(9)
Fzo -20dB 2p3RC13CC1
Desired
Loop The compensator capacitor Cc1 can be calculated as:
Gain
1 L3COUT
-20dB CC1 = = ---(10)
0.7532p3FPO3RC1 0.753RC1
Fo
PI -20dB In practice, one more capacitor is sometimes added in
Compensator parallel with the RC network as shown in Figure 7.

VOUT

Fz1 Rf1
Figure 6 - Bode plot of the buck converter power
Ve
stage, desired loop gain and PI compensator. Rf2 gm
In many applications, an electrolytic capacitor is cho- Rc1
sen as the output capacitor due to its low cost. For elec- Cc2
trolytic capacitor, the zero caused by ESR (FZO) is a few VREF Cc1
KHz. If the switching frequency is a few hundred KHz,
the zero crossover frequency FO is chosen to be 1/10 of
switching frequency and FO is located at: Figure 7 - PI compensator with one additional pole.
FPO < FZO < FO < fS/2

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APPLICATION NOTES AN-1043

This additional capacitor gives a second pole as: Step 1 - Collect system parameters such as input volt-
1 age, output voltage, etc. and determine switching fre-
FP2 = ---(11) quency.
CC13CC2
2p3RC13
CC1 + CC2 Input Voltage 5V
Set this pole to one half of switching frequency, which Output Voltage 3.3V
results in the capacitor Cc2. Output Current 10A
Switching Frequency 200KHz
fS
FP2 = Output Inductor 3.3mH
2
Output Capacitor 2200mF with 18mV ESR
1 1 Peak to Peak Oscillator VOSC = 1.25V
CC2 = ≅ p3RC13fS ---(12)
1 Ramp Voltage
p3RC13fS -
CC1 Reference Voltage VREF = 1.25V
Transconductance Gain gm=0.6mA/V or 600mmho
4.2) Design Example of PI Compensator
Take IRU3037 controlled buck converter as an example. Table 2 - The parameters of IRU3037 controlled
The schematic is shown in Figure 8. buck converter in Figure 8.

5V
D1
1N4148 L1

1uH
D2 C2 C1
1N4148 2x 10TPB100ML, 47uF
100uF, 55mV
C3 C4 C5
1uF 1uF 0.1uF

Vcc Vc
Q1
HDrv
IRF7457 L2
U1
SS 3.3V
C8 3.3uH
IRU3037 @ 10A
0.1uF Q2 C7
LDrv
IRF7460 2200uF
ESR 18mV

Comp Rf1
Cc1 Fb
4.7nF 1.65K, 1%
Cc2 Gnd
68pF Rc1 Rf2
27K 1K, 1%

Figure 8 - Application of IRU3037 with PI compensator.

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 APPLICATION NOTE AN-1043

Step 2 - Determine the power stage poles and zeros. (Optional) Second capacitor CC2 can be calculated us-
The pole caused by the output inductor and output ca- ing equation (12):
pacitor is calculated as:
1 1
1 CC2 = p3RC13fS = p327K3200K ≅ 59pF
FPO =
2p3 L3COUT
Select CC2 = 68pF
1
FPO = ≅ 1.87KHz Calculate resistors Rf1 and Rf2. Select resistor Rf2 to be a
2p3 3.3mH32200mF
reasonable value. For example, from low noise point of
The zero caused by ESR of the output capacitor is cal- view, select Rf2=1K, 1%.
culated as:
VO-V REF 3.3-1.25
Rf1 = 3Rf2 = 31K = 1.64K
1 VREF 1.25
FZO =
2p3ESR3COUT
Select Rf1 = 1.64K, 1%
1
FZO = ≅ 4KHz 5. Type III (PID) Compensator
2p318mV32200mF

Step 3 - Determine the zero crossover frequency and 5.1) Introduction

compensation type. Select desired zero-crossover fre- The PI compensation is based on the output capacitor
quency: having enough ESR to ensure stability. If the output ca-
fS fS pacitor is a ceramic capacitor, the zero caused by ESR
FO [ ~ will be much larger than the desired zero cross over fre-
5 10
Select FO=20KHz quency, the type III (PID) compensation is considered
as shown in Figure 9. The Bode plot of the PID compen-
fS
Because we have FPO<FZO<FO< , a PI Compensator sation network is shown in Figure 10.
2
is chosen.
VOUT
Step 4 - Determine the desired location of zeros and Zf Zc
Cc2
poles for the selected compensator. Select:
Rf3
FZ1 = 0.753FPO = 0.7531.87KHz ≅ 1.4KHz Rf1 Rc1 Cc1
Cf3
If additional capacitor is chosen:
fS
FP2 = = 100KHz Ve
2 gm
Rf2
Step 5 - Calculate the real parameters-resistor and ca-
pacitors for the selected compensator.
Calculate RC1 from equation (8): VREF
Figure 9 - PID compensation network.
2p3FO3L3VOSC VO
RC1 = 3
ESR3VIN3g m VREF
2p320KHz33.3mH31.25
RC1 = 3 3.3 PID
18mV35V30.6310-3 1.25 -20dB -20dB
Compensator
RC1 ≅ 25.3K
Select RC1 = 27K
Calculate CC1 By: Fz1
Fz2 Fp2 Fp3 = fs/2
1 L3COUT
CC1 = = Figure 10 - Bode plot of PID compensator.
0.7532p3FPO3RC1 0.753RC1
3.3mH32200mF
CC1 = ≅ 4.2nF
0.75327K

Select CC1 = 4.7nF

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APPLICATION NOTES AN-1043

The transfer function of the PID compensator is given Set first zero of PID at 75% of the resonant pole caused
as: by output inductor and capacitor:
Ve 1-gm3ZC
= ---(13) FZ1 = 75%3FPO ---(20)
VOUT 1+gm3Zf+Zf/Rf2
The error amplifier gain is independent of the transcon- Set second zero of PID at exact resonant pole caused
ductance under the following condition: by output inductor and capacitor:
Zf
gm3Zf >> 1+ and gm3ZC >> 1 FZ2 = FPO ---(21)
Rf2
So we have: Set second pole of PID at the zero caused by output
capacitor ESR:
Ve ZC
≅
VOUT Zf FP2 = FZO ---(22)
By replacing the ZC and Zf according to Figure 9, the Set the third pole of PID at one half of switching fre-
transfer function can be expressed as: quency:

D(s)=
1
3
(1+
2p3F )( 2p3F )
s
1+
s
Z1 Z2
FP3 = fS/2 ---(23)

The Bode plot of power stage and proposed PID com-

s
s3Rf13(CC1 +C )
C2
(1+ 2p3F )(1+ 2p3F
s
P2) P3
pensator is shown in Figure 11.

---(14)
The compensator has two zeros and three poles.
Power -40dB
1
FZ1 = ---(15) Stage
2p3RC13CC1
1 Fpo Fzo
FZ2 = ---(16)
2p3Cf33(Rf1+Rf3)
FP1 = 0 -20dB
Loop
1 Gain
FP2 = ---(17)
2p3Rf33Cf3
-20dB
1 Fo
FP3 = ---(18)
CC13CC2
2p3RC13
CC1+CC2
-40dB
The type III compensator is usually designed by selec-
tion of location of F Z1, FZ2, F P2 and FP3 in order to get the PID
desired zero crossover frequency and enough phase Compensator
margin. If gm3ZC> 1, equation (13) will change its polar-
ity and a 180 degree phase shift will be introduced. The -20dB -20dB
system will become unstable. Therefore, a careful se-
lection of ZC has to be made. It is verified that the follow- Fz1
ing restriction has to be followed: Fz2 Fp2 Fp3 = fs/2
2
RC1 >> g m (mandatory); Figure 11 - The Bode plot of the buck converter
1 power stage, the desired loop gain
Rf1 ?? Rf2 ?? Rf3 > g m (desirable) ---(19) and PID compensator (method A).
Where Rf1 ?? Rf2 ?? Rf3 are the parallel resistance of Rf1,
Rf2 and Rf3. The zero crossover frequency FO is determined by the
following equation:
5.2) Type III (PID) Compensator Design Method A
VOSC 32p3FO3L3COUT
If the zero caused by ESR is less than half of the switch- Cf3 = ---(24)
VIN3RC1
ing frequency, that is FPO<FO<FZO<fS/2, then the follow-
ing design method can be used.

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 APPLICATION NOTE AN-1043

5V
D1
1N4148 L1

1uH
D2 C2 C1
1N4148 2x 10TPB100ML, 47uF
100uF, 55mV Tantalum
C3 C4 C5
1uF 1uF 0.1uF

Vcc Vc
Q1
HDrv
IRF7457 L2
U1
SS 3.3V
C8 3.3uH
IRU3037 Q2
@ 10A
0.1uF LDrv C7
IRF7460 Poscap, 2x 6TPC150M
150uF, ESR
40mV Each
Comp Rf1
Fb
11.7K, 1%
Gnd Rf3
Cf3
Rf2 2.2nF 2.74K
7.15K, 1%
Cc1 Rc1
4.7nF 10K
Cc2
150pF

Figure 12 - An example of IRU3037 controlled buck converter

with PID compensation method A.

5.3) Design Example of PID Compensator Method A Step 3 - Determine the zero crossover frequency and
Step 1 - Collect system parameters in Figure 12 such compensation type. Select desired zero-crossover fre-
as input voltage, output voltage, etc. and determine the quency.
switching frequency. Comparing with section 4.2, only fS fS
the output capacitor is changed. The output capacitor is FO [ ~
5 10
23150mF with 40mV each. The total ESR is:
If we select FO=30KHz and we have FPO<FZO<FO<fS/2,
ESR = 40mV/2 = 20mV
the PI compensator in section 4.2 can be chosen.
Total capacitor is:
COUT = 23150mF = 300mF Suppose FO=15KHz and FPO<FO<FZO<fS/2, then a PID
compensator with method A is chosen.
Step 2 - Determine the power stage poles and zeros.
1 Step 4 - Determine the desired location of zeros and
FPO = poles for the selected compensator. Select:
2p3 L3COUT
1 FZ1 = 0.753FPO = 3.75KHz
FPO = ≅ 5KHz FZ2 = FPO = 5KHz
2p3 3.3mH3300mF
FP2 = FZO = 26.5KHz
Zero caused by ESR:
1 1 fS 200KHz
FZO = FP3 = = = 100KHz
2p3ESR3COUT = 2p320mV323150mF 2 2

FZO ≅ 26.5KHz

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APPLICATION NOTES AN-1043

Step 5 - Calculate the real parameters-resistor and ca- 5.4) Type III (PID) Compensation Design Method B
pacitors for the selected compensator. If a ceramic capacitor is chosen, the zero caused by
2 ESR of capacitor is in the order of the switching fre-
Select RC1 so that RC1 >> g m
quency such as FZO>fS/2. The compensator method A
2 2 will not be very suitable. The compensation calculation
= ≅ 3.3K
gm 0.6mA / V can be based on the lead lag compensation (method B).
The Bode plot of power stage, loop gain, PID compensa-
Select RC1 = 10K
tor method B and phase are shown in Figure 13.
Calculate CC1 and CC2 by setting FZ1=0.753FPO and
FP3=fS/2:
1 1
CC1 = = = 4.2nF
2p3FZ13RC1 2p33.75KHz310K
Select CC1 = 4.7nF Power
Stage
1 1
CC2 ≅ = = 159pF
2p3FP33RC1 2p3100KHz310K Fpo Fzo
Select CC2 = 150pF > 30pF(reasonable capacitor)
-20dB -40dB
Calculate capacitor Cf3 by using equation (24):
Loop -20dB
VOSC 32p3FO3L3COUT
Cf3 = Gain
VIN3RC1
1.2532p315KHz33.3mH3300mF
Cf3 = ≅ 2.3nF Fo
5V310K
Select Cf3=2.2nF
-40dB
Calculate Rf3 and Rf1 by setting FP2=FZO and FZ2=FPO:
1 1 PID
Rf3 = = = 2.73K -20dB
2p3Cf33FP2 2p32.2nF326.5KHz Compensator
Select Rf3 = 2.74K
-20dB
1
Rf1 = - Rf3
2p3Cf33FZ2 Fz1 Fp3 = fs/2
Fz2 Fp2
1
Rf1 = - 2.74K = 11.7K
2p32.2nF35KHz
Select Rf1 = 11.7K Phase of PID Phase Boost
Compensator
Calculate Rf2:
VREF
Rf2 = 3 Rf1 Figure 13 - Bode plot of buck converter
VOUT - VREF
with PID compensator method B.
1.25
Rf2 = 311.7K = 7.13K
3.3 - 1.25 In the bold outline area of Figure 13, the PID compensa-
Select Rf2 = 7.15K, 1% tor can be seen as lead-lag compensation. It is known
that the lead-lag compensation can give a maximum
Check: phase boost at frequency.
Rf1 ?? Rf2 ?? Rf3 = 11.7K ?? 7.15K ?? 2.74K F= FP23FZ2 ---(25)
Rf1 ?? Rf2 ?? Rf3 ≅ 1.7K > 1/gm = 1.6K
If Rf1 ?? Rf2 ?? Rf3<1/gm, then iteration may be required by
going back and selecting a larger RC1.

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 APPLICATION NOTE AN-1043

The maximum phase gain will be generated, that is: The second zero of PID compensator can be calculated
by:
(
FP2 - FZ2
uMAX = Sin-1 FP2 + FZ2 ) ---(26) FZ2 = FO3
1 - SinuMAX
1 + SinuMAX
---(29)

One of the design strategies is that we can set the maxi- The second pole of compensator is given by:
mum phase boost occurring at zero-cross over frequency,
that is: 1 + SinuMAX
FP2 = FO3 ---(30)
1 - SinuMAX
FO = FP23FZ2 ---(27) The other zeroes and poles of compensator can be set
Suppose uMARGIN is the desired phase margin and 60° is by:
typical value. Parameter f is the phase of power stage Select FZ1 by FZ1<FZ2 and FZ1<FPO ---(31)
at zero crossover frequency. The required phase boost FP3 = FS/2 ---(32)
from PID compensator is set by:
The zero crossover frequency is determined by the fol-
uMAX = uMARGIN - f ---(28) lowing:
Because f ≅ 0 and uMAX ≅ uMARGIN. 2p3FO3L3COUT VOSC
Cf3 = 3 ---(33)
RC1 VIN

5V
D1
1N4148 L1

1uH
D2 C2 C1
1N4148 2x 10TPB100ML, 47uF
100uF, 55mV Tantalum
C3 C4 C5
1uF 1uF 0.1uF

Vcc Vc
Q1
HDrv
IRF7457 L2
U1
SS 3.3V
C8 3.3uH
IRU3037 @ 10A
0.1uF Q2
LDrv C7
IRF7460 10x 22uF
ESR, 10mV Each
Comp Rf1
Fb
27.4K
Gnd Rf3
Cf3
1nF 2.15K
Rf2
Rc1 16.7K, 1%
Cc1
3.3nF 20K
Cc2
82pF

Figure 14 - Example of IRU3037 controlled buck converter with ceramic capacitors

and PID compensator method B.

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APPLICATION NOTES AN-1043

5.5) Design Example of IRU3037 with Ceramic Ca- Step 5 - Calculate the real parameters-resistor and ca-
pacitor and PID Compensator Method B pacitors of compensator. Select RC1:
Step 1 - Collect system parameters in Figure 14 and
RC1 >> 2/gm = 2/0.6mmho ≅ 3.3K
determine switching frequency. Comparing with section
4.2 output capacitor is 10 ceramic cap with 22mF, 10mV Select RC1 = 20K
ESR. Total capacitance is: Calculate:
COUT = 10322mF = 220mF 1 1
CC1 = 2p3FZ13RC1 = 2p32.68KHz320K ≅ 3nF
ESR = 10mV/10 = 1mV
Step 2 - Determine the power stage poles and zeros. Select CC1 = 3.3nF

1 Calculate:
FPO =
2p3 L3COUT 1 1
1 CC2 = 2p3FP33RC1 = 2p3100KHz320K ≅ 80pF
FPO = ≅ 5.9Hz
2p3 3.3mH3220mF Select CC2 = 82pF

1
FZO = Calculate Cf3 based on location of zero crossover fre-
2p3ESR3COUT
quency:
1
FZO = ≅ 723KHz 2p3FO3L3COUT VOSC
2p31mV3220mF Cf3 = 3
RC1 VIN
Step 3 - Determine the zero crossover frequency and
2p320K33.3mH3220mF 1.25V
compensation type. Select zero crossover frequency as: Cf3 = 3 ≅ 1.14nF
20K 5V
fS 200KHz
FO = = = 20KHz Select Cf3 = 1nF
10 10

Because FPO< FO< fS/2 << FZO, we select the PID com- Calculate:
pensation based on lead lag (method B).
1 1
Rf3 = = 2p31nF374KHz ≅ 2.15K
2p3Cf33FP2
Step 4 - Determine the desired location of zeros and
poles for PID compensator. The desired phase margin Select Rf3 = 2.15K
is:
uMAX ≅ uMARGIN = 608 Calculate:
1
Then: Rf1 = - Rf3
2p3Cf33FZ2
1 - SinuMAX 1
FZ2 = FO3 ≅ 5.36KHz Rf1 = 2p31nF35.36KHz - 2.15K ≅ 27.5K
1 + SinuMAX

1 + SinuMAX Select Rf1 = 27.4K, 1%

FP2 = FO3 ≅ 74KHz
1 - SinuMAX
For DC regulation, calculate:
Select FZ1<FZ2 and FZ1<FPO
Select FZ1 = 0.53FZ2 = 0.535.36KHz ≅ 2.68KHz VREF 1.25
Rf2 = 3Rf1 = 327.4K ≅ 16.7K
Select FP3 = fS/2 = 100KHz VO-V REF 3.3-1.25
Select Rf2 = 16.7K, 1%

Check:
Rf1 ?? Rf2 ?? Rf3 = 27.5K ?? 16.7 ?? 2.15K ≅ 1.8K
Rf1 ?? Rf2 ?? Rf3 > 1/gm = 1.6K

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 APPLICATION NOTE AN-1043

Conclusion References
The control loop design based on transconductance [1] D. Maksimovic, R. Erickson, “Advances in Averaged
amplifier is proposed for buck converter. For most of buck Switch Modeling and Simulation” 2.4MB slides from
converter with electrolytic capacitor and low performance 3 hour tutorial seminar presented at the IEEE Power
tantalum capacitors, a simple type II (PI) compensator Electronics Specialists Conference, June 1999,
can be employed. For ceramic output capacitors, a type Charleston, South Carolina.
III or PID compensator is usually required. Although
IRU3037 controlled circuits are taken as an example in
this application note, the proposed design method also
applies to other IC applications such as IRU3046 or
IRU3055 controlled multi-phase buck converters.

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