You are on page 1of 59

A B C D E

1 1

ACLU1&ACLU2
(G40-70 & G50-70)

2 2

NM-A271 Rev 1.0 Schematic

Intel Haswell/Broadwell U-Processor with DDRIIIL + AMD Jet-LE/Topaz-XT GPU

3 3

2013-12-17
REV:1.0

4 4

Security Classification
Classification LC Future Center Secret Data Title
Issued Date 2013/08/08 Deciphered Date 2013/08/05 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 1 of 59
A B C D E
A B C D E

LCFC confidential File Name : ACLU1

AMD Jet-LE / Topaz-XT


S3 Package: 23mmX23mm PCI-Express
Page 18~24 PCIe Port5
4x Gen2 Memory BUS (DDR3L)
Dual Channel DDR3L-SO-DIMM X2
Page 14,15
VRAM 256/128*16
1
1.35V DDR3L 1600 MT/s 1

DDR3L*8 4GB/2GB/1GB UP TO 8G x 2
Page 25~26

HDMI USB Left


HDMI Conn.
Page 34 USB 3.0 1x
USB 3.0 Port1
USB 2.0 Port1
DP to VGA DPx2 Lane USB 2.0 2x
VGA Conn.
Page 36 Page 35 Parade PS8613 Intel MCP USB 2.0 Port2
Page 41
eDP x2 Lane
eDP Conn
USB 2.0 1x Touch Screen
USB2.0 1x
Int. Camera Page 33 USB2.0 Port4
USB2.0 Port5

2
Haswell U 15W / 2

Int. MIC Conn. Broadwell U 15W


Page 33
USB2.0 1x USB Right
USB2.0 Port0
SATA HDD SATA Gen3
Page 42 SATA Port0 USB2.0 1x
BGA-1168 Cardreader Realtek SD/MMC Conn.
40mm*24mm RTS5170
SATA ODD SATA Gen1 USB2.0 Port3
USB Board
Page 42 SATA Port1

USB 2.0 1x
LAN Realtek NGFF Card
RJ45 Conn. PCIe 1x PCIe 1x WLAN&BT
Page 38
RTL8111GUL (1G) PCIe Port4
RTL8106EUL (10M/100M) Page 40 USB2.0 Port6
3 3
Page 37 PCIe Port3
Sub-board ( for 14")
HD Audio SPI BUS SPI ROM
Page 3~13
8MB Page 07 POWER BOARD

Codec SPI ROM 4MB USB Board


SPK Conn. for reserve
Conexant CX20752 Page 07
Page 43
Page 43

EC
ITE IT8586E-LQFP Sub-board ( for 15")
Page 44

HP&Mic Combo Conn. POWER BOARD

USB Board USB Board


Touch Pad Int.KBD Thermal Sensor
4 Page 45 Page 45 NCT7718W 4
Page 39
ODD Board

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Block Diagram


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 2 of 59
A B C D E
A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )


SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Power Plane Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+1.5VS
+1.35VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1
+1.05VS 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+3VALW +0.675VS
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
B+ +3VALW_PCH CPU_CORE

+5VALW +1.35V S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF

+VGA_CORE
State +3VGS
+1.8VGS
+1.35VGS
+0.95VGS
USB Port Table BOM Structure Table
USB 2.0 USB 3.0 BOM Structure BTO Item
EHCI1 XHCI Not stuff
@
S0 O O O O O 0 USB Port (Right Side) 100M@ 100M LAN Part
14@ For 14" part
1 USB Port1 (Left Side) 1 USB Port1 (Left Side) For 15" part
15@
S3 O O O O X 2 USB Port2 (Left Side) 2 AOAC@ AOAC support part
2 GIGA@ GIGA LAN Part 2
3 Cardreader 3 For AMD Jet GPU part
S3 JET@
Battery only O O O O X 4 TOUCH PANEL 4 ME@ ME part(connector, hole)
PX@ Discrete GPU SKU part
5 Camera For VRAM RankA part
RANKA@
6 RANKB@ For VRAM RankB part
S5 S4/AC Only O O O X X NGFF(WLAN)
TOPAZ@ For AMD Topaz GPU part
7 For support touch panel sku part
TS@
S5 S4 UMA@ UMA SKU part
Battery only O X X X X H2@ Hynix 128Mx16 VRAM part
H4@ Hynix 256Mx16 VRAM part
S5 S4 M2@ Micron 128Mx16 VRAM part
AC & Battery X X X X X M4@ Micron 256Mx16 VRAM part
don't exist S2@ Samsung 128Mx16 VRAM part
PCIE PORT LIST S4@ Samsung 256Mx16 VRAM part
H2GX8@ Hynix 128Mx16 VRAM x8pcs sku
SMBUS Control Table Port Device
3 H4GX4@ Hynix 256Mx16 VRAM x4pcs sku 3

WLAN Thermal TP
1 M4GX4@ Micron 256Mx16 VRAM x4pcs sku
SOURCE VGA BATT IT8586E SODIMM PCH charger
WiMAX Sensor Module 2 CD@ Cost down part
3 LAN
4 WLAN
EC_SMB_CK1 IT8586E V 5
EC_SMB_DA1 +3VALW X V +3VALW X X X X X V Discrete GPU
6
EC_SMB_CK2 IT8586E V V
X X V V X X
EC_SMB_DA2 +3VS +3VGS X +3VS +3VS +3VALW_PCH

PCH_SMB_CLK PCH
PCH_SMB_DATA +3VALW_PCH X X X V V X V X X
+3VS +3VS +3VALW_PCH

EC SM Bus1 address EC SM Bus2 address PCH SM Bus address


Device Address
Device Device Address DDR DIMMA 1010 000Xb
4 4

Smart Battery 0X16 Thermal Sensor NCT7718W 1001_100xb DDR DIMMB 1010 010Xb
Charger 0001 0010 b VGA 0x41(default) Wlan Rsvd
PCH need to update

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Notes List


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 3 of 59
A B C D E
5 4 3 2 1

UC1A HSW_ULT_DDR3L

HDMI_TX2- C54 C45 CPU_EDP_TX0-


34 HDMI_TX2- C55 DDI1_TXN0 EDP_TXN0 B46 CPU_EDP_TX0- 33
HDMI D2 HDMI_TX2+ CPU_EDP_TX0+
D 34 HDMI_TX2+ B58 DDI1_TXP0 EDP_TXP0 A47 CPU_EDP_TX0+ 33 D
HDMI_TX1- CPU_EDP_TX1-
34 HDMI_TX1- HDMI_TX1+ C58 DDI1_TXN1 EDP_TXN1 B47 CPU_EDP_TX1+ CPU_EDP_TX1- 33
HDMI D1 34 HDMI_TX1+ HDMI_TX0- B55 DDI1_TXP1 EDP_TXP1 CPU_EDP_TX1+ 33
34 HDMI_TX0- HDMI_TX0+ A55 DDI1_TXN2 C47
HDMI D0 34 HDMI_TX0+ HDMI_CLK- A57 DDI1_TXP2 EDP_TXN2 C46
34 HDMI_CLK- B57 DDI1_TXN3 EDP_TXP2 A49
HDMI CLK HDMI_CLK+
34 HDMI_CLK+ DDI1_TXP3 DDI EDP EDP_TXN3 B49
VGA_TX0- C51 EDP_TXP3
35 VGA_TX0- VGA_TX0+ C50 DDI2_TXN0 A45 CPU_EDP_AUX# +VCCIOA_OUT +VCCIOA_OUT & EDP_COMP :
35 VGA_TX0+ C53 DDI2_TXP0 EDP_AUXN B45 CPU_EDP_AUX# 33
DP TO VGA Converter VGA_TX1- CPU_EDP_AUX Trace Width: 20mil
35 VGA_TX1- VGA_TX1+ B54 DDI2_TXN1 EDP_AUXP CPU_EDP_AUX 33
35 VGA_TX1+ C49 DDI2_TXP1 D20 1 2 24.9_0402_1%
Space: 25mil
EDP_COMP RC1
B50 DDI2_TXN2 EDP_RCOMP A43 LCD_BKLT_CTRL_R RC2 1 @ 2 0_0402_5% Max length: 100mil
A53 DDI2_TXP2 EDP_DISP_UTIL INVT_PWM 33
B53 DDI2_TXN3
DDI2_TXP3

1 OF 19
HASWELL-ULT-DDR3L_BGA1168

+3VS

RPC19
DDPC_CLK 1 8
DDPC_DATA 2 7
DDPB_CLK 3 6
UC1I HSW_ULT_DDR3L
DDPB_DATA 4 5

C 2.2K_0804_8P4R_5% C

PCH_EDP_PWM B8 B9 DDPB_CLK DDPx_CTRLDATA


33 PCH_EDP_PWM PCH_ENBKL A9 EDP_BKLCTL DDPB_CTRLCLK C9 DDPB_DATA DDPB_CLK 34
33 PCH_ENBKL EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA DDPB_DATA 34 The signal has a weak internal pull-down.
PCH_ENVDD C6 D9 DDPC_CLK
33 PCH_ENVDD EDP_VDDEN DDPC_CTRLCLK
DDPC_CTRLDATA
D11 DDPC_DATA * H
L
Port is detected.
Port is not detected.

PCI_PIRQA# U6
PCI_PIRQB# P4 PIRQA/GPIO77 C5
PCI_PIRQC# N4 PIRQB/GPIO78 DDPB_AUXN B6 VGA_AUX#
N2 PIRQC/GPIO79 DISPLAY DDPC_AUXN B5 VGA_AUX# 35
PCI_PIRQD#
@ PAD 1 AD4 PIRQD/GPIO80 DDPB_AUXP A6 VGA_AUX
TC1 PME PCIE DDPC_AUXP VGA_AUX 35
BOARD_ID3 U7
9 BOARD_ID3 GPIO52 L1 GPIO55
1 20 GPIO52 GPIO52
PXS_PWREN RC7 PX@ 2 1K_0402_5% PXS_PWREN_R L3 C8 HDMI_HPD
23,57,58 PXS_PWREN 1 GPIO54 DDPB_HPD HDMI_HPD 34
PXS_RST# RC8 PX@ 2 0_0402_5% PXS_RST#_R R5 A8 VGA_HPD
19 PXS_RST# GPIO53 L4 GPIO51 DDPC_HPD D6 EDP_HPD VGA_HPD 35
20 GPIO53 GPIO53 EDP_HPD

1
RC37 After confirm with vendor, HPD
1

D 9 OF 19 100K_0402_5%
RC1701 @ 2 2 QC13 HASWELL-ULT-DDR3L_BGA1168 @
has internal pull-down ~100K at
44 VGA_GATE# G PS8613, just reserve in case.
0_0402_5% 2N7002KW_SOT323-3

2
1 RC37 can be removed next phase
CC96 @ S
if no issue.
3

.1U_0402_10V6-K
@
2
B B

+3VS +3VS

1
RC9

2
+3VS 1M_0402_5%

G
@

2
RPC1
1 8 PCI_PIRQA# EDP_HPD @ 3 1 QC4
CPU_EDP_HPD 33

D
2 7 PCI_PIRQB#
3 6 PCI_PIRQC# 2N7002KW_SOT323-3
4 5 PCI_PIRQD#

1
10K_0804_8P4R_5% RC13
100K_0402_5%

+3VS @

2
RC16 1 2

RC10 1 2 10K_0402_5% GPIO52 0_0402_5%

RC11 1 2 10K_0402_5% GPIO53

RC14 1 2 10K_0402_5% PXS_PWREN_R

RC15 1 2 10K_0402_5% PXS_RST#_R

A A

Reserve for NV GPU


RC27 1 @ 2 10K_0402_5% GPIO52

RC30 1 @ 2 10K_0402_5% GPIO53

Security Classification LC Future Center Secret Data Title


RC17 2 1 100K_0402_5% PXS_PWREN_R

RC18 1 @ 2 10K_0402_5% PXS_RST#_R


Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (DDI,EDP)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 4 of 59
5 4 3 2 1
5 4 3 2 1

UC1B HSW_ULT_DDR3L

+1.05V_VCCST

TC2 @ 1 PROC_DETECT# D61


PROC_DETECT

1
D TC3 @ 1 CATERR# K61 MISC D
RC19 H_PECI N62 CATERR J62 XDP_PRDY# 1 PAD @
44 H_PECI PECI PRDY K62 1 TC4
62_0402_1% XDP_PREQ# PAD @
PREQ E60 XDP_TCLK 1 TC5
PAD @
PROC_TCK TC6
E61 XDP_TMS 1 PAD @

2
1 2 RC20 H_PROCHOT#_R K63 JTAG PROC_TMS E59 XDP_TRST# 1 TC7
56_0402_5% PAD @
44,51,52 H_PROCHOT# PROCHOT PROC_TRST F63 1 TC8
THERMAL XDP_TDI PAD @
PROC_TDI TC9
F62 XDP_TDO 1 PAD @
PROC_TDO TC10
+1.35V 1 2 RC21 CPU_PROCPWRGD C61
10K_0402_5% PROCPWRGD PWR
J60 XDP_BPM0# 1 PAD @
BPM#0 TC11

1
H60 XDP_BPM1# 1 PAD @
BPM#1 H61 1 TC12
RC22 XDP_BPM2# PAD @
BPM#2 H62 TC13
470_0402_5% XDP_BPM3# 1 PAD @
SM_RCOMP_0 AU60 BPM#3 K59 XDP_BPM4# 1 TC14
PAD @
SM_RCOMP0 DDR3L BPM#4 TC15
SM_RCOMP_1 AV60 H63 XDP_BPM5# 1 PAD @
TC16

2
SM_RCOMP_2 AU61 SM_RCOMP1 BPM#5 K60 XDP_BPM6# 1 PAD @
SM_RCOMP2 BPM#6 TC17
RC23 1 2 0_0402_5% CPU_DRAMRST#_R AV15 J61 XDP_BPM7# 1 PAD @
14,15 CPU_DRAMRST# SM_DRAMRST BPM#7 TC18
@ SM_PG_CNTL1 AV61
SM_PG_CNTL1
1
CC1 2 OF 19
0.01U_0402_25V7K HASWELL-ULT-DDR3L_BGA1168
2
C C

100_0402_1% 2 1 RC24 SM_RCOMP_2

121_0402_1% 2 1 RC25 SM_RCOMP_1


+3VALW
200_0402_1% 2 1 RC26 SM_RCOMP_0

1
RC28
100K_0402_5%

2
CPU_DRAMPG_CNTL 55
+1.35V
B B

1
C +1.35V
RC3 1 2 2 QC14
1K_0402_5% B
E

3
MMBT3904WH_SOT323-3 1 QC5
D
RC31 1 2 0_0402_5% 2
SM_PG_CNTL1 @ G
1 S
CD1 PJA138K_SOT23-3 RD1 1 2 66.5_0402_1% DDRA_ODT0
3 DDRA_ODT0 14
2

.1U_0402_10V6-K
RC29 @ DDR_ODT RD2 1 2 66.5_0402_1% DDRA_ODT1
2 DDRA_ODT1 14
10K_0402_5%
@ RD3 1 2 66.5_0402_1% DDRB_ODT0
DDRB_ODT0 15
1

RD4 1 2 66.5_0402_1% DDRB_ODT1


DDRB_ODT1 15

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (MISC,THERMAL,JATG)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 5 of 59
5 4 3 2 1
5 4 3 2 1

UC1C HSW_ULT_DDR3L UC1D HSW_ULT_DDR3L

14 DDRA_DQ[0..15]
DDRA_DQ0 AH63 AU37
AH62 SA_DQ0 SA_CLK#0 AV37 DDRA_CLK0# 14 14 DDRA_DQ[32..47] AY31 AM38
DDRA_DQ1 DDRA_DQ32
AK63 SA_DQ1 SA_CLK0 AW36 DDRA_CLK0 14 AW31 SB_DQ0 SB_CK#0 AN38 DDRB_CLK0# 15
DDRA_DQ2 DDRA_DQ33
D AK62 SA_DQ2 SA_CLK#1 AY36 DDRA_CLK1# 14 AY29 SB_DQ1 SB_CK0 AK38 DDRB_CLK0 15 D
DDRA_DQ3 DDRA_DQ34
SA_DQ3 SA_CLK1 DDRA_CLK1 14 SB_DQ2 SB_CK#1 DDRB_CLK1# 15
DDRA_DQ4 AH61 DDRA_DQ35 AW29 AL38
SA_DQ4 SB_DQ3 SB_CK1 DDRB_CLK1 15
DDRA_DQ5 AH60 AU43 DDRA_DQ36 AV31
AK61 SA_DQ5 SA_CKE0 AW43 DDRA_CKE0 14 AU31 SB_DQ4 AY49
DDRA_DQ6 DDRA_DQ37
AK60 SA_DQ6 SA_CKE1 AY42 DDRA_CKE1 14 AV29 SB_DQ5 SB_CKE0 AU50 DDRB_CKE0 15
DDRA_DQ7 DDRA_DQ38
AM63 SA_DQ7 SA_CKE2 AY43 AU29 SB_DQ6 SB_CKE1 AW49 DDRB_CKE1 15
DDRA_DQ8 DDRA_DQ39
DDRA_DQ9 AM62 SA_DQ8 SA_CKE3 DDRA_DQ40 AY27 SB_DQ7 SB_CKE2 AV50
DDRA_DQ10 AP63 SA_DQ9 AP33 DDRA_DQ41 AW27 SB_DQ8 SB_CKE3
AP62 SA_DQ10 SA_CS#0 AR32 DDRA_CS0# 14 AY25 SB_DQ9 AM32
DDRA_DQ11 DDRA_DQ42
SA_DQ11 SA_CS#1 DDRA_CS1# 14 SB_DQ10 SB_CS#0 DDRB_CS0# 15
DDRA_DQ12 AM61 DDRA_DQ43 AW25 AK32
AM60 SA_DQ12 AP32 1 AV27 SB_DQ11 SB_CS#1 DDRB_CS1# 15
DDRA_DQ13 SA_ODT0 PAD @ DDRA_DQ44
SA_DQ13 SA_ODT0 TC19 SB_DQ12
DDRA_DQ14 AP61 DDRA_DQ45 AU27 AL32 SB_ODT0 1 PAD @
AP60 SA_DQ14 AY34 AV25 SB_DQ13 SB_ODT0 TC20
DDRA_DQ15 DDRA_DQ46
15 DDRB_DQ[0..15] AP58 SA_DQ15 SA_RAS AW34 DDRA_RAS# 14 AU25 SB_DQ14 AM35
DDRB_DQ0 DDRA_DQ47
SA_DQ16 SA_WE DDRA_WE# 14 15 DDRB_DQ[32..47] SB_DQ15 SB_RAS DDRB_RAS# 15
DDRB_DQ1 AR58 AU34 DDRB_DQ32 AM29 AK35
SA_DQ17 SA_CAS DDRA_CAS# 14 SB_DQ16 SB_WE DDRB_WE# 15
DDRB_DQ2 AM57 DDRB_DQ33 AK29 AM33
SA_DQ18 SB_DQ17 SB_CAS DDRB_CAS# 15
DDRB_DQ3 AK57 AU35 DDRB_DQ34 AL28
SA_DQ19 SA_BA0 DDRA_BS0# 14 SB_DQ18
DDRB_DQ4 AL58 AV35 DDRB_DQ35 AK28 AL35
SA_DQ20 SA_BA1 DDRA_BS1# 14 SB_DQ19 SB_BA0 DDRB_BS0# 15
DDRB_DQ5 AK58 AY41 DDRB_DQ36 AR29 AM36
SA_DQ21 SA_BA2 DDRA_BS2# 14 SB_DQ20 SB_BA1 DDRB_BS1# 15
DDRB_DQ6 AR57 DDRB_DQ37 AN29 AU49
SA_DQ22 DDRA_MA[0..15] 14 SB_DQ21 SB_BA2 DDRB_BS2# 15
DDRB_DQ7 AN57 AU36 DDRA_MA0 DDRB_DQ38 AR28 4 OF 19
SA_DQ23 SA_MA0 SB_DQ22 DDRB_MA[0..15] 15
DDRB_DQ8 AP55 AY37 DDRA_MA1 DDRB_DQ39 AP28 AP40 DDRB_MA0
DDRB_DQ9 AR55 SA_DQ24 SA_MA1 AR38 DDRA_MA2 DDRB_DQ40 AN26 SB_DQ23 SB_MA0 AR40 DDRB_MA1
DDRB_DQ10 AM54 SA_DQ25 SA_MA2 AP36 DDRA_MA3 DDRB_DQ41 AR26 SB_DQ24 SB_MA1 AP42 DDRB_MA2
DDRB_DQ11 AK54 SA_DQ26 SA_MA3 AU39 DDRA_MA4 DDRB_DQ42 AR25 SB_DQ25 SB_MA2 AR42 DDRB_MA3
DDRB_DQ12 AL55 SA_DQ27 SA_MA4 AR36 DDRA_MA5 DDRB_DQ43 AP25 SB_DQ26 SB_MA3 AR45 DDRB_MA4
DDRB_DQ13 AK55 SA_DQ28 SA_MA5 AV40 DDRA_MA6 DDRB_DQ44 AK26 SB_DQ27 SB_MA4 AP45 DDRB_MA5
DDRB_DQ14 AR54 SA_DQ29 SA_MA6 AW39 DDRA_MA7 DDRB_DQ45 AM26 SB_DQ28 SB_MA5 AW46 DDRB_MA6
DDRB_DQ15 AN54 SA_DQ30 DDR CHANNEL A SA_MA7 AY39 DDRA_MA8 DDRB_DQ46 AK25 SB_DQ29 SB_MA6 AY46 DDRB_MA7
14 DDRA_DQ[16..31] SA_DQ31 SA_MA8 SB_DQ30 SB_MA7
DDRA_DQ16 AY58 AU40 DDRA_MA9 DDRB_DQ47 AL25 AY47 DDRB_MA8
SA_DQ32 SA_MA9 14 DDRA_DQ[48..63] SB_DQ31 SB_MA8
DDRA_DQ17 AW58 AP35 DDRA_MA10 DDRA_DQ48 AY23 DDR CHANNEL B AU46 DDRB_MA9
DDRA_DQ18 AY56 SA_DQ33 SA_MA10 AW41 DDRA_MA11 DDRA_DQ49 AW23 SB_DQ32 SB_MA9 AK36 DDRB_MA10
C DDRA_DQ19 AW56 SA_DQ34 SA_MA11 AU41 DDRA_MA12 DDRA_DQ50 AY21 SB_DQ33 SB_MA10 AV47 DDRB_MA11 C
DDRA_DQ20 AV58 SA_DQ35 SA_MA12 AR35 DDRA_MA13 DDRA_DQ51 AW21 SB_DQ34 SB_MA11 AU47 DDRB_MA12
DDRA_DQ21 AU58 SA_DQ36 SA_MA13 AV42 DDRA_MA14 DDRA_DQ52 AV23 SB_DQ35 SB_MA12 AK33 DDRB_MA13
DDRA_DQ22 AV56 SA_DQ37 SA_MA14 AU42 DDRA_MA15 DDRA_DQ53 AU23 SB_DQ36 SB_MA13 AR46 DDRB_MA14
DDRA_DQ23 AU56 SA_DQ38 SA_MA15 DDRA_DQ54 AV21 SB_DQ37 SB_MA14 AP46 DDRB_MA15
DDRA_DQ24 AY54 SA_DQ39 AJ61 DDRA_DQS#0 DDRA_DQ55 AU21 SB_DQ38 SB_MA15
DDRA_DQ25 AW54 SA_DQ40 SA_DQSN0 AN62 DDRA_DQS#1 DDRA_DQ56 AY19 SB_DQ39 AW30 DDRA_DQS#4
DDRA_DQ26 AY52 SA_DQ41 SA_DQSN1 AM58 DDRB_DQS#0 DDRA_DQ57 AW19 SB_DQ40 SB_DQSN0 AV26 DDRA_DQS#5
DDRA_DQ27 AW52 SA_DQ42 SA_DQSN2 AM55 DDRB_DQS#1 DDRA_DQ58 AY17 SB_DQ41 SB_DQSN1 AN28 DDRB_DQS#4
DDRA_DQ28 AV54 SA_DQ43 SA_DQSN3 AV57 DDRA_DQS#2 DDRA_DQ59 AW17 SB_DQ42 SB_DQSN2 AN25 DDRB_DQS#5
DDRA_DQ29 AU54 SA_DQ44 SA_DQSN4 AV53 DDRA_DQS#3 DDRA_DQ60 AV19 SB_DQ43 SB_DQSN3 AW22 DDRA_DQS#6
DDRA_DQ30 AV52 SA_DQ45 SA_DQSN5 AL43 DDRB_DQS#2 DDRA_DQ61 AU19 SB_DQ44 SB_DQSN4 AV18 DDRA_DQS#7
DDRA_DQ31 AU52 SA_DQ46 SA_DQSN6 AL48 DDRB_DQS#3 DDRA_DQ62 AV17 SB_DQ45 SB_DQSN5 AN21 DDRB_DQS#6
15 DDRB_DQ[16..31] SA_DQ47 SA_DQSN7 SB_DQ46 SB_DQSN6
DDRB_DQ16 AK40 DDRA_DQ63 AU17 AN18 DDRB_DQS#7
SA_DQ48 15 DDRB_DQ[48..63] SB_DQ47 SB_DQSN7
DDRB_DQ17 AK42 AJ62 DDRA_DQS0 DDRB_DQ48 AR21
DDRB_DQ18 AM43 SA_DQ49 SA_DQSP0 AN61 DDRA_DQS1 DDRB_DQ49 AR22 SB_DQ48 AV30 DDRA_DQS4
DDRB_DQ19 AM45 SA_DQ50 SA_DQSP1 AN58 DDRB_DQS0 DDRB_DQ50 AL21 SB_DQ49 SB_DQSP0 AW26 DDRA_DQS5
DDRB_DQ20 AK45 SA_DQ51 SA_DQSP2 AN55 DDRB_DQS1 DDRB_DQ51 AM22 SB_DQ50 SB_DQSP1 AM28 DDRB_DQS4
DDRB_DQ21 AK43 SA_DQ52 SA_DQSP3 AW57 DDRA_DQS2 DDRB_DQ52 AN22 SB_DQ51 SB_DQSP2 AM25 DDRB_DQS5
DDRB_DQ22 AM40 SA_DQ53 SA_DQSP4 AW53 DDRA_DQS3 DDRB_DQ53 AP21 SB_DQ52 SB_DQSP3 AV22 DDRA_DQS6
DDRB_DQ23 AM42 SA_DQ54 SA_DQSP5 AL42 DDRB_DQS2 DDRB_DQ54 AK21 SB_DQ53 SB_DQSP4 AW18 DDRA_DQS7
DDRB_DQ24 AM46 SA_DQ55 SA_DQSP6 AL49 DDRB_DQS3 DDRB_DQ55 AK22 SB_DQ54 SB_DQSP5 AM21 DDRB_DQS6
DDRB_DQ25 AK46 SA_DQ56 SA_DQSP7 DDRB_DQ56 AN20 SB_DQ55 SB_DQSP6 AM18 DDRB_DQS7
DDRB_DQ26 AM49 SA_DQ57 AP49 DDRB_DQ57 AR20 SB_DQ56 SB_DQSP7
SA_DQ58 SM_VREF_CA DDR_SM_VREFCA 14 SB_DQ57
DDRB_DQ27 AK49 AR51 DDRB_DQ58 AK18
SA_DQ59 SM_VREF_DQ0 DDR_SA_VREFDQ 14 SB_DQ58
DDRB_DQ28 AM48 AP51 DDRB_DQ59 AL18
SA_DQ60 SM_VREF_DQ1 DDR_SB_VREFDQ 15 SB_DQ59
DDRB_DQ29 AK48 DDRB_DQ60 AK20
DDRB_DQ30 AM51 SA_DQ61 DDRB_DQ61 AM20 SB_DQ60
SA_DQ62 SMVREF SB_DQ61
DDRB_DQ31 AK51 WIDTH:20MIL DDRB_DQ62 AR18
SA_DQ63 DDRB_DQ63 AP18 SB_DQ62
SPACING: 20MIL SB_DQ63

B B

DDRA_DQS#[0..7] DDRB_DQS#[0..7]
DDRA_DQS#[0..7] 14 DDRB_DQS#[0..7] 15
DDRA_DQS[0..7] DDRB_DQS[0..7]
DDRA_DQS[0..7] 14 DDRB_DQS[0..7] 15
3 OF 19
HASWELL-ULT-DDR3L_BGA1168 HASWELL-ULT-DDR3L_BGA1168

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (DDR3L)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 6 of 59
5 4 3 2 1
5 4 3 2 1

RTC_X1

+3VS
RC32 2 1 10M_0402_5% RTC_X2 1 RPC2

1
CC3 JME1 ODD_DETECT# 1 8
VCCRTC 1U_0402_10V6K SHORT PADS SATA0GP 2 7
YC1 1 2 @ SATA2GP 3 6

2
2 SATA3GP 4 5
2 32.768KHZ_12.5PF_200458-PG14 2 RC33 1 2 20K_0402_1% SRTC_RST#
RC34 1 2 20K_0402_1% RTC_RST# 10K_0804_8P4R_5%
CC4 CC5
15P_0402_50V8J 18P_0402_50V8J 1

1
1 1 CC6 JCMOS1
1U_0402_10V6K SHORT PADS
@

2
2
D D
CRYSTAL +3VALW_PCH
1, Space 15MIL
2, No trace under crystal
3, Place on oppsosit side of MCP for temp influence SML0_CLK RC35 2 1 2.2K_0402_5%

SML0_DATA RC36 2 1 2.2K_0402_5%


UC1E HSW_ULT_DDR3L

VCCRTC RPC22
RTC_X1 AW5 SMB_ALERT# 1 8
RTC_X2 AY5 RTCX1 SML0_ALERT# 2 7
RC39 2 1 1M_0402_5% SM_INTRUDER# AU6 RTCX2 J5 SATA_PRX_DTX_N0 SML1_ALERT# 3 6
INTRUDER SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0 42
RC41 2 1 330K_0402_5% INTVRMEN AV7 H5 SATA_PRX_DTX_P0 SATA_PRX_DTX_P0 42 4 5
AV6 INTVRMEN SATA_RP0/PERP6_L3 B15
SRTC_RST#
SRTCRST
RTC
SATA_TN0/PETN6_L3
SATA_PTX_DRX_N0
SATA_PTX_DRX_N0 42 HDD
INTVRMEN RTC_RST# AU7 A15 SATA_PTX_DRX_P0 10K_0804_8P4R_5%
RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0 42
* H Integrated VRM enable (Default)
L Integrated VRM disable SATA_RN1/PERN6_L2
J8 SATA_PRX_DTX_N1 SATA_PRX_DTX_N1 42
H8 SATA_PRX_DTX_P1
(INTVRMEN should always be pull high.) SATA_RP1/PERP6_L2 A17
SATA_PRX_DTX_P1 42
SATA_TN1/PETN6_L2
SATA_PTX_DRX_N1
SATA_PTX_DRX_N1 42 ODD
B17 SATA_PTX_DRX_P1
SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 42
RC42 1 2 33_0402_5% HDA_BCLK AW8 J6
43 HDA_BITCLK_AUDIO HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1
RC43 1 2 33_0402_5% HDA_SYNC AV11 H6
43 HDA_SYNC_AUDIO HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1
RC44 1 2 33_0402_5% HDA_RST# AU8 B14
43 HDA_RST_AUDIO# HDA_RST/I2S_MCLK AUDIO SATA SATA_TN2/PETN6_L1
HDA_SDIN0 AY10 C15
43 HDA_SDIN0 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1
AU12
+3VALW_PCH RC45 1 2 33_0402_5% HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
43 HDA_SDOUT_AUDIO HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0
RC46 1 2 0_0402_5% TC21 @ 1 AW10 E5
44 ME_FLASH HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0
@ TC22 @ 1 AV10 C17
RC47 1 @ 2 1K_0402_5% HDA_SDOUT TC23 @ 1 AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17
I2S1_SCLK SATA_TP3/PETP6_L0

HDA_SDO This signal has a weak internal pull-down. V1 SATA0GP


SATA0GP/GPIO34 U1 ODD_DETECT#
* 0 = Enable security measures defined in the Flash Descriptor.
1 = Disable Flash Descriptor Security(override). This strap
SATA1GP/GPIO35
SATA2GP/GPIO36
V6 SATA2GP
ODD_DETECT# 42
IREF&RCOMP
AC1 SATA3GP +1.05VS_PSATA3PLL Width: 12-15Mil
should only be asserted high during external pull-up in TC24 @ 1 PCH_JTAG_TRST# AU62 SATA3GP/GPIO37
manufacturing/debug environments ONLY. PCH_TRST Space:12Mil
C TC25 @ 1 PCH_JTAG_TCK AE62 A12 C
TC26 @ 1 PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11
Length: 500Mil
TC28 @ 1 PCH_JTAG_TDO AE61 PCH_TDI RSVD3 K10
TC30 @ 1 PCH_JTAG_TMS AD62 PCH_TDO RSVD4 C12 SATA_RCOMP RC48 2 1 3.01K_0402_1%
For EMI PCH_TMS
JTAG
SATA_RCOMP
HDA_SDIN0 AL11 U3 SATALED# RC49 1 @ 2 10K_0402_5%
RSVD1 SATALED +3VS
TC32 @ 1 AC4
TC33 @ 1 PCH_JTAGX AE63 RSVD2
TC34 @ 1 AV2 JTAGX
1 RSVD0
@
CC7
10P_0402_50V8J
2
5 OF 19
HASWELL-ULT-DDR3L_BGA1168

UC1G HSW_ULT_DDR3L

AU14 AN2 SMB_ALERT#


44 LPC_AD0 LAD0 SMBALERT/GPIO11
AW12 AP2 PCH_SMB_CLK
44 LPC_AD1 LAD1 SMBCLK
AY12 LPC AH1 PCH_SMB_DATA
44 LPC_AD2 AW11 LAD2 SMBUS SMBDATA AL2 SML0_ALERT#
44 LPC_AD3 LAD3 SML0ALERT/GPIO60
AV12 AN1 SML0_CLK
44 LPC_FRAME# LFRAME SML0CLK AK1 SML0_DATA
SML0DATA AU4 SML1_ALERT#
SML1ALERT/PCHHOT/GPIO73 AU3 PCH_SML1_CLK
SPI_CLK_1 RC173 1 @ 2 33_0402_5% SML1CLK/GPIO75 AH3 PCH_SML1_DAT
SML1DATA/GPIO74 DIMM1, DIMM2, NGFF
SPI_CLK RC50 1 2 15_0402_5% SPI_CLK_R AA3
44 SPI_CLK SPI_CLK
SPI_CS0# RC51 1 2 0_0402_5% SPI_CS0#_R Y7 AF2
44 SPI_CS0# SPI_CS0 CL_CLK
SPI_CS1# RC174 1 @ 2 0_0402_5% SPI_CS1#_R Y4 AD2 +3VALW_PCH +3VS +3VS
SPI_SI_1 RC175 1 @ 2 33_0402_5% AC2 SPI_CS1 SPI C-LINK
CL_DATA AF4
SPI_SI RC52 1 2 15_0402_5% SPI_SI_R AA2 SPI_CS2 CL_RST
44 SPI_SI SPI_MOSI
SPI_SO RC53 1 2 15_0402_5% SPI_SO_R AA4
44 SPI_SO SPI_MISO
SPI_SO_1 RC177 1 @ 2 33_0402_5% SPI_WP#_R Y6
SPI_IO2

1
SPI_HOLD#_R AF1
B SPI_IO3 RC56 RC57 RC58 RC59
B

2
2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%

G
7 OF 19

2
HASWELL-ULT-DDR3L_BGA1168 PCH_SMB_CLK QC2A 6 1

S
+3V_SPI SMB_CLK_S3 14,15,40

D
2N7002KDWH_SOT363-6

5
G
1

RC60 RC61 PCH_SMB_DATA QC2B 3 4

S
SMB_DATA_S3 14,15,40
1K_0402_5% 1K_0402_5%

D
+3V_SPI 2N7002KDWH_SOT363-6
2

UC3
SPI_WP#_R RC54 1 @ 2 33_0402_5% SPI_WP# SPI_CS0# 1 8
CS# VCC
SPI_SO 2 7 SPI_HOLD# 1
SPI_HOLD#_R RC55 1 @ 2 33_0402_5% SPI_HOLD# DO HOLD# CC8
SPI_WP# 3 6 SPI_CLK
GPU, EC, Thermal Sensor
.1U_0402_10V6-K
WP# CLK
4 5 SPI_SI 2 +3VALW_PCH +3VS
GND DI

+3V_SPI W25Q64FVSSIG_SO8

1
RC62 RC63

2
2.2K_0402_5% 2.2K_0402_5%

G
1

+3V_SPI
RC179 RC180 UC6 @

2
1K_0402_5% 1K_0402_5%
@ @ SPI_CS1# 1 8 PCH_SML1_CLK QC3A 6 1

S
CS VCC EC_SMB_CK2 20,39,44

D
2

SPI_SO_1 2 7 SPI_HOLD#_1 1 2N7002KDWH_SOT363-6


DO(IO1) HOLD/RST(IO3)

5
A SPI_WP#_R RC176 1 @ 2 33_0402_5% SPI_WP#_1 CC97 A

G
SPI_WP#_1 3 6 SPI_CLK_1 .1U_0402_10V6-K
+3VALW_PCH +3V_SPI WP(IO2) CLK @
SPI_HOLD#_R RC178 1 @ 2 33_0402_5% SPI_HOLD#_1 4 5 SPI_SI_1 2
RC171 1 2 GND DI(IO0) PCH_SML1_DAT QC3B 3 4

S
EC_SMB_DA2 20,39,44
0_0402_5% W25Q32FVSSIG_SO8

D
+3VS 2N7002KDWH_SOT363-6

RC172 1 @ 2
0_0402_5%
Security Classification LC Future Center Secret Data Title
+3V_SPI
1. If support DS3, connect to +3VS and don't support EC mirror code; Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (RTC&AUDIO&SATA&SMBUS)
* 2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 7 of 59
5 4 3 2 1
5 4 3 2 1

+3VS RC71 2 1 1M_0402_5%

RPC3 YC2
1 8 PCIE_CLKREQ1#
2 7 PCIE_CLKREQ0# 2 3 XTAL24_OUT
3 6 PCIE_CLKREQ5# GND1 OSC2
4 5 XTAL24_IN 1 4
OSC1 GND2
10K_0804_8P4R_5% 1
1 24MHZ_6PF_7V24000032
RPC4 CC12 CC11
D D
1 8 LAN_CLKREQ# 4.7P_0402_50V8B 4.7P_0402_50V8B
2 7 WLAN_CLKREQ# 2
3 6 SYS_RESET# 2
UC1F HSW_ULT_DDR3L
4 5 PM_CLKRUN#

10K_0804_8P4R_5%

RC120 1 2 10K_0402_5% GPU_CLKREQ#


C43 A25 XTAL24_IN
C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT
PCIE_CLKREQ0# U2 CLKOUT_PCIE_P0 XTAL24_OUT
PCIECLKRQ0/GPIO18 K21
RSVD5
+1.05VS_PLPTCLKPLL DIFFCLK_BIASREF
B41 M21 Width: 12-15Mil
A41 CLKOUT_PCIE_N1 RSVD6 C26 DIFFCLK_BIASREF 2 1
CLKOUT_PCIE_P1 DIFFCLK_BIASREF Space:12Mil
PCIE_CLKREQ1# Y5 RC72 3.01K_0402_1%
PCIECLKRQ1/GPIO19 C35 MCP_TESTLOW1
Length: 500Mil
CLK_PCIE_LAN# C41 CLOCK TESTLOW_C35 C34 MCP_TESTLOW2
37 CLK_PCIE_LAN# CLK_PCIE_LAN B42 CLKOUT_PCIE_N2 TESTLOW_C34 AK8 MCP_TESTLOW3
PCIE CLK2 LAN 37 CLK_PCIE_LAN CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8
LAN_CLKREQ# AD1 AL8 MCP_TESTLOW4
37 LAN_CLKREQ# PCIECLKRQ2/GPIO20 TESTLOW_AL8
CLK_PCIE_WLAN# B38 AN15 CLK_PCI_EC_R RC73 2 1 22_0402_5% RPC5
40 CLK_PCIE_WLAN# C37 CLKOUT_PCIE_N3 CLKOUT_LPC_0 AP15 CLK_PCI_EC 44 8 1
PCIE CLK3 WLAN CLK_PCIE_WLAN MCP_TESTLOW1
40 CLK_PCIE_WLAN WLAN_CLKREQ# N1 CLKOUT_PCIE_P3 CLKOUT_LPC_1 MCP_TESTLOW2 7 2
40 WLAN_CLKREQ# PCIECLKRQ3/GPIO21 B35 6 3
MCP_TESTLOW3
CLK_PCIE_GPU# A39 CLKOUT_ITPXDP A35 MCP_TESTLOW4 5 4
19 CLK_PCIE_GPU# CLK_PCIE_GPU B39 CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
PCIE CLK4 GPU 19 CLK_PCIE_GPU CLKOUT_PCIE_P4
GPU_CLKREQ# U5 10K_0804_8P4R_5%
20 GPU_CLKREQ# PCIECLKRQ4/GPIO22
B37
C A37 CLKOUT_PCIE_N5 C
PCIE_CLKREQ5# T2 CLKOUT_PCIE_P5
+3VALW PCIECLKRQ5/GPIO23

6 OF 19
RC74 1 2 10K_0402_5% AC_PRESENT_R HASWELL-ULT-DDR3L_BGA1168 VCCRTC

RC75 1 @ 2 10K_0402_5% PCH_GPIO72

1
RC76 1 2 10K_0402_5% WAKE# RC77
330K_0402_5%

2
+3VALW_PCH
DSWODVREN

1
RC78 1 2 10K_0402_5% SUSWARN#_R
RC80
RC90 1 2 10K_0402_5% PCH_GPIO72 330K_0402_5%
UC1H HSW_ULT_DDR3L @

2
Reserve for DS3 SYSTEM POWER MANAGEMENT RC182 1 2 0_0402_5% EC_RSMRST#

RC79 1 @ 2 0_0402_5% SUSACK#_R AK2 AW7 DSWODVREN Reserve for DS3


44 SUSACK# SUSACK DSWVRMEN
SYS_RESET# AC3 AV5 PCH_DPWROK_R RC81 1 @ 2 0_0402_5% DSWODVREN - On Die DSW VR Enable
SYS_RESET DPWROK DPWROK_EC 44
RC139 1 @ 2 0_0402_5% SYS_PWROK_R AG2 AJ5 WAKE# RC82 1 @ 2 0_0402_5%
44 SYS_PWROK
10,44 PCH_PWROK
RC126 1 @ 2 0_0402_5% PCH_PWROK_R AY7 SYS_PWROK
PCH_PWROK
WAKE PCIE_WAKE# 9,37,40,44 * H Enable 
L Disable
RC83 1 @ 2 0_0402_5% APWROK AB5
RC84 1 @ 2 0_0402_5% PLT_RST#_R AG7 APWROK V5 PM_CLKRUN#
B 19,37,40,44 PLT_RST# PLTRST CLKRUN/GPIO32 B
AG4 SUS_STAT# 1 @ TC37
SUS_STAT/GPIO61 AE6 SUSCLK
SUSCLK/GPIO62 SUSCLK 40
AP5 PM_SLP_S5#
1 2 0_0402_5% PCH_RSMRST#_R AW6 SLP_S5/GPIO63 PM_SLP_S5# 44
RC85 @
44 EC_RSMRST# RSMRST
RC86 1 2 0_0402_5% SUSWARN#_R AV4
44 SUSWARN# SUSWARN/SUSPWRDNACK/GPIO30
RC87 1 @ 2 0_0402_5% PBTN_OUT#_R AL7 AJ6 PM_SLP_S4#_R RC140 1 @ 2 0_0402_5%
44 PBTN_OUT# AC_PRESENT_R AJ8 PWRBTN SLP_S4 AT4 PM_SLP_S3#_R 1 2 0_0402_5% PM_SLP_S4# 44
RC141 @
ACPRESENT/GPIO31 SLP_S3 PM_SLP_S3# 44
PCH_GPIO72 AN4 AL5
1 AF3 BATLOW/GPIO72 SLP_A AP4 PM_SLP_SUS#_R RC89 1 @ 2 0_0402_5%
TC38 1 AM5 SLP_S0 SLP_SUS AJ7 1 PM_SLP_SUS# 44
@ PAD
TC39 SLP_WLAN/GPIO29 SLP_LAN
@ PAD TC40 Reserve for DS3
CC104 @ @ PAD
1 2 PCH_PWROK
1000P_0402_50V7K
8 OF 19
CC103 @ HASWELL-ULT-DDR3L_BGA1168
1 2 PCH_DPWROK_R
1000P_0402_50V7K

@
CC101 1 2 1000P_0402_50V7K

RC91 1 2 10K_0402_5% SYS_PWROK RC88 1 @ 2 0_0402_5% AC_PRESENT_R


44 AC_PRESENT
RPC21
1 8
2 7 PCH_PWROK
1

3 6 PCH_RSMRST#_R D @
4 5 2 QC8
44,53 ACIN# G
A 2N7002KW_SOT323-3 A
10K_0804_8P4R_5%
S
3

100K_0402_5% 2 1 RC92 PLT_RST#_R

100K_0402_1% 2 @ 1 RC94 PCH_DPWROK_R Title


Security Classification LC Future Center Secret Data
1K_0402_5% 1 @ 2 RC95 SUSCLK
Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (Clock,PM)
10K_0402_5% 2 @ 1 RC105 GPU_CLKREQ#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 8 of 59
5 4 3 2 1
5 4 3 2 1

H_THRMTRIP#_R

.01U_0402_16V7-K
44 EC_LID_OUT# RC96 1 2 PCH_GPIO14
+3VALW 0_0402_5% +3VS

CC102
1
RC97 1 @ 2 10K_0402_5% PCH_GPIO12 DC2 1 2 @
RC98 1 2 10K_0402_5% DS3_WAKE# +1.05V_VCCST
RC99 1 2 10K_0402_5% PCH_GPIO25 SDM10U45LP-7_DFN1006-2-2

2
@ 2

2
RC100 RC101 RC102 RC121
UC1J HSW_ULT_DDR3L RC104 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
1K_0402_5% TOPAZ@ 15@ @ @
+3VALW_PCH

1
BOARD_ID0

1
BOARD_ID1
RC103 1 2 10K_0402_5% ODD_EN PCH_GPIO76 P1 D60 H_THRMTRIP#_R RC124 1 2 0_0402_5% BOARD_ID2
BMBUSY/GPIO76 THRMTRIP H_THRMTRIP# 20
PCH_GPIO8 AU2 V4 KBRST# @ KBRST# 44 BOARD_ID3
D GPIO8 RCIN/GPIO82 4 BOARD_ID3 D
PCH_GPIO12 AM7 T4 SERIRQ
SERIRQ 44

2
PCH_GPIO15 AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15 OPI_COMP RC106 2 149.9_0402_1%
BOARD_ID0 Y1 GPIO15 MISC PCH_OPI_RCOMP AF20 1 @ RC107 RC108 RC109 RC123
T3 GPIO16 RSVD7 AB21
+3VALW_PCH
42 ODD_DA#
ODD_DA#
GPIO17 RSVD8
TC41 OPI_RCOMP 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
ODD_EN AD5 Width 20Mil JET@ 14@
42 ODD_EN GPIO24
RPC6 RC110 1 @ 2 DS3_WAKE# AN5 Space 15Mil
8,37,40,44 PCIE_WAKE#

1
8 1 PCH_GPIO8 0_0402_5% PCH_GPIO28 AD7 GPIO27
7 2 PCH_GPIO26 AN3 GPIO28 Length 500Mil
6 3 PCH_GPIO28 GPIO26 R6 PCH_GPIO83
5 4 PCH_GPIO26 PCH_GPIO56 AG6 GSPI0_CS/GPIO83 L6 BOARD_ID1
PCH_GPIO57 AP1 GPIO56 GSPI0_CLK/GPIO84 N6 PCH_GPIO85
10K_0804_8P4R_5% PCH_GPIO58 AL4 GPIO57 GSPI0_MISO/GPIO85 L8 PCH_GPIO86
PCH_GPIO59 AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 PCH_BT_OFF#
GPIO59 GSPI1_CS/GPIO87 PCH_BT_OFF# 40
RPC7 PCH_GPIO44 AK4 GPIO L5 PCH_WLAN_OFF# BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 Description Stuff Resistor
GPIO44 GSPI1_CLK/GPIO88 PCH_WLAN_OFF# 40
8 1 PCH_GPIO57 PCH_GPIO47 AB6 N7 PCH_GPIO89
7 2 PCH_GPIO56 VGA_PWRGD U4 GPIO47 GSPI1_MISO/GPIO89 K2 PCH_GPIO90
19,44,58 VGA_PWRGD GPIO48 GSPI_MOSI/GPIO90
6 3 PCH_GPIO58 PCH_GPIO49 Y3 J1 PCH_GPIO91 0 0 0 0 14" + Jet-LE sku RC107,RC108,RC109,RC123
5 4 PCH_GPIO59 PCH_GPIO50 P3 GPIO49
GPIO50
UART0_RXD/GPIO91
UART0_TXD/GPIO92
K3 PCH_GPIO92 *
PCH_GPIO71 Y2 J2 PCH_GPIO93
10K_0804_8P4R_5% PCH_GPIO13 AT3 HSIOPC/GPIO71 SERIAL IO UART0_RTS/GPIO93 G1 PCH_GPIO94 0 1 0 0 15" + Jet-LE sku RC107,RC101,RC109,RC123
PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4 PCH_GPIO0
RPC8 @ PCH_GPIO25 AM4 GPIO14 UART1_RXD/GPIO0 G2 PCH_GPIO1
8 1 PCH_GPIO47 EC_SMI# RC111 1 2 PCH_GPIO45 AG5 GPIO25 UART1_TXD/GPIO1 J3 PCH_GPIO2 1 0 0 0 14" + Topaz-XT sku RC100,RC108,RC109,RC123
44 EC_SMI# GPIO45 UART1_RST/GPIO2
7 2 PCH_GPIO44 PCH_GPIO46 AG3 J4 PCH_GPIO3
6 3 PCH_GPIO13 0_0402_5% GPIO46 UART1_CTS/GPIO3 F2 PCH_GPIO4
5 4 PCH_GPIO14 PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 PCH_GPIO5 1 1 0 0 15" + Topaz-XT sku RC100,RC101,RC109,RC123
PCH_GPIO10 AM2 GPIO9 I2C0_SCL/GPIO5 G4 PCH_GPIO6
10K_0804_8P4R_5% PCH_GPIO33 P2 GPIO10 I2C1_SDA/GPIO6 F1 PCH_GPIO7 RC112 1 2 0_0402_5%
DEVSLP0/GPIO33 I2C1_SCL/GPIO7 EC_SCI# 44
PCH_GPIO70 C4 E3 PCH_GPIO64 @
RPC9 PCH_GPIO38 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 PCH_GPIO65
8 1 PCH_GPIO45 BOARD_ID2 N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 PCH_GPIO66
7 2 PCH_GPIO46 PCH_BEEP V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4 PCH_GPIO67
43 PCH_BEEP SPKR/GPIO81 SDIO_D1/GPIO67
6 3 PCH_GPIO10 C3 CMOS_ON#
SDIO_D2/GPIO68 CMOS_ON# 33
5 4 PCH_GPIO9 E2 PCH_GPIO69
SDIO_D3/GPIO69
10K_0804_8P4R_5% 10 OF 19
HASWELL-ULT-DDR3L_BGA1168
C C

+3VS

RC125 1 2 10K_0402_5% ODD_DA#

RPC10 19 PCIE_CRX_GTX_N[0..3]
8 1 PCH_GPIO33
7 2 PCH_GPIO49 19 PCIE_CRX_GTX_P[0..3]
6 3 PCH_GPIO50
5 4 PCH_GPIO76
19 PCIE_CTX_C_GRX_N[0..3]
10K_0804_8P4R_5% UC1K HSW_ULT_DDR3L +3VALW_PCH
19 PCIE_CTX_C_GRX_P[0..3]
RPC11 PCH_GPIO15 RC114 1 @ 2 1K_0402_5%
8 1 PCH_GPIO83 PCIE_CRX_GTX_N0 F10 AN8 USB20_N0
PERN5_L0 USB2N0 USB20_N0 45
7 2 PCH_GPIO38 PCIE_CRX_GTX_P0 E10 AM8 USB20_P0
6 3 PCH_GPIO70 PERP5_L0 USB2P0 USB20_P0 45 RIGHT USB (2.0) GPIO15, Internal PD
5 4 PCH_GPIO85 PCIE_CTX_C_GRX_N0 .1U_0402_10V6-K PX@ 1 2 CC16 PCIE_CTX_GRX_N0 C23 AR7 USB20_N1 1: INTEL ME TLS W/ Confidentiality
PETN5_L0 USB2N1 USB20_N1 41
PCIE_CTX_C_GRX_P0 .1U_0402_10V6-K PX@ 1 2 CC14 PCIE_CTX_GRX_P0 C22 AT7 USB20_P1
10K_0804_8P4R_5% PETP5_L0 USB2P1 USB20_P1 41 LEFT USB (3.0) *0: INTEL ME TLS W/O Confidentiality
PCIE_CRX_GTX_N1 F8 AR8 USB20_N2
PERN5_L1 USB2N2 USB20_N2 41
RPC12 PCIE_CRX_GTX_P1 E8 AP8 USB20_P2
8 1 PCH_GPIO89 PERP5_L1 USB2P2 USB20_P2 41 LEFT USB (2.0)
7 2 PCH_GPIO90 PCIE_CTX_C_GRX_N1 .1U_0402_10V6-K PX@ 1 2 CC15 PCIE_CTX_GRX_N1 B23 AR10 USB20_N3
PETN5_L1 USB2N3 USB20_N3 45
6 3 PCH_GPIO91 PCIE_CTX_C_GRX_P1 .1U_0402_10V6-K PX@ 1 2 CC17 PCIE_CTX_GRX_P1 A23 AT10 USB20_P3 +3VS
5 4 PCH_GPIO92 PETP5_L1 USB2P3 USB20_P3 45 Card reader
GPU PCIE5 PCIE_CRX_GTX_N2 H10 AM15 USB20_N4 PCH_GPIO66 RC113 1 @ 2 1K_0402_5%
PERN5_L2 USB2N4 USB20_N4 33
10K_0804_8P4R_5% PCIE_CRX_GTX_P2 G10 AL15 USB20_P4
PERP5_L2 USB2P4 USB20_P4 33 Touch panel GPIO66, Internal 20K PD
RPC13 PCIE_CTX_C_GRX_N2 .1U_0402_10V6-K PX@ 1 2 CC18 PCIE_CTX_GRX_N2 B21 AM13 USB20_N5 1: Enable Top Swap Mode
PETN5_L2 USB2N5 USB20_N5 33
8 1 PCH_GPIO93 PCIE_CTX_C_GRX_P2 .1U_0402_10V6-K PX@ 1 2 CC19 PCIE_CTX_GRX_P2 C21 AN13 USB20_P5
7 2 PCH_GPIO1 PETP5_L2 USB2P5 USB20_P5 33 Camera *0: Disable Top Swap Mode(default)
6 3 PCH_GPIO94 PCIE_CRX_GTX_N3 E6 AP11 USB20_N6
PERN5_L3 USB2N6 USB20_N6 40
5 4 PCH_GPIO0 PCIE_CRX_GTX_P3 F6 AN11 USB20_P6
PERP5_L3 USB2P6 USB20_P6 40 BT
10K_0804_8P4R_5% PCIE_CTX_C_GRX_N3 .1U_0402_10V6-K PX@ 1 2 CC20 PCIE_CTX_GRX_N3 B22 AR13
B
PCIE_CTX_C_GRX_P3 .1U_0402_10V6-K PX@ 1 2 CC21 PCIE_CTX_GRX_P3 A21 PETN5_L3 USB2N7 AP13 +3VS B
RPC14 PETP5_L3 USB2P7
8 1 PCH_GPIO3 37 PCIE_PRX_DTX_N3 PCIE_PRX_DTX_N3 G11
7 2 PCH_GPIO2 PCIE_PRX_DTX_P3 F11 PERN3 G20 USB30_RX_N1 PCH_GPIO86 RC115 2 @ 1 1K_0402_5%
37 PCIE_PRX_DTX_P3 PERP3 USB3RN1 USB30_RX_N1 41
6 3 PCH_GPIO4 LAN PCIE3 H20 USB30_RX_P1
USB3RP1 USB30_RX_P1 41
5 4 PCH_GPIO5 CC22 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_N3 C29 RC116 2 @ 1 1K_0402_5%
37 PCIE_PTX_C_DRX_N3
CC23 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_P3 B30 PETN3 PCIE USB C33 USB30_TX_N1
LEFT USB (3.0)
37 PCIE_PTX_C_DRX_P3 PETP3 USB3TN1 USB30_TX_N1 41
10K_0804_8P4R_5% B34 USB30_TX_P1
USB3TP1 USB30_TX_P1 41
PCIE_PRX_DTX_N4 F13 GPIO86, Internal PD
40 PCIE_PRX_DTX_N4 PERN4
RPC15 PCIE_PRX_DTX_P4 G13 E18 1: LPC
40 PCIE_PRX_DTX_P4 PERP4 USB3RN2
8 1 PCH_GPIO64 WLAN PCIE4 F18 *0: SPI
7 2 PCH_GPIO6 CC24 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_N4 B29 USB3RP2
40 PCIE_PTX_C_DRX_N4 PETN4
6 3 PCH_GPIO65 CC25 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_P4 A29 B33
40 PCIE_PTX_C_DRX_P4 PETP4 USB3TN2
5 4 PCH_GPIO7 A33
G17 USB3TP2
10K_0804_8P4R_5% F17 PERN1/USB3RN3
PERP1/USB3RP3 +3VS
RPC16 C30
8 1 PCH_GPIO67 C31 PETN1/USB3TN3 AJ10 USBRBIAS RC118 2 1
7 2 PETP1/USB3TP3 USBRBIAS AJ11
PCH_GPIO69
USBRBIAS
22.6_0402_1% USBRBIAS PCH_BEEP RC117 2 @ 1 1K_0402_5%
6 3 PCH_GPIO71 F15 AN10 Width 20Mil
5 4 G15 PERN2/USB3RN4 RSVD11 AM10
PERP2/USB3RP4 RSVD12 Space 15Mil
Length 500Mil GPIO81, No Reboot, Internal PD
10K_0804_8P4R_5% B31 1: Enabled No Reboot Mode
A31 PETN2/USB3TN4
PETP2/USB3TP4 *0: Disable No Reboot Mode
AL3 USB_OC0#
OC0/GPIO40 AT1 USB_OC1#
OC1/GPIO41 USB_OC1# 41
AH2 USB_OC2#
+1.05VS_PUSB3PLL OC2/GPIO42 USB_OC2# 45
E15 AV3 USB_OC3#
E13 RSVD9 OC3/GPIO43
+3VS RC119 2 1 3.01K_0402_1% PCIE_RCOMP A27 RSVD10 +3VALW_PCH
B27 PCIE_RCOMP
RPC18 PCIE_IREF
1 8 CMOS_ON# PCIE_RCOMP&PCIE_IREF
2 7 PCH_WLAN_OFF# Width 12~15Mil RPC17
3 6 PCH_BT_OFF# Space >12Mil 11 OF 19 USB_OC0# 8 1
4 5 KBRST# HASWELL-ULT-DDR3L_BGA1168 USB_OC1# 7 2
A
Length 500Mil USB_OC3# 6 3 A
10K_0804_8P4R_5% USB_OC2# 5 4

RC122 1 2 10K_0402_5% SERIRQ 10K_0804_8P4R_5%

RC181 1 UMA@ 2 10K_0402_5% VGA_PWRGD

Security Classification
Classification LC Future Center Secret Data Title
Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (GPIO,USB,PCIE)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 9 of 59
5 4 3 2 1
5 4 3 2 1

CPU_CORE +1.35V_CPU
UC1L HSW_ULT_DDR3L

+1.35V Need short +1.35V_CPU @ TC45 1 L59 C36


RSVD13 VCC8

2.2U_0603_10V6-K

2.2U_0603_10V6-K

2.2U_0603_10V6-K

2.2U_0603_10V6-K
@ TC46 1 J58 C40
JC1 @ RSVD14 VCC9 C44
VCC10 1 1 1 1

CC26

CC27

CC28

CC29
1 2 AH26 C48
1 2 AJ31 VDDQ1 VCC11 C52
AJ33 VDDQ2 VCC12 C56
JUMP_43X79 AJ37 VDDQ3 VCC13 E23 2 2 2 2
AN33 VDDQ4 VCC14 E25
AP43 VDDQ5 VCC15 E27 CD@
AR48 VDDQ6 VCC16 E29
D
AY35 VDDQ7 VCC17 E31 D
AY40 VDDQ8 VCC18 E33
CPU_CORE
VDDQ9 VCC19
For cost down, change to X5R.
AY44 E35
CPU_CORE AY50 VDDQ10 VCC20 E37
VDDQ11 VCC21

2
VCC_SENSE E39
F59 VCC22 E41
Length Match: <25Mil RC127
VCC1 VCC23

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
Space: More Than 25Mil 100_0402_1% @ TC47 1 N58 E43
RSVD15 VCC24

330U_2.5V_M
@ TC48 1 AC58 E45 1 1 1 1 1 1 1
GND Reference RSVD16 VCC25

CC34

CC30

CC35

CC31

CC32

CC33
E47

1
VCC26

CC41
+VCCIO_OUT RC128 1 @ 2 0_0402_5% E63 E49 +
59 CPU_VCC_SENSE VCC_SENSE VCC27
AB23 E51
A59 RSVD17 VCC28 E53 2 2 2 2 2 2
E20 VCCIO_OUT VCC29 E55 2
+VCCIOA_OUT VCCIOA_OUT VCC30
1 @ TC50 1 AD23 E57 @
@ TC51 1 AA23 RSVD18 VCC31 F24 CD@
CC36 @ TC52 1 AE59 RSVD19 VCC32 F28
4.7U_0603_10V6-K RSVD20 VCC33 F32
@ 2 CPU_SVID_ALERT#_R L62 VCC34 F36
N63 VIDALERT HSW ULT POWER VCC35 F40
1.35V_CPU(1.4A)
CPU_SVID_CLK_R
VIDSCLK VCC36
CPU_SVID_DAT_R L63
VIDSOUT VCC37
F44 HW 4PCS 2.2UF CAP Mounted
VCCST_PWRGD B59 F48 HW 6PCS 10UF CAP Mounted
CPU_VR_ON F60 VCCST_PWRGD VCC38 F52
59 CPU_VR_ON
CPU_VR_READY C59 VR_EN VCC39 F56
PWR 2PCS 470U Near VR Output
+1.05VS VR_READY VCC40 G23
D63 VCC41 G25
RC129 2 @ 1 150_0402_1% PWR_DEBUG H59 VSS344 VCC42 G27
P62 PWR_DEBUG VCC43 G29
@ TC53 1 P60 VSS345 VCC44 G31 +1.35V_CPU
@ TC54 1 P61 RSVD_TP1 VCC45 G33
@ TC55 1 N59 RSVD_TP2 VCC46 G35
RSVD_TP3 VCC47

CC37

CC38
RC130 2 1 N61 G37
10K_0402_5% @ TC56 1 T59 RSVD_TP4 VCC48 G39
RSVD21 VCC49

33P_0402_50V8J

33P_0402_50V8J
@ TC57 1 AD60 G41
@ TC58 1 AD59 RSVD22 VCC50 G43
RSVD23 VCC51 1 1
@ TC59 1 AA59 G45
@ TC60 1 AE60 RSVD24 VCC52 G47
@ TC61 1 AC59 RSVD25 VCC53 G49
@ TC62 1 AG58 RSVD26 VCC54 G51 2 2
C C
RSVD27 VCC55

@
@ TC63 1 U59 G53
+1.05VS +1.05V_VCCST @ TC64 1 V59 RSVD28 VCC56 G55
RSVD29 VCC57 G57
VCCST(0.1A) VCC58
LC1 1 2 AC22 H23
UPB100505T-121Y-N AE22 VCCST1 VCC59 J23
CPU_CORE AE23 VCCST2 VCC60 K23
1 1 VCCST3 VCC61 K57
CC39 CC40 AB57 VCC62 L22
22U_0805_6.3V6M 1U_0402_10V6K AD57 VCC2 VCC63 M23
For RF
2 2 AG57 VCC3 VCC64 M57
CC2
33P_0402_50V8J
C24 VCC4 VCC65 P57
1 VCC5 VCC66
C28 U57
C32 VCC6 VCC67 W57
VCC7 VCC68
2 12 OF 19
@

HASWELL-ULT-DDR3L_BGA1168
SVID
1, Stripline Line, No More Than 6000Mil
2, Alert# Route Between CLK and Data
3, CLK Length<Data Length<CLK Length + 2000Mil
4, Space at least 18Mil For RF
+1.05VS
2

CC42
RC131 RC132 .1U_0402_10V6-K
75_0402_1% 130_0402_1% @
2
1

59 CPU_SVID_ALERT# RC133 2 1 43_0402_5% CPU_SVID_ALERT#_R

@
RC134 1 2 0_0402_5% CPU_SVID_CLK_R
59 CPU_SVID_CLK
@
B B
RC135 1 2 0_0402_5% CPU_SVID_DAT_R
59 CPU_SVID_DAT
CPU_VR_ON

+1.05V_VCCST

2
+1.05V_VCCST

2
RC146
RC145 10K_0402_5%
2

+3VALW 10K_0402_5%
+3VALW RC137 @

1
1K_0402_5%

1
0_0402_5%
2

2
2 1 CPU_VR_READY
1

RC136 VCCST_PWRGD RC144 RC147 @


10K_0402_5% 10K_0402_5%
3

3
D D 1
1

1
5 QC6B 2 5 CC141
G G 2N7002KDWH_SOT363-6 100P_0402_50V8J
2N7002KDWH_SOT363-6 CC140 QC7B @
6

6
RC138 D S RC148 D S 2
1000P_0402_50V7K
4

4
2 1 2 QC6A 1 2 1 2
8,44 PCH_PWROK @ 44,59 VR_CPU_PWROK 2N7002KDWH_SOT363-6
G G
0_0402_5% 2N7002KDWH_SOT363-6 0_0402_5% QC7A
1 1
CC46 S CC49 S
1

1
@ 0.01U_0402_16V7K @ 0.01U_0402_16V7K
@ @
2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (Power)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 10 of 59
5 4 3 2 1
5 4 3 2 1

+3VALW_PCH

HSW_ULT_DDR3L 2
+1.05VS_VCCHSIO UC1M CC50
VCCHSIO 1.838A 1U_0402_10V6K
K9
L10 VCCHSIO[1] 1
+1.05VS VCCHSIO[2] VCCRTC

1U_0402_10V6K

1U_0402_10V6K
VCC1_05[1:9] 1.741A M9
N8 VCCHSIO[3] HSIO RTC AH11
1 1 VCC1_05[1] VCCSUS3_3[5] VCCRTC 1mA

CC53

CC51

1U_0402_10V6K
P9 AG10
VCC1_05[2] VCCRTC

CC55

CC56

CC57
1 B18 AE7 +DCPRTC CC52 2 1
+1.05VS_PUSB3PLL VCCUSB3PLL DCPRTC

CC54

0.1U_0402_10V7K

0.1U_0402_10V7K
+1.05VS_PSATA3PLL B11
D 2 2 VCCSATA3PLL D

1U_0402_10V6K
VCCSPI 0.1U_0402_10V7K
2
VCCSPI 18mA 2 2 2

0.1U_0402_10V7K
+1.05VS_POPIPLL Y20 SPI Y8
AA21 RSVD30 OPI
VCCSPI
VCCAPLL[1] 2

CC58 @
W21 +1.05VS
VCCAPLL[2] AG14 1 1 1
VCCASW[1] AG13
VCCASW[2] 1
VCCASW[1:5] 658mA +1.05VS
@ 1U_0402_10V6K 1 2 CC59 +1.05VS_DCPSUS3 J13 USB3
VCCHDA DCPSUS3 J11 CD@
VCC1_05[3]

CC63

CC64

CC65
VCCHDA 11mA H11
AH14 HDA VCC1_05[4] H15
VCCHDA VCC1_05[5]

1U_0402_10V6K

1U_0402_10V6K

10U_0603_6.3V6M
AE8
VCC1_05[6]
1U_0402_10V6K

AF22 1U_0402_10V6K 2 2 2
@ 1U_0402_10V6K 1 2 CC60 +1.05VS_DCPSUS2 AH13 VRM VCC1_05[7] AG19 +PCH_DCPSUSBYP CC61 2 1 +1.05VS
1 DCPSUS2 DCPSUSBYP[1]
CC62

CORE AG20
+3VALW_PCH DCPSUSBYP[2] AE9
VCCASW[3] 1 1 1

CC68

CC69
VCCSUS3_3[1:5] 65mA AF9
2 AC9 VCCASW[4] AG8
VCCSUS3_3[1] VCCASW[5]
22U_0805_6.3V6M

1U_0402_10V6K

22U_0805_6.3V6M
VCCDSW 114mA AA9 GPIO/LPC AD10 +1.05VS_DCPSUS1 CC66 2 1 @
AH10 VCCSUS3_3[2] DCPSUS1[1] AD8
1 VCCDSW3_3 VCCDSW3_3 DCPSUS1[2] 2 1
CC67

1U_0402_10V6K

V8 +1.5VS 1U_0402_10V6K
+3VS VCC3_3[1]
1 VCC3_3[1:4] 41mA W9 VCCTS1_5 3mA
VCC3_3[2]
CC70 @

22U_0805_6.3V6M J15 +3VS


2 THERMAL SENSOR VCCTS1_5 K14 1 2
1 VCC3_3[3]
CC71

@
K16
2 VCC3_3[4]

0.1U_0402_10V7K
+1.05VS_PLPTVCC1P05
+3VS 2
2

CC72
+1.05VS_PLPTCLKPLL J18 VCCSDIO 17mA
+1.05VS K19 VCCCLK[1] SERIAL IO U8
VCCCLK[2] VCCSDIO[1]

1U_0402_10V6K
A20 T9
J17 VCCACLKPLL VCCSDIO[2] 1
VCCCLK[3] 2

CC74
R21
VCCCLK[4]
1U_0402_10V6K

1U_0402_10V6K

T21 LPT LP POWER 1U_0402_10V6K


TC66 @ 1 K18 VCCCLK[5] SUS OSCILLATOR AB8 +1.05VS_DCPSUS4 CC73 2 1 @
1 1 RSVD31 DCPSUS4 1
CC75

CC76

TC67 @ 1 M20
V21 RSVD32 +1.05VS
AE20 RSVD33 AC20
C C
2 2 AE21 VCCSUS3_3[3] RSVD34 AG16
+3VALW_PCH VCCSUS3_3[4] USB2 VCC1_05[8] AG17
VCC1_05[9]

1U_0402_10V6K
CD@ 2

CC77
+3VL 13 OF 19
HASWELL-ULT-DDR3L_BGA1168 1
RC149 2 @ 1 VCCDSW3_3
+3VALW 0_0402_5%

RC150 2 1
0_0402_5%

+3VALW_PCH +1.05VS Need short +1.05VS_VCCHSIO +1.05VS_PUSB3PLL +1.05VS +1.05VS_PLPTVCC1P05

JC2 @ +1.05VS_PUSB3PLL 41mA +1.05VS_PLPTVCC1P05 185mA


RC151 2 @ 1 VCCHDA 1 2 LC2 1 2 LC3 1 2
+3VS 0_0402_5% 1 2 2.2UH_CIG10W2R2MNC_20% 2.2UH_CIG10W2R2MNC_20%
JUMP_43X79 1 1 1 1 1 1 1 1
0_0402_5% 2 @ 1 RC152 CC78 CC79 CC80
22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_10V6K CC81 CC100 CC82 CC83 CC84
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_10V6K
2 2 2 2 2 2 2 2

+3VS

RC153 2 @ 1 VCCSPI
+3V_SPI 0_0402_5% +1.05VS_PSATA3PLL +1.05VS_PLPTCLKPLL 31mA +1.05VS_PLPTCLKPLL
+1.05VS_PSATA3PLL 42mA
0_0402_5% 2 @ 1 RC154 LC4 1 2 LC5 1 2
B B
2.2UH_CIG10W2R2MNC_20% 2.2UH_CIG10W2R2MNC_20%

1 1 1 1 1 1 1 1
CC85 CC86 CC87
22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_10V6K CC88 CC95 CC98 CC99 CC89
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_10V6K
2 2 2 2 2 2 2 2

VCCDSW3_3 CC90 1 2 0.47U_0402_25V6K +PCH_DCPSUSBYP

For Intel recommend, place one 0.47uF +1.05VS_POPIPLL


capacitor to address temporary inrush @ +1.05VS_POPIPLL 57mA
LC6 1 2
current.(DOC.489999) 0_0603_5%

1 1 1
1
CC91 CC92 CC93 CC94
33P_0402_50V8J 47U_0805_4V6-M 47U_0805_4V6-M 1U_0402_10V6K
@ 2@ 2@ 2
2

For RF

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (Power2)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 11 of 59
5 4 3 2 1
5 4 3 2 1

UC1N HSW_ULT_DDR3L UC1O HSW_ULT_DDR3L

A11 AJ35 AP22 AV59


A14 VSS1 VSS65 AJ39 AP23 VSS129 VSS193 AV8
A18 VSS2 VSS66 AJ41 AP26 VSS130 VSS194 AW16
D D
A24 VSS3 VSS67 AJ43 AP29 VSS131 VSS195 AW24
A28 VSS4 VSS68 AJ45 AP3 VSS132 VSS196 AW33
A32 VSS5 VSS69 AJ47 AP31 VSS133 VSS197 AW35
A36 VSS6 VSS70 AJ50 AP38 VSS134 VSS198 AW37
A40 VSS7 VSS71 AJ52 AP39 VSS135 VSS199 AW4 UC1P HSW_ULT_DDR3L
A44 VSS8 VSS72 AJ54 AP48 VSS136 VSS200 AW40 H17
A48 VSS9 VSS73 AJ56 AP52 VSS137 VSS201 AW42 D33 VSS300 H57
A52 VSS10 VSS74 AJ58 AP54 VSS138 VSS202 AW44 D34 VSS257 VSS301 J10
A56 VSS11 VSS75 AJ60 AP57 VSS139 VSS203 AW47 D35 VSS258 VSS302 J22
AA1 VSS12 VSS76 AJ63 AR11 VSS140 VSS204 AW50 D37 VSS259 VSS303 J59
AA58 VSS13 VSS77 AK23 AR15 VSS141 VSS205 AW51 D38 VSS260 VSS304 J63
AB10 VSS14 VSS78 AK3 AR17 VSS142 VSS206 AW59 D39 VSS261 VSS305 K1
AB20 VSS15 VSS79 AK52 AR23 VSS143 VSS207 AW60 D41 VSS262 VSS306 K12
AB22 VSS16 VSS80 AL10 AR31 VSS144 VSS208 AY11 D42 VSS263 VSS307 L13
AB7 VSS17 VSS81 AL13 AR33 VSS145 VSS209 AY16 D43 VSS264 VSS308 L15
AC61 VSS18 VSS82 AL17 AR39 VSS146 VSS210 AY18 D45 VSS265 VSS309 L17
AD21 VSS19 VSS83 AL20 AR43 VSS147 VSS211 AY22 D46 VSS266 VSS310 L18
AD3 VSS20 VSS84 AL22 AR49 VSS148 VSS212 AY24 D47 VSS267 VSS311 L20
AD63 VSS21 VSS85 AL23 AR5 VSS149 VSS213 AY26 D49 VSS268 VSS312 L58
AE10 VSS22 VSS86 AL26 AR52 VSS150 VSS214 AY30 D5 VSS269 VSS313 L61
AE5 VSS23 VSS87 AL29 AT13 VSS151 VSS215 AY33 D50 VSS270 VSS314 L7
AE58 VSS24 VSS88 AL31 AT35 VSS152 VSS216 AY4 D51 VSS271 VSS315 M22
AF11 VSS25 VSS89 AL33 AT37 VSS153 VSS217 AY51 D53 VSS272 VSS316 N10
AF12 VSS26 VSS90 AL36 AT40 VSS154 VSS218 AY53 D54 VSS273 VSS317 N3
C
AF14 VSS27 VSS91 AL39 AT42 VSS155 VSS219 AY57 D55 VSS274 VSS318 P59 C
AF15 VSS28 VSS92 AL40 AT43 VSS156 VSS220 AY59 D57 VSS275 VSS319 P63
AF17 VSS29 VSS93 AL45 AT46 VSS157 VSS221 AY6 D59 VSS276 VSS320 R10
AF18 VSS30 VSS94 AL46 AT49 VSS158 VSS222 B20 D62 VSS277 VSS321 R22
AG1 VSS31 VSS95 AL51 AT61 VSS159 VSS223 B24 D8 VSS278 VSS322 R8
AG11 VSS32 VSS96 AL52 AT62 VSS160 VSS224 B26 E11 VSS279 VSS323 T1
AG21 VSS33 VSS97 AL54 AT63 VSS161 VSS225 B28 E17 VSS280 VSS324 T58
AG23 VSS34 VSS98 AL57 AU1 VSS162 VSS226 B32 F20 VSS281 VSS325 U20
AG60 VSS35 VSS99 AL60 AU16 VSS163 VSS227 B36 F26 VSS282 VSS326 U22
AG61 VSS36 VSS100 AL61 AU18 VSS164 VSS228 B4 F30 VSS283 VSS327 U61
AG62 VSS37 VSS101 AM1 AU20 VSS165 VSS229 B40 F34 VSS284 VSS328 U9
AG63 VSS38 VSS102 AM17 AU22 VSS166 VSS230 B44 F38 VSS285 VSS329 V10
AH17 VSS39 VSS103 AM23 AU24 VSS167 VSS231 B48 F42 VSS286 VSS330 V3
AH19 VSS40 VSS104 AM31 AU26 VSS168 VSS232 B52 F46 VSS287 VSS331 V7
AH20 VSS41 VSS105 AM52 AU28 VSS169 VSS233 B56 F50 VSS288 VSS332 W20
AH22 VSS42 VSS106 AN17 AU30 VSS170 VSS234 B60 F54 VSS289 VSS333 W22
AH24 VSS43 VSS107 AN23 AU33 VSS171 VSS235 C11 F58 VSS290 VSS334 Y10
AH28 VSS44 VSS108 AN31 AU51 VSS172 VSS236 C14 F61 VSS291 VSS335 Y59
AH30 VSS45 VSS109 AN32 AU53 VSS173 VSS237 C18 G18 VSS292 VSS336 Y63
AH32 VSS46 VSS110 AN35 AU55 VSS174 VSS238 C20 G22 VSS293 VSS337
AH34 VSS47 VSS111 AN36 AU57 VSS175 VSS239 C25 G3 VSS294
AH36 VSS48 VSS112 AN39 AU59 VSS176 VSS240 C27 G5 VSS295 V58
AH38 VSS49 VSS113 AN40 AV14 VSS177 VSS241 C38 G6 VSS296 VSS338 AH46
AH40 VSS50 VSS114 AN42 AV16 VSS178 VSS242 C39 G8 VSS297 VSS339 V23
AH42 VSS51 VSS115 AN43 AV20 VSS179 VSS243 C57 H13 VSS298 VSS340 E62 RC158 1 @ 2 0_0402_5%
B B
AH44 VSS52 VSS116 AN45 AV24 VSS180 VSS244 D12 VSS299 VSS_SENSE AH16 CPU_VSS_SENSE 59
VSS53 VSS117 VSS181 VSS245 VSS341

2
AH49 AN46 AV28 D14 16 OF 19
AH51 VSS54 VSS118 AN48 AV33 VSS182 VSS246 D18 HASWELL-ULT-DDR3L_BGA1168 RC159
AH53 VSS55 VSS119 AN49 AV34 VSS183 VSS247 D2
VSS56 VSS120 VSS184 VSS248
100_0402_1% VSS_SENSE
AH55 AN51 AV36 D21 Length Match: No More Than 25Mil
AH57 VSS57 VSS121 AN52 AV39 VSS185 VSS249 D23 Space: More Than 25Mil

1
AJ13 VSS58 VSS122 AN60 AV41 VSS186 VSS250 D25
AJ14 VSS59 VSS123 AN63 AV43 VSS187 VSS251 D26 GND Reference
AJ23 VSS60 VSS124 AN7 AV46 VSS188 VSS252 D27
AJ25 VSS61 VSS125 AP10 AV49 VSS189 VSS253 D29
AJ27 VSS62 VSS126 AP17 AV51 VSS190 VSS254 D30
AJ29 VSS63 VSS127 AP20 AV55 VSS191 VSS255 D31
VSS64 VSS128 VSS192 15 OF 19 VSS256
HASWELL-ULT-DDR3L_BGA1168

14 OF 19
HASWELL-ULT-DDR3L_BGA1168

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (VSS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 12 of 59
5 4 3 2 1
5 4 3 2 1

UC1Q HSW_ULT_DDR3L

DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3


DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 TP_DC_TEST_A4 1 @ TC71
TC70 @ 1 TP_DC_TEST_AY60 AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4
D
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60 TP_DC_TEST_A60 1 @ TC72 D
DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61
TC73 @ 1 TP_DC_TEST_B2 B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62 TP_DC_TEST_A62 1 @ TC74
DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1 TP_DC_TEST_AV1 1 @ TC75
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 TP_DC_TEST_AW1 1 @ TC76
DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 TP_DC_TEST_AW63 1 @ TC77
17 OF 19 DAISY_CHAIN_NCTF_AW63
HASWELL-ULT-DDR3L_BGA1168

UC1R HSW_ULT_DDR3L

N23
RSVD42 R23
TC78 @ 1 RSVD43 T23
AT2 RSVD44
TC82 @ 1 AU44 RSVD35 U10 1 @ TC83
TC84 @ 1 RSVD45
AV44 RSVD36
D15 RSVD37
RSVD38 AL1 1 @ TC86
RSVD46 AM11
TC88 @ 1 RSVD47 AP7
F22 RSVD48
RSVD39 AU10
H22 RSVD49
RSVD40 AU15 1 @ TC93
J21 RSVD50
C RSVD41 AW14 C
RSVD51 AY14
RSVD52

18 OF 19
HASWELL-ULT-DDR3L_BGA1168

UC1S HSW_ULT_DDR3L

TC96 @ 1 CFG0 AC60 AV63 1 @ TC97 CFG3 RC160 2 @ 1 1K_0402_1%


TC98 @ 1 CFG1 AC62 CFG0 RSVD_TP5 AU63 1 @ TC101
TC99 @ 1 CFG2 AC63 CFG1 RSVD_TP6
TC100 @ 1 CFG3 AA63 CFG2
1 CFG4 AA60 CFG3 C63 1 @
TC102 @
CFG4 RSVD_TP7
TC103 CFG3
TC104 @ 1 CFG5 Y62 C62 1 @ TC105 *1: Disable
TC106 @ 1 CFG6 Y61 CFG5 RSVD_TP8 B43 1 @ TC107
CFG6 RSVD58 0: Enable, Set DFX Enabled BIT
TC108 @ 1 CFG7 Y60
TC109 @ 1 CFG8 V62 CFG7 A51 1 @ TC110
In Debug Interface MSR
TC111 @ 1 CFG9 V61 CFG8 RSVD_TP9 B51 1 @ TC112
TC113 @ 1 CFG10 V60 CFG9 RSVD_TP10
TC114 @ 1 CFG11 U60 CFG10 L60 1 @ TC115
TC116 @ 1 CFG12 T63 CFG11 RSVD_TP11
TC117 @ 1 CFG13 T62 CFG12 RESERVED N60 1 @ TC118 CFG4 RC161 2 1 1K_0402_1%
B
TC119 @ 1 CFG14 T61 CFG13 RSVD59 B

TC120 @ 1 CFG15 T60 CFG14 W23


CFG15 RSVD60 Y22
1 CFG16 AA62 RSVD61 AY15 PROC_OPI_COMP 2 1
TC123 @
CFG16 PROC_OPI_RCOMP
RC162 PROC_OPI_RCOMP
TC124 @ 1 CFG18 U63 49.9_0402_1% Width 20Mil CFG4
1 AA61 CFG18 AV62 1 @
TC125 @ CFG17
CFG17 RSVD62
TC126 Space 15Mil *L: eDP enable
TC127 @ 1 CFG19 U62 D58 H: eDP disable
CFG19 RSVD63 Length 500Mil
RC163 2 1 49.9_0402_1% CFG_RCOMP V63 P22
CFG_RCOMP VSS342 N21
@ 1 A5 VSS343
CFG_RCOMP&TD_IREF TC129
RSVD53 P20
RSVD64
Width 20Mil E1
RSVD54 RSVD65
R20
Space 15Mil D1 CFG0 RC164 2 @ 1 1K_0402_1%
J20 RSVD55
Length 500Mil TC135 @ 1 H18 RSVD56 CFG1 RC165 2 @ 1 1K_0402_1%
2 1 TD_IREF B12 RSVD57
RC166 8.2K_0402_1% TD_IREF CFG8 RC167 2 @ 1 1K_0402_1%
19 OF 19
HASWELL-ULT-DDR3L_BGA1168 CFG9 RC168 2 @ 1 1K_0402_1%

CFG10 RC169 2 @ 1 1K_0402_1%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 MCP (OTHER)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 13 of 59
5 4 3 2 1
5 4 3 2 1

DDR_SA_VREFDQ 6
DDR3 SO-DIMM A
DDRA_DQ[0..63] 6
+1.35V
+1.35V +1.35V
DDRA_DQS[0..7] 6

1
DDRA_DQS#[0..7] 6
RD5
1.82K_0402_1% 3A@1.5V DDRA_MA[0..15] 6
RD6 For RF
JDDR1
2

1 2 +VREF_DQ_DIMMA 1 2
D 2_0402_5% 3 VREF_DQ VSS_2 4 DDRA_DQ4 D
VSS_1 DQ4
1
0.022U_0402_16V7-K

1.82K_0402_1%

2.2U_0603_6.3V6K

.1U_0402_10V6-K

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J
DDRA_DQ0 5 6 DDRA_DQ5
DDRA_DQ1 7 DQ0 DQ5 8
1 1 DQ1 VSS_4 1 1 1
RD7

CD5

CD6

CD7
1 CD4 CD2 9 10 DDRA_DQS#0 @ @ @
VSS_3 DQS0#
CD3

11 12 DDRA_DQS0
13 DM0 DQS0 14
2

CD@2 2 DDRA_DQ2 15 VSS_5 VSS_6 16 DDRA_DQ6 2 2 2


2 DDRA_DQ3 17 DQ2 DQ6 18 DDRA_DQ7
19 DQ3 DQ7 20
DDRA_DQ8 21 VSS_7 VSS_8 22 DDRA_DQ12
DQ8 DQ12
1

DDRA_DQ9 23 24 DDRA_DQ13
RD8 25 DQ9 DQ13 26
24.9_0402_1% DDRA_DQS#1 27 VSS_9 VSS_10 28
DDRA_DQS1 29 DQS1# DM1 30 CPU_DRAMRST#
31 DQS1 RESET# 32 CPU_DRAMRST# 5,15
2

DDRA_DQ10 33 VSS_11 VSS_12 34 DDRA_DQ14


DDRA_DQ11 35 DQ10 DQ14 36 DDRA_DQ15
37 DQ11 DQ15 38
DDRA_DQ16 39 VSS_13 VSS_14 40 DDRA_DQ20 Layout Note: OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y0J)
DDRA_DQ17 41 DQ16 DQ20 42 DDRA_DQ21
43 DQ17 DQ21 44 Place near DIMM (10uF_0603_6.3V)*8
DDRA_DQS#2 45 VSS_15 VSS_16 46
DDRA_DQS2 47 DQS2# DM2 48 (1U_0402_6.3V)*4
49 DQS2 VSS_18 50 DDRA_DQ22
DDRA_DQ18 51 VSS_17 DQ22 52 DDRA_DQ23 (.1U_0402_10V6-K)*4
DDRA_DQ19 53 DQ18 DQ23 54
55 DQ19 VSS_20 56 DDRA_DQ28
DDRA_DQ24 57 VSS_19 DQ28 58 DDRA_DQ29 +1.35V
DDRA_DQ25 59 DQ24 DQ29 60
61 DQ25 VSS_22 62 DDRA_DQS#3
VSS_21 DQS3#

CD8

CD9

CD10

CD11

CD12

CD13

CD14

CD15

CD16

CD17

CD18

CD19

CD56

CD57

CD58

CD59
63 64 DDRA_DQS3
65 DM3 DQS3 66
VSS_23 VSS_24

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
C DDRA_DQ26 67 68 DDRA_DQ30 C
DQ26 DQ30 1
DDRA_DQ27 69 70 DDRA_DQ31 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
71 DQ27 DQ31 72 + CD20
VSS_25 VSS_26 220U_6.3V_M
@
DDRA_CKE0 73 74 DDRA_CKE1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
6 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 6
75 76
77 VDD_1 VDD_2 78 DDRA_MA15
DDRA_BS2# 79 NC_1 A15 80 DDRA_MA14
6 DDRA_BS2# BA2 A14
81 82 CD@ CD@
DDRA_MA12 83 VDD_3 VDD_4 84 DDRA_MA11 CD@ CD@ CD@ CD@
DDRA_MA9 85 A12/BC# A11 86 DDRA_MA7
87 A9 A7 88
DDRA_MA8 89 VDD_5 VDD_6 90 DDRA_MA6
DDRA_MA5 91 A8 A6 92 DDRA_MA4
93 A5 A4 94
DDRA_MA3 95 VDD_7 VDD_8 96 DDRA_MA2
DDRA_MA1 97 A3 A2 98 DDRA_MA0
99 A1 A0 100
DDRA_CLK0 101 VDD_9 VDD_10 102 DDRA_CLK1
6 DDRA_CLK0 CK0 CK1 DDRA_CLK1 6
DDRA_CLK0# 103 104 DDRA_CLK1#
6 DDRA_CLK0# CK0# CK1# DDRA_CLK1# 6
105 106 +1.35V
DDRA_MA10 107 VDD_11 VDD_12 108 DDRA_BS1#
DDRA_BS0# 109 A10/AP BA1 110 DDRA_RAS# DDRA_BS1# 6 Note:
6 DDRA_BS0# BA0 RAS# DDRA_RAS# 6 VREF trace width:20 mils at least

1
111 112
DDRA_WE# 113 VDD_13 VDD_14 114 DDRA_CS0# RD9 Spacing:20mils to other signal/planes
6 DDRA_WE# WE# S0# DDRA_CS0# 6
DDRA_CAS# 115 116 DDRA_ODT0 Trace width:20 mils 1.82K_0402_1% Place near DIMM scoket
6 DDRA_CAS# CAS# ODT0 DDRA_ODT0 5
117 118
DDRA_MA13 119 VDD_15 VDD_16 120 DDRA_ODT1
Space:20mils

2
DDRA_CS1# 121 A13 ODT1 122 DDRA_ODT1 5
6 DDRA_CS1# S1# NC_2
123 124 +VREF_CA RD10 1 2 0_0402_5%
125 VDD_17 VDD_18 126 DDR_SM_VREFCA 6
+VREF_CA @ 1
B 127 TEST VREF_CA 128 +VREF_CA 15 B
CD21
VSS_27 VSS_28

1
.1U_0402_10V6-K

DDRA_DQ32 129 130 DDRA_DQ36 0.022U_0402_16V7-K


DDRA_DQ33 131 DQ32 DQ36 132 DDRA_DQ37 RD11
DQ33 DQ37 1 1 2
CD22

133 134 CD23 1.82K_0402_1%


VSS_29 VSS_30

1
DDRA_DQS#4 135 136 2.2U_0603_6.3V6K
DDRA_DQS4 137 DQS4# DM4 138 CD@

2
139 DQS4 VSS_32 140 DDRA_DQ38 2 2 RD12
DDRA_DQ34 141 VSS_31 DQ38 142 DDRA_DQ39 24.9_0402_1%
DDRA_DQ35 143 DQ34 DQ39 144

2
145 DQ35 VSS_34 146 DDRA_DQ44
DDRA_DQ40 147 VSS_33 DQ44 148 DDRA_DQ45
DDRA_DQ41 149 DQ40 DQ45 150
DQ41 VSS_35 Layout Note: (10U_0603_6.3V)*2
151 152 DDRA_DQS#5
153 VSS_36 DQS5# 154 DDRA_DQS5 Place near DIMM
155 DM5 DQS5 156 (.1U_0402_10V)*4
DDRA_DQ42 157 VSS_37 VSS_38 158 DDRA_DQ46
DDRA_DQ43 159 DQ42 DQ46 160 DDRA_DQ47
161 DQ43 DQ47 162
DDRA_DQ48 163 VSS_39 VSS_40 164 DDRA_DQ52
DDRA_DQ49 165 DQ48 DQ52 166 DDRA_DQ53 +0.675VS
167 DQ49 DQ53 168
DDRA_DQS#6 169 VSS_41 VSS_42 170
DQS6# DM6
CD24

CD25

CD26

CD27

CD64

CD65
DDRA_DQS6 171 172
173 DQS6 VSS_44 174 DDRA_DQ54
VSS_43 DQ54
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

10U_0603_6.3V6M

10U_0603_6.3V6M
DDRA_DQ50 175 176 DDRA_DQ55
DDRA_DQ51 177 DQ50 DQ55 178
DQ51 VSS_46 1 1 1 1 1 1
179 180 DDRA_DQ60
DDRA_DQ56 181 VSS_45 DQ60 182 DDRA_DQ61
DDRA_DQ57 183 DQ56 DQ61 184
185 DQ57 VSS_48 186 DDRA_DQS#7 2 2 2 2 2 2
187 VSS_47 DQS7# 188 DDRA_DQS7
189 DM7 DQS7 190
A DDRA_DQ58 191 VSS_49 VSS_50 192 DDRA_DQ62 CD@ CD@ CD@ A
DDRA_DQ59 193 DQ58 DQ62 194 DDRA_DQ63
195 DQ59 DQ63 196
1 @ 2 0_0402_5%197 VSS_51 VSS_52 198
RD13 199 SA0 EVENT# 200 SMB_DATA_S3
+3VS 201 VDDSPD SDA 202 SMB_CLK_S3 SMB_DATA_S3 7,15,40
203 SA1 SCL 204 SMB_CLK_S3 7,15,40
1 1 VTT_1 VTT_2 +0.675VS
1

@ Security Classification LC Future Center Secret Data Title


CD28 CD29
0_0402_5%
205
GND1 GND2
206 1 0.65A@0.75V
2.2U_0603_6.3V6K .1U_0402_10V6-K 207 208 CD68
2 2 RD14 BOSS1 BOSS2 33P_0402_50V8J
Issued Date 2013/08/08 Deciphered Date 2013/08/05 DDRIII SO-DIMM A
@
2

2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
LCN_DAN06-K4406-0103 Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
ME@ For RF DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
ACLU1&ACLU2 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, December 19, 2013 Sheet 14 of 59
5 4 3 2 1
5 4 3 2 1

DDR_SB_VREFDQ 6

+1.35V
DDR3 SO-DIMM B Swap Table
Pin
+1.35V +1.35V Pin Name Net Name
Number

1
DDRB_DQ[0..63] 6
RD15 5 DQ0 DDRB_DQ17
1.82K_0402_1% 3A@1.5V DDRB_DQS[0..7] 6 7 DQ1 DDRB_DQ23
RD16 For RF 15 DQ2 DDRB_DQ18
JDDR2
17 DQ3 DDRB_DQ21

2
1 2 +VREF_DQ_DIMMB 1 2 DDRB_DQS#[0..7] 6
2_0402_5% 3 VREF_DQ VSS1 4 DDRB_DQ16 4 DQ4 DDRB_DQ16
VSS2 DQ4 DDRB_MA[0..15] 6

1.82K_0402_1%

CD30

2.2U_0603_6.3V6K

CD31

.1U_0402_10V6-K

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J
DDRB_DQ17 5
DQ0 DQ5
6 DDRB_DQ22 6 DQ5 DDRB_DQ22
1
0.022U_0402_16V7-K

1 1 DDRB_DQ23 7 8 1 1 1 16 DQ6 DDRB_DQ19


DQ1 VSS3

RD17

CD33

CD34

CD35
D 9 10 DDRB_DQS#2 @ @ @ D
11 VSS4 DQS#0 12 DDRB_DQS2
18 DQ7 DDRB_DQ20
1 DM0 DQS0 10 DQS#0 DDRB_DQS#2
CD32

13 14
2 2 DDRB_DQ18 15 VSS5 VSS6 16 DDRB_DQ19 2 2 2 12 DQS0 DDRB_DQS2
2

DDRB_DQ21 17 DQ2 DQ6 18 DDRB_DQ20


2 19 DQ3 DQ7 20
VSS7 VSS8
21 DQ8 DDRB_DQ3
CD@ DDRB_DQ3 21 22 DDRB_DQ2 23 DQ9 DDRB_DQ5
DDRB_DQ5 23 DQ8 DQ12 24 DDRB_DQ4
DQ9 DQ13 33 DQ10 DDRB_DQ6
1

25 26
RD18 DDRB_DQS#0 27 VSS9 VSS10 28 35 DQ11 DDRB_DQ1
24.9_0402_1% DDRB_DQS0 29 DQS#1 DM1 30 CPU_DRAMRST# 22 DQ12 DDRB_DQ2
DQS1 RESET# CPU_DRAMRST# 5,14
31
VSS11 VSS12
32 24 DQ13 DDRB_DQ4
DDRB_DQ6 33 34 DDRB_DQ0 34 DQ14 DDRB_DQ0
2

DDRB_DQ1 35 DQ10 DQ14 36 DDRB_DQ7


37 DQ11 DQ15 38 Layout Note: (10uF_0603_6.3V)*8 36 DQ15 DDRB_DQ7
DDRB_DQ8 39 VSS13 VSS14 40 DDRB_DQ13 27 DQS#1 DDRB_DQS#0
DDRB_DQ10 41 DQ16 DQ20 42 DDRB_DQ12 Place near DIMM (1U_0402_6.3V)*8 29 DQS1 DDRB_DQS0
43 DQ17 DQ21 44
DDRB_DQS#1 45 VSS15 VSS16 46 (.1U_0402_10V6-K)*4 39 DQ16 DDRB_DQ8
DDRB_DQS1 47 DQS#2 DM2 48
DQS2 VSS17 41 DQ17 DDRB_DQ10
49 50 DDRB_DQ9
DDRB_DQ14 51 VSS18 DQ22 52 DDRB_DQ11
51 DQ18 DDRB_DQ14
DDRB_DQ15 53 DQ18 DQ23 54 53 DQ19 DDRB_DQ15
55 DQ19 VSS19 56 DDRB_DQ31 +1.35V 40 DQ20 DDRB_DQ13
VSS20 DQ28
DDRB_DQ27 57
DQ24 DQ29
58 DDRB_DQ30 42 DQ21 DDRB_DQ12
DDRB_DQ26 59 60 50 DQ22 DDRB_DQ9
DQ25 VSS21

CD36

CD37

CD38

CD39

CD40

CD41

CD42

CD43
61 62 DDRB_DQS#3
63 VSS22 DQS#3 64 DDRB_DQS3
52 DQ23 DDRB_DQ11
DM3 DQS3 45 DQS#2 DDRB_DQS#1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
65 66
DDRB_DQ28 67 VSS23 VSS24 68 DDRB_DQ29 47 DQS2 DDRB_DQS1
DQ26 DQ30 1 1 1 1 1 1 1 1
DDRB_DQ24 69 70 DDRB_DQ25
71 DQ27 DQ31 72
VSS25 VSS26
57 DQ24 DDRB_DQ27
C C
2 2 2 2 2 2 2 2 59 DQ25 DDRB_DQ26
67 DQ26 DDRB_DQ28
DDRB_CKE0 73 74 DDRB_CKE1 69 DQ27 DDRB_DQ24
6 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 6
75 76 56 DQ28 DDRB_DQ31
VDD1 VDD2
77
NC1 A15
78 DDRB_MA15 CD@ CD@ 58 DQ29 DDRB_DQ30
DDRB_BS2# 79 80 DDRB_MA14 68 DQ30 DDRB_DQ29
6 DDRB_BS2# BA2 A14
81 82
DDRB_MA12 83 VDD3 VDD4 84 DDRB_MA11
70 DQ31 DDRB_DQ25
A12/BC# A11 62 DQS#3 DDRB_DQS#3

CD44

CD45

CD46

CD47

CD60

CD61

CD62

CD63
DDRB_MA9 85 86 DDRB_MA7
87 A9 A7 88 64 DQS3 DDRB_DQS3
VDD5 VDD6

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DDRB_MA8 89 90 DDRB_MA6
91 A8 A6 92
DDRB_MA5
A5 A4
DDRB_MA4 1 1 1 1 1 1 1 1 129 DQ32 DDRB_DQ33
93 94 131 DQ33 DDRB_DQ36
DDRB_MA3 95 VDD7 VDD8 96 DDRB_MA2
DDRB_MA1 97 A3 A2 98 DDRB_MA0
141 DQ34 DDRB_DQ39
99 A1 A0 100 2 2 2 2 2 2 2 2 143 DQ35 DDRB_DQ38
DDRB_CLK0 101 VDD9 VDD10 102 DDRB_CLK1 130 DQ36 DDRB_DQ37
6 DDRB_CLK0 CK0 CK1 DDRB_CLK1 6
6 DDRB_CLK0# DDRB_CLK0# 103
CK0# CK1#
104 DDRB_CLK1#
DDRB_CLK1# 6
CD@ CD@ CD@ CD@ 132 DQ37 DDRB_DQ32
105 106 140 DQ38 DDRB_DQ35
DDRB_MA10 107 VDD11 VDD12 108 DDRB_BS1#
DDRB_BS0# 109 A10/AP BA1 110 DDRB_RAS#
DDRB_BS1# 6 142 DQ39 DDRB_DQ34
6 DDRB_BS0# BA0 RAS# DDRB_RAS# 6 135 DQS#4 DDRB_DQS#4
111 112
DDRB_WE# 113 VDD13 VDD14 114 DDRB_CS0# 137 DQS4 DDRB_DQS4
6 DDRB_WE# WE# S0# DDRB_CS0# 6
DDRB_CAS# 115 116 DDRB_ODT0
6 DDRB_CAS# CAS# ODT0 DDRB_ODT0 5
117 118 147 DQ40 DDRB_DQ40
DDRB_MA13 119 VDD15 VDD16 120 DDRB_ODT1
A13 ODT1 DDRB_ODT1 5 149 DQ41 DDRB_DQ43
DDRB_CS1# 121 122
6 DDRB_CS1#
123 S1# NC2 124
157 DQ42 DDRB_DQ42
125 VDD17 VDD18 126 +VREF_CB RD19 1 2 0_0402_5% 159 DQ43 DDRB_DQ44
127 NCTEST VREF_CA 128 +VREF_CA 14 146 DQ44 DDRB_DQ45
@
VSS27 VSS28
.1U_0402_10V6-K
DDRB_DQ33 129
DQ32 DQ36
130 DDRB_DQ37 148 DQ45 DDRB_DQ41
B DDRB_DQ36 131 132 DDRB_DQ32 B
DQ33 DQ37 1 1 158 DQ46 DDRB_DQ46
133 134 CD48 CD49
DDRB_DQS#4 135 VSS29 VSS30 136 2.2U_0603_6.3V6K
160 DQ47 DDRB_DQ47
DDRB_DQS4 137 DQS#4 DM4 138 CD@ 152 DQS#5 DDRB_DQS#5
139 DQS4 VSS31 140 DDRB_DQ35 2 2 154 DQS5 DDRB_DQS5
DDRB_DQ39 141 VSS32 DQ38 142 DDRB_DQ34
143 DQ34 DQ39 144
DDRB_DQ38
DQ35 VSS33
163 DQ48 DDRB_DQ52
145 146 DDRB_DQ45 165 DQ49 DDRB_DQ51
DDRB_DQ40 147 VSS34 DQ44 148 DDRB_DQ41
DQ40 DQ45 Layout Note: (10U_0603_6.3V)*2 175 DQ50 DDRB_DQ50
DDRB_DQ43 149 150
151 DQ41 VSS35 152 DDRB_DQS#5 Place near DIMM 177 DQ51 DDRB_DQ48
153 VSS36 DQS#5 154 DDRB_DQS5 (.1U_0402_10V)*4 164 DQ52 DDRB_DQ49
DM5 DQS5
155
VSS37 VSS38
156 166 DQ53 DDRB_DQ53
DDRB_DQ42 157 158 DDRB_DQ46 174 DQ54 DDRB_DQ54
DDRB_DQ44 159 DQ42 DQ46 160 DDRB_DQ47
161 DQ43 DQ47 162
176 DQ55 DDRB_DQ55
DDRB_DQ52 163 VSS39 VSS40 164 DDRB_DQ49 +0.675VS 169 DQS#6 DDRB_DQS#6
DDRB_DQ51 165 DQ48 DQ52 166 DDRB_DQ53 171 DQS6 DDRB_DQS6
167 DQ49 DQ53 168
VSS41 VSS42
CD50

CD51

CD52

CD53

CD66

CD67
DDRB_DQS#6 169 170 181 DQ56 DDRB_DQ62
DDRB_DQS6 171 DQS#6 DM6 172
DQS6 VSS43 183 DQ57 DDRB_DQ57
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

10U_0603_6.3V6M

10U_0603_6.3V6M
173 174 DDRB_DQ54
DDRB_DQ50 175 VSS44 DQ54 176 DDRB_DQ55
191 DQ58 DDRB_DQ59
DQ50 DQ55 1 1 1 1 1 1 193 DQ59 DDRB_DQ63
DDRB_DQ48 177 178
179 DQ51 VSS45 180 DDRB_DQ56 180 DQ60 DDRB_DQ56
VSS46 DQ60
DDRB_DQ62 181
DQ56 DQ61
182 DDRB_DQ61 182 DQ61 DDRB_DQ61
DDRB_DQ57 183 184 2 2 2 2 2 2
DQ57 VSS47 192 DQ62 DDRB_DQ58
185 186 DDRB_DQS#7 CD@
187 VSS48 DQS#7 188 DDRB_DQS7
194 DQ63 DDRB_DQ60
189 DM7 DQS7 190 CD@ CD@ 186 DQS#7 DDRB_DQS#7
DDRB_DQ59 191 VSS49 VSS50 192 DDRB_DQ58 188 DQS7 DDRB_DQS7
DDRB_DQ63 193 DQ58 DQ62 194 DDRB_DQ60
A 195 DQ59 DQ63 196 A
RD20 1 2 @ 197 VSS51 VSS52 198
0_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3
1 2 201 VDDSPD SDA 202 SMB_DATA_S3 7,14,40
SMB_CLK_S3
+3VS 203 SA1 SCL 204 SMB_CLK_S3 7,14,40
RD21 10K_0402_5% +0.675VS
VTT1 VTT2
1 1 0.65A@0.75V
205 206 1
CD54 CD55 G1 G2 CD69
Security Classification LC Future Center Secret Data Title
2.2U_0603_6.3V6K .1U_0402_10V6-K LCN_DAN06-K4406-0102 33P_0402_50V8J
2 2 @
ME@ 2 Issued Date 2013/08/08 Deciphered Date 2013/08/05 DDRIII SO-DIMM B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
For RF DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
ACLU1&ACLU2 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, December 19, 2013 Sheet 15 of 59
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 16 of 59
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 17 of 59
5 4 3 2 1
5 4 3 2 1

RECOMMENDED SETTINGS
CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE X = DESIGN DEPENDANT
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE
Power-Up/Down Sequence
RECOMMENDED
"Topaz" has the following requirements with regards to power-supply sequencing to MLPS Bit Strap Name Description
SETTINGS
avoid damaging the ASIC: PS_0[1] ROM_CONFIG[0] Define the ROM type when STRAP_BIOS_ROM_EN = 1,
PS_0[2] ROM_CONFIG[1] Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.
PS_0[3] ROM_CONFIG[2] X
All the ASIC supplies must reach their respective nominal voltages within 20 ms 100 = 256MB

D of the start of the ramp-up sequence, though a shorter ramp-up duration is PS_0[4] N/A Reserved for internal use only. Must be 1 at reset. 1 D

preferred. The maximum slew rate on all rails is 50 mV/μs. AUD_PORT_CONN_ The LSB (least significant bit) of the strap option that
It is recommended that the 3.3-V rail ramp up first. PS_0[5] PINSTRAP[0] indicates the number of audio-capable display outputs. 1
The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 μs 1 = PCIe GEN3 is supported.
before VDDC, VDDCI, and VMEMIO start to ramp up. PS_1[1] STRAP_BIF_GEN3_EN_A 0 = PCIe GEN3 is not supported. 0= Not support X
The power rails that are shared with other components on the system should be 0 = The CLKREQB power management capability is disabled
gated for the dGPU so that when the dGPU is powered down (for example PS_1[2] STRAP_BIF_CLK_PM_EN 1 = The CLKREQB power management capability is enabled 0

AMD PowerXpress idle state), all the power rails are removed from the dGPU. PS_1[3] N/A Reserved for internal use only. Must be 0 at reset. 0
The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/μs). STRAP_TX_CFG_DRV_ 0 = The transmitter half-swing is enabled
For power down, reversing the ramp-up sequence is recommended. PS_1[4] FULL_SWING 1 = The transmitter full-swing is enabled 1

0 = Tx deemphasis disabled.
PS_1[5] STRAP_TX_DEEMPH_EN 1 = Tx deemphasis enabled. 1= Enable X

PS_2[1] N/A Reserved. 0

PS_2[2] N/A Reserved. 0


0 ~ 20ms
0 = Disable the external BIOS ROM device.
PS_2[3] STRAP_BIOS_ROM_EN 1 = Enable the external BIOS ROM device. 0= Disable X

VDDR3(+3VGS) 0 = VGA controller capacity enabled.


0 ~ 20ms PS_2[4] STRAP_BIF_VGA_DIS 1 = The device will not be recognized as the system’s VGA controller. 1

PS_2[5] N/A Reserved 1

C
VDD_CT(+1.8VGS) Board configuration related strapping, such as for memory ID
C
PS_3[1] BOARD_CONFIG[0] 000 = Hynix 256M*16 001 = Hynix 128M*16 X
PS_3[2] BOARD_CONFIG[1] 100 = Samsung 256M*16 011 = Samsung 128M*16
PS_3[3] BOARD_CONFIG[2] 010 = Micron 256M*16 111 = Micron 128M*16

PCIE_VDDC(+0.95VGS) Determines the maximum number of digital display audio endpoints


that will be presented to the OS and user.(Combine with PS_0[5])
10us min. 111 = No usable endpoints.
AUD_PORT_CONN_ 110 = One usable endpoint.
PS_3[4] PINSTRAP[1] 101 = Two usable endpoints. 111= No usable endpoints.
VDDR1(+1.35VGS) PS_3[5] AUD_PORT_CONN_
100 = Three usable endpoints.
011 = Four usable endpoints.
11
PINSTRAP[2] 010 = Five usable endpoints.
001 = Six usable endpoints.
000 = All endpoints are usable.
VDDC/VDDCI(+VGA_CORE) 100ms min.

PERSTb(GPU_RST#) 100us min. VRAM ID config


VRAM ID PU resistor PD resistor
Memory Type
REFCLK(CLK_PCIE_VGA) PS_3[3:1] RV33 RV36

Hynix
100 4.53K 4.99K
H5TC2G63FFR-11C
B B
128Mx16 Micron
111 4.75K NC
MT41J128M16JT-093G

Samsung
110 3.4K 10K
K4W2G1646Q-BC1A

Hynix
000 NC 4.75K
H5TC4G63AFR-11C

Micron
256Mx16 010 4.53K 2K
MT41J256M16HA-093G

Samsung
001 8.45K 2K
K4W4G1646D-BC1A

Micron
011 6.98K 4.99K
MT41K256M16HA-107G

A A

Security Classification
Classification LC Future Center Secret Data Title
Issued Date 2013/08/08 Deciphered Date 2013/08/05 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 18 of 59
5 4 3 2 1
5 4 3 2 1

PCIE_CTX_C_GRX_P[3..0] PCIE_CRX_GTX_P[3..0]
9 PCIE_CTX_C_GRX_P[3..0] PCIE_CRX_GTX_P[3..0] 9
UV1A
PCIE_CTX_C_GRX_N[3..0] PCIE_CRX_GTX_N[3..0]
9 PCIE_CTX_C_GRX_N[3..0] PCIE_CRX_GTX_N[3..0] 9

PCIE_CTX_C_GRX_P0 AF30 AH30 PCIE_CRX_C_GTX_P0 .1U_0402_10V6-K 1 2 PX@ CV1 PCIE_CRX_GTX_P0


PCIE_CTX_C_GRX_N0 AE31 PCIE_RX0P PCIE_TX0P AG31 PCIE_CRX_C_GTX_N0 .1U_0402_10V6-K 1 2 PX@ CV2 PCIE_CRX_GTX_N0
PCIE_RX0N PCIE_TX0N

D PCIE_CTX_C_GRX_P1 AE29 AG29 PCIE_CRX_C_GTX_P1 .1U_0402_10V6-K 1 2 PX@ CV3 PCIE_CRX_GTX_P1 D


PCIE_CTX_C_GRX_N1 AD28 PCIE_RX1P PCIE_TX1P AF28 PCIE_CRX_C_GTX_N1 .1U_0402_10V6-K 1 2 PX@ CV4 PCIE_CRX_GTX_N1
PCIE_RX1N PCIE_TX1N

PCIE_CTX_C_GRX_P2 AD30 AF27 PCIE_CRX_C_GTX_P2 .1U_0402_10V6-K 1 2 PX@ CV5 PCIE_CRX_GTX_P2


PCIE_CTX_C_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PCIE_CRX_C_GTX_N2 .1U_0402_10V6-K 1 2 PX@ CV6 PCIE_CRX_GTX_N2
PCIE_RX2N PCIE_TX2N

PCIE_CTX_C_GRX_P3 AC29 AD27 PCIE_CRX_C_GTX_P3 .1U_0402_10V6-K 1 2 PX@ CV7 PCIE_CRX_GTX_P3


PCIE_CTX_C_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PCIE_CRX_C_GTX_N3 .1U_0402_10V6-K 1 2 PX@ CV8 PCIE_CRX_GTX_N3
PCIE_RX3N PCIE_TX3N

AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N

AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N

Y30 AB27
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N

W29 Y27
V28 PCIE_RX7P PCIE_TX7P Y26
PCIE_RX7N PCIE_TX7N

V30 W24
C U31 NC#V30 NC#W24 W23 C
NC#U31 NC#W23

U29 V27
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26

PCI EXPRESS INTERFACE


T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23

R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27

P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23

N29 P27
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26

M30 P24
L31 NC#M30 NC#P24 P23
NC#L31 NC#P23

L29 M27
K30 NC#L29 NC#M27 N26
B NC#K30 NC#N26 B

CLOCK
CLK_PCIE_GPU AK30
8 CLK_PCIE_GPU PCIE_REFCLKP
CLK_PCIE_GPU# AK32
8 CLK_PCIE_GPU# PCIE_REFCLKN
+0.95VGS
CALIBRATION
Y22 RV3 1 PX@ 2 1.69K_0402_1%
PCIE_CALR_TX
1K_0402_1% 1 PX@ 2 RV4 N10 AA22 RV5 1 PX@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX

GPU_RST# AL27
20 GPU_RST# PERSTB
1

JET-S3-LE_FCBGA631
RV6 @ RV27 1 @ 2 0_0402_5%
100K_0402_5%
PX@
2

RV7 1 @ 2 0_0402_5% DV3 PX@


GPU_RST# 2
1 GPU_PWROK
GPU_PWROK 58
+3VGS VGA_PWRGD 3
9,44,58 VGA_PWRGD
BAT54AWT1G_SOT323-3
5

A UV2 A
VCC

1
4 PXS_RST# IN1 4 GPU_RST#
2 OUT
GND

8,37,40,44 PLT_RST# IN2

Security Classification LC Future Center Secret Data Title


MC74VHC1G08DFT2G_SC70-5
3

PX@ Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_PCIE


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A3 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 19 of 59
5 4 3 2 1
5 4 3 2 1

+3VGS UV1B RECOMMENDED SETTINGS


+1.8VGS
CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
+3VGS 1 = INSTALL 10K RESISTOR
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE X = DESIGN DEPENDANT
.1U_0402_10V6-K .1U_0402_10V6-K AF2 GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE
NC#AF2

2
1 2 CV222 1 2 CV223 AF4
RV235 RV236 @ @ NC#AF4
10K_0402_5% 10K_0402_5% N9 AG3 MLPS Bit Strap Name Description RECOMMENDED
@ UV11 L9 DBG_DATA16 NC#AG3 AG5 SETTINGS
@ DBG_DATA15 NC#AG5
AE9 DPA PS_0[1] ROM_CONFIG[0] Define the ROM type when STRAP_BIOS_ROM_EN = 1,

1
1 8 Y11 DBG_DATA14 AH3 PS_0[2] ROM_CONFIG[1] Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.
VCC(A) VCC(B) AE8 DBG_DATA13 NC#AH3 AH1 PS_0[3] ROM_CONFIG[2] X
GPU_VID3 RV121 1 @ 2 2 7 RV239 1 @ 2 GPU_SVD AD9 DBG_DATA12 NC#AH1 100 = 256MB
33_0402_5% 1A 1B 33_0402_5% AC10 DBG_DATA11 AK3
GPU_VID4 RV122 1 @ 2 3 6 RV240 1 @ 2 GPU_SVC AD7 DBG_DATA10 NC#AK3 AK1 PS_0[4] N/A Reserved for internal use only. Must be 1 at reset. 1
33_0402_5% 2A 2B 33_0402_5% AC8 DBG_DATA9 NC#AK1
DVO
5 4 AC7 DBG_DATA8 AK5 AUD_PORT_CONN_ The LSB (least significant bit) of the strap option that
DIR GND DBG_DATA7 NC#AK5
2

2
AB9 AM3 PS_0[5] PINSTRAP[0] indicates the number of audio-capable display outputs. 1
RV237 RV238 AB8 DBG_DATA6 NC#AM3
10K_0402_5% 74AVCH2T45GD_XSON8_3X2 AB7 DBG_DATA5 AK6 1 = PCIe GEN3 is supported.
10K_0402_5% DBG_DATA4 NC#AK6
@ AB4 AM5 PS_1[1] STRAP_BIF_GEN3_EN_A 0 = PCIe GEN3 is not supported. 0= Not support X
@ DBG_DATA3 NC#AM5
AB2 DPB
@
1

Y8 DBG_DATA2 AJ7 0 = The CLKREQB power management capability is disabled


D
RV241 2 @ 1 Y7 DBG_DATA1 NC#AJ7 AH6 PS_1[2] STRAP_BIF_CLK_PM_EN 1 = The CLKREQB power management capability is enabled 0
D
+3VGS DBG_DATA0 NC#AH6
10K_0402_5%
AK8 PS_1[3] N/A Reserved for internal use only. Must be 0 at reset. 0
NC#AK8

10U_0603_6.3V6M
.1U_0402_10V6-K
2 1 AL7
NC#AL7 STRAP_TX_CFG_DRV_ 0 = The transmitter half-swing is enabled
CV236 CV31 PS_1[4] FULL_SWING 1 = The transmitter full-swing is enabled 1
@ @ W6
1 2 V6 NC#W6 0 = Tx deemphasis disabled.
NC#V6 V4 PS_1[5] STRAP_TX_DEEMPH_EN 1 = Tx deemphasis enabled. 1= Enable X
AC6 NC#V4 U5
AC5 NC#AC6 NC#U5 PS_2[1] N/A Reserved. 0
NC#AC5 W3 VGA_VSSI_SEN 1 TV10 PAD @
Reserve NC#W3
AA5 V2 PS_2[2] N/A Reserved. 0
AA6 NC#AA5 NC#V2
DPC
+3VGS +1.8VGS NC#AA6 Y4 0 = Disable the external BIOS ROM device.
NC#Y4 W5 PS_2[3] STRAP_BIOS_ROM_EN 1 = Enable the external BIOS ROM device. 0= Disable X
NC#W5
10K_0402_5% 1 @ 2 RV8 GPU_GPIO5 RV93 1 2 TOPAZ@ BP_0 U1 AA3 PLL_ANALOG_OUT RV94 1 @ 2 0 = VGA controller capacity enabled.
4.7K_0402_5% TV11 @ 1 VGA_VDDCI_SEN W1 NC#U1 NC#AA3 Y2 16.2K_0402_1% PS_2[4] STRAP_BIF_VGA_DIS 1 = The device will not be recognized as the system’s VGA controller. 1
RV95 1 2 TOPAZ@ PAD BP_1 U3 NC#W1 NC#Y2
4.7K_0402_5% Y6 NC#U3 J8 PS_2[5] N/A Reserved 1
NC#Y6 NC#J8 Reserve for Topaz
10K_0402_5% 1 @ 2 RV9 GPU_GPIO0 TV12 @ 1 PLL_ANALOG_IN AA1
10K_0402_5% 1 @ 2 RV12 GPU_GPIO8 PAD NC#AA1 Board configuration related strapping, such as for memory ID
10K_0402_5% 1 @ 2 RV13 GPU_GPIO9 PS_3[1] BOARD_CONFIG[0] 000 = Hynix 256M*16 001 = Hynix 128M*16 X
10K_0402_5% 1 @ 2 RV14 GPU_GPIO10 PS_3[2] BOARD_CONFIG[1] 100 = Samsung 256M*16 011 = Samsung 128M*16
10K_0402_5% 1 @ 2 RV15 GPU_GPIO11 PS_3[3] BOARD_CONFIG[2] 010 = Micron 256M*16 111 = Micron 128M*16
10K_0402_5% 1 @ 2 RV96 GPU_GPIO12 I2C
10K_0402_5% 1 @ 2 RV17 GPU_GPIO13 Determines the maximum number of digital display audio endpoints
10K_0402_5% 1 @ 2 RV18 GPU_GPIO22 R1 that will be presented to the OS and user.(Combine with PS_0[5])
10K_0402_5% 1 @ 2 RV97 GPU_VID1 R3 SCL 111 = No usable endpoints.
10K_0402_5% 1 @ 2 RV98 GPU_GPIO21 SDA TOPAZ@ AUD_PORT_CONN_ 110 = One usable endpoint.
10K_0402_5% 1 @ 2 RV99 GPU_VID5 AM26 DIECRACKMON RV117 1 2 PS_3[4] PINSTRAP[1] 101 = Two usable endpoints. 111= No usable endpoints.
10K_0402_5% 1 @ 2 RV106 GPU_VID2 NC_R AK26 10K_0402_5% 100 = Three usable endpoints. 11
GPU_GPIO0 U6 GENERAL PURPOSE I/ONC_AVSSN#AK26 PS_3[5] AUD_PORT_CONN_ 011 = Four usable endpoints.
+VGA_CORE_GPIO1 U10 GPIO_0 AL25 PINSTRAP[2] 010 = Five usable endpoints.
Reserve NC_GPIO_1 NC_G 001 = Six usable endpoints.
+VGA_CORE_GPIO2 T10 AJ25
U8 NC_GPIO_2 NC_AVSSN#AJ25 000 = All endpoints are usable.
VGA_SMB_DATA
RB751V-40_SOD323-2 VGA_SMB_CLK U7 SMBDATA AH24
DV1 1 2 @ GPU_GPIO5 T9 SMBCLK NC_B AG25
44 VGA_AC_DET T8 GPIO_5_AC_BATT NC_AVSSN#AG25
GPU_VID5
T7 GPIO_6 DAC1 AH26
GPU_GPIO8 P10 NC_GPIO_7 NC_HSYNC AJ27 4.7K_0402_5% 1 TOPAZ@ 2 RV20 +3VGS +VDDIO_GPU +1.8VGS
+VGA_CORE GPU_GPIO9 P4 GPIO_8_ROMSO NC_VSYNC
GPU_GPIO10 P2 GPIO_9_ROMSI
GPIO_10_ROMSCK SVC SVD Output Voltage (V)
RV100 1 2 0_0402_5% +VGA_CORE_GPIO1 GPU_GPIO11 N6 AD22 Pull down for none OBFF design RV234 1 JET@ 2 RV203 1 TOPAZ@ 2
TOPAZ@ @ PAD TV3 1 GPU_GPIO12 N5 NC_GPIO_11 NC_RSET 0 0 1.1 0_0402_5% 0_0402_5%
RV101 1 2 0_0402_5% +VGA_CORE_GPIO2 GPU_GPIO13 N3 NC_GPIO_12 AG24
TOPAZ@ +VGA_CORE_GPIO14 Y9 NC_GPIO_13 NC_AVDD AE22 0 1 1.0
RV102 1 2 0_0402_5% +VGA_CORE_GPIO14 GPU_SVD 0_0402_5% 1 JET@ 2 RV103 GPU_VID3 N1 NC_GPIO_14
GPIO_15_PWRCNTL_0
NC_AVSSQ *
C TOPAZ@ 10K_0402_5% 1 @ 2 RV22 GPU_GPIO16 M4 AE23 1 0 0.9 C
GPIO_16 NC_VDD1DI

2
RV104 1 2 0_0402_5% +VGA_CORE_GPIO18 R6 AD23
58 GPU_HOT# GPIO_17_THERMAL_INT NC_VSS1DI
TOPAZ@ +VGA_CORE_GPIO18 W10 1 1 0.8 RV205 RV204 RV208
10K_0402_5% 1 PX@ 2 RV23 GPIO_19_CTF M2 NC_GPIO_18 10K_0402_5% 10K_0402_5% 10K_0402_5%
GPIO_19_CTF FutureASIC/SEYMOUR/PARK
GPU_SVC 0_0402_5% 1 JET@ 2 RV105 GPU_VID4 P8 AM12 CEC_1 1 @ TV5 PX@ @ @
GPU_GPIO21 P7 GPIO_20_PWRCNTL_1 CEC_1 PAD

1
GPU_GPIO22 N8 GPIO_21 GPU_SVD
GPU_VID2 AK10 GPIO_22_ROMCSB AK12 GPU_SVD_R RV107 1TOPAZ@ 2 0_0402_5% GPU_SVC
AM10 GPIO_29 NC_SVI2#AK12 AL11 GPU_SVD 58
GPU_VID1 GPU_SVT_R RV108 1TOPAZ@ 2 0_0402_5% GPU_SVT
1 2 RV124 N7 GPIO_30 NC_SVI2#AL11 AJ11 GPU_SVT 58
0_0402_5% @ GPU_CLKREQ#_R GPU_SVC_R RV109 1TOPAZ@ 2 0_0402_5%
8 GPU_CLKREQ# CLKREQB NC_SVI2#AJ11 GPU_SVC 58

2
2

2
JTAG_TRSTB L6 RV209
+3VGS JTAG_TDI L5 JTAG_TRSTB RV206 RV207 10K_0402_5%
JTAG_TCK L3 JTAG_TDI 10K_0402_5% 10K_0402_5% @
PAD JTAG_TMS L1 JTAG_TCK AL13 GENLK_CLK 1 TV1 PAD @ @ PX@

1
10K_0402_5% 1 @ 2 RV37 JTAG_TRSTB TV7 @ 1JTAG_TDO K4 JTAG_TMS NC_GENLK_CLK AJ13 GENLK_VSYNC 1 TV2 PAD @

1
10K_0402_5% 1 @ 2 RV38 JTAG_TDI RV34 1 PX@ 2 TESTEN K7 JTAG_TDO NC_GENLK_VSYNC
10K_0402_5% 1 @ 2 RV39 JTAG_TMS 1K_0402_5% AF24 TESTEN
NC#AF24 AG13
10K_0402_5% 1 @ 2 RV40 JTAG_TCK NC_SWAPLOCKA AH12
0_0402_5% 1 2 RV110 AB13 NC_SWAPLOCKB
+VGA_CORE NC_GENERICA
TOPAZ@ W8 +1.8VGS +1.8VGS
0_0402_5% 1 2 RV111 W9 NC_GENERICB
TOPAZ@ W7 NC_GENERICC AC19 PS_0
NC_GENERICD PS_0

1
0_0402_5% 1 2 RV112 AD10
TOPAZ@ AJ9 NC_GENERICE_HPD4 AD19 PS_1 RV25 RV26
AL9 NC#AJ9 PS_1 8.45K_0402_1% 10K_0402_5%
DBG_CNTL0 AE17 PS_2 PX@ @
AC14 PS_2

2
PAD TV6 @ 1 PX_EN AB16 NC_HPD1 AE20 PS_3 PS_0 PS_1
PX_EN PS_3

1
4.7K_0402_5% 1 @ 2 RV31 1 1
PX@ 2 1 CV25 XTALIN AE19 RV28 CV15 RV29 CV16
AC16 TS_A 2K_0402_1% .01U_0402_16V7-K 4.75K_0402_1% .01U_0402_16V7-K
10P_0402_50V8J NC_DBG_VREFG PX@ @ PX@ @
If need stuff RV31. use 0ohm resistor. 2 2

2
DDC/AUX
2

AE6
PLL/CLOCK NC_DDC1CLK AE5
27MHZ_10PF_7V27000050

YV1
GND1

OSC1

PX@ NC_DDC1DATA +1.8VGS +1.8VGS


1

AD2 +VGA_CORE
NC_AUX1P
1
RV46 AD4
NC_AUX1N

1
1M_0402_5% RV19
GND2
OSC2

PX@ AC11 RV113 1 TOPAZ@ 2 0_0402_5% 100_0402_1% RV32 RV33


NC_DDC2CLK AC13 RV114 1 2 0_0402_5% @ 10K_0402_5% 8.45K_0402_1%
2

NC_DDC2DATA TOPAZ@ @ @
2

XTALIN AM28 AD13


3

2
XTALOUT AK28 XTALIN NC_AUX2P AD11 PS_2 PS_3
XTALOUT NC_AUX2N
B B

1
10K_0402_5% 1 PX@ 2 RV45 XO_IN AC22 AD20 VGA_VSS_SEN_R RV125 1 TOPAZ@ 2 0_0402_5% 1 1
1 XO_IN NC#AD20 VGA_VSS_SEN 58
10K_0402_5% PX@ 2 RV50 XO_IN2 AB22 AC20 VGA_CORE_SEN_R RV126 1 2 0_0402_5% RV35 CV18 RV36 CV19
XO_IN2 NC#AC20 VGA_CORE_SEN 58
TOPAZ@ 4.75K_0402_1% .01U_0402_16V7-K 2K_0402_1% .01U_0402_16V7-K
PX@ 2 1 CV32 XTALOUT AE16 PX@ @ @ @
NC#AE16 AD16 2 2

2
10P_0402_50V8J NC#AD16
1

SEYMOUR/FutureASIC AC1
PAD TV13@ 1 GPU_DPLUS T4 NC_DDCVGACLK AC3 RV16
PAD TV14@ 1 GPU_DMINUS T2 DPLUS THERMAL NC_DDCVGADATA 100_0402_1%
DMINUS @
2

+3VS RV41 1 @ 2 GPIO_28_FDO R5


10K_0402_5% LV3 1 2 PX@ +TSVDD AD17 GPIO28_FDO
+1.8VGS TSVDD Capacitor Value (nF) Bits [5:4] R_pu (Ω) R_pd (Ω) Bits [3:1]
BLM15AG121SH1D_2P AC17
TSVSS +VGA_CORE 680 00 NC 4750 000
CV21
1U_0402_6.3V6K
2

(1.8V@13mA TSVDD) 1
RV42 82 01 8450 2000 001
10K_0402_5% JET-S3-LE_FCBGA631
JET@ @ For Topaz, RV16/RV19 stuff 100ohm 10 10 4530 2000 010
2
PX@

for Jet, RV16/RV19 stuff 0hm.


1

NC 11 6980 4990 011

4530 4990 100


For Jet: Connect GPIO_28 to 10K pull
down to enable MLPS. 3240 5620 101
For Topaz: default is MLPS mode
3400 10000 110
+3VGS
4750 NC 111

Note: 0402 1% resistors are required.


1

RV127 RV21 1 @ 2 0_0402_5%


WRST# 44
20K_0402_5%
@ RV24 1 @ 2 0_0402_5%
H_THRMTRIP# 9
2
3

E
QV12
B
2 Internal VGA Thermal Sensor
MMBT3906_SOT23-3 +3VGS
@
C +3VGS
1

C
RV128 1 @ 2 2 QV13
1

2.2K_0402_5% B MMBT3904WH_SOT323-3
CV215

.1U_0402_10V6-K

E @ RV43 RV44
3
1

45.3K_0402_1% 45.3K_0402_1%
G

1
@ RV129 RV130 RV131 PX@ PX@
GPU_RST# 1 2 DV2 20K_0402_5% 20K_0402_5% 100K_0402_5%
19 GPU_RST#
2

FOR ONE TIME CTF USE 47K @ @ @


A SDM10U45LP-7_DFN1006-2-2 FOR RESETABLE CTF USE 2K 2 VGA_SMB_CLK QV4A 1 6 PX@ A
S

EC_SMB_CK2 7,39,44
2

1 2

C 2N7002KDWH_SOT363-6
G

GPIO_19_CTF 1 @ 2 RV132 RV133 1 @ 2 2


47K_0402_5% 47K_0402_5% B
CV216

.01U_0402_16V7-K

E
3
1

QV14 VGA_SMB_DATA QV4B 4 3 PX@


S

1 EC_SMB_DA2 7,39,44
D

RV134 MMBT3904_SOT23-3
100K_0402_5% @ 2N7002KDWH_SOT363-6
@
2
@
2

RV10 1 @ 2 0_0402_5% RV135 1 @ 2 0_0402_5%


4 GPIO52
Security Classification LC Future Center Secret Data Title
RV11 1 @ 2 0_0402_5%
4 GPIO53
Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_Main_MSIC
Reserve for NV DGPU(near GPU) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Tuesday, December 24, 2013 Sheet 20 of 59
5 4 3 2 1
5 4 3 2 1

UV1F
+VGA_CORE

D D
AB11 RV115 1 2 0_0402_5% TOPAZ@
NC_VARY_BL AB12 RV116 1 2 0_0402_5% TOPAZ@
NC_DIGON

AL15
NC_UPHYAB_TMDPA_TX0N AK14
NC_UPHYAB_TMDPA_TX0P
AH16
NC_UPHYAB_TMDPA_TX1N AJ15
NC_UPHYAB_TMDPA_TX1P
AL17
NC_UPHYAB_TMDPA_TX2N AK16
NC_UPHYAB_TMDPA_TX2P
AH18
NC_UPHYAB_TMDPA_TX3N AJ17
NC_UPHYAB_TMDPA_TX3P
AL19
NC_TXOUT_L3P AK18
NC_TXOUT_L3N
C C
TMDP

AH20
NC_UPHYAB_TMDPB_TX0N AJ19
NC_UPHYAB_TMDPB_TX0P
AL21
NC_UPHYAB_TMDPB_TX1N AK20
NC_UPHYAB_TMDPB_TX1P
AH22
NC_UPHYAB_TMDPB_TX2N AJ21
NC_UPHYAB_TMDPB_TX2P
AL23
NC_UPHYAB_TMDPB_TX3N AK22
NC_UPHYAB_TMDPB_TX3P
AK24
NC_TXOUT_U3P AJ23
NC_TXOUT_U3N

JET-S3-LE_FCBGA631
B @ B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_TMDP


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 21 of 59
5 4 3 2 1
5 4 3 2 1

+1.8VGS (1.8V@40mA DP_VDDR)


@
RV48 1 2 +DP_VDDR
UV1G UV1E

PX@

PX@
0_0603_5%
NC/DP POWER

10U_0603_6.3V6M

1U_0402_6.3V6K
DP POWER
1 1
AG15 AE11 AA27 A3
AG16 NC_DP_VDDR#AG15 NC#AE11 AF11 AB24 GND_1 GND_65 A30
D D
AF16 NC_DP_VDDR#AG16 NC#AF11 AE13 AB32 GND_2 GND_66 AA13
2 2 AG17 NC_DP_VDDR#AF16 NC#AE13 AF13 AC24 GND_3 GND_67 AA16

CV39

CV40
AG18 NC_DP_VDDR#AG17 NC#AF13 AG8 AC26 GND_4 GND_68 AB10
AG19 NC_DP_VDDR#AG18 NC#AG8 AG10 AC27 GND_5 GND_69 AB15
AF14 NC_DP_VDDR#AG19 NC#AG10 AD25 GND_6 GND_70 AB6
DP_VDDR#AF14 AD32 GND_7 GND_71 AC9
AE27 GND_8 GND_72 AD6
+0.95VGS AF32 GND_9 GND_73 AD8
(0.95V@32mA DP_VDDC) GND_10 GND_74
@ AG27 AE7
RV47 1 2 +DP_VDDC AG20 AF6 AH32 GND_11 GND_75 AG12
AG21 NC_DP_VDDC#AG20 NC#AF6 AF7 K28 GND_12 GND_76 AH10

CV38

CV37
0_0603_5%
AF22 NC_DP_VDDC#AG21 NC#AF7 AF8 K32 GND_13 GND_77 AH28
AG22 NC_DP_VDDC#AF22 NC#AF8 AF9 L27 GND_14 GND_78 B10

1U_0402_6.3V6K

.1U_0402_16V7K
AD14 NC_DP_VDDC#AG22 NC#AF9 M32 GND_15 GND_79 B12
1 1 DP_VDDC#AD14 GND_16 GND_80
N25 B14
N27 GND_17 GND_81 B16
P25 GND_18 GND_82 B18
2 2 AG14 AE1 P32 GND_19 GND_83 B20
NC_DP_VSSR_1 NC#AE1 GND_20 GND_84
PX@

PX@
AH14 AE3 R27 B22
AM14 NC_DP_VSSR_2 NC#AE3 AG1 T25 GND_21 GND_85 B24
AM16 NC_DP_VSSR_3 NC#AG1 AG6 T32 GND_22 GND_86 B26
AM18 NC_DP_VSSR_4 NC#AG6 AH5 U25 GND_23 GND_87 B6
AF23 NC_DP_VSSR_5 NC#AH5 AF10 U27 GND_24 GND_88 B8
AG23 NC_DP_VSSR_6 NC#AF10 AG9 V32 GND_25 GND_89 C1
C
AM20 NC_DP_VSSR_7 NC#AG9 AH8 W25 GND_26 GND_90 C32 C
AM22 NC_DP_VSSR_8 NC#AH8 AM6 W26 GND_27 GND_91 E28
AM24 NC_DP_VSSR_9 NC#AM6 AM8 W27 GND_28 GND_92 F10
AF19 NC_DP_VSSR_10 NC#AM8 AG7 Y25 GND_29 GND_93 F12
AF20 NC_DP_VSSR_11 NC#AG7 AG11 Y32 GND_30 GND_94 F14
AE14 NC_DP_VSSR_12 NC#AG11 GND_31 GND_95 F16
DP_VSSR_13 GND_96 F18
GND_97 F2
GND_98 F20
RV49 1 2 @ AF17 AE10 M6 GND_99 F22
150_0402_1% NC_UPHYAB_DP_CALR NC#AE10 N13 GND_32 GND_100 F24
N16 GND_33 GND_101 F26
N18 GND_34 GND_102 F6
JET-S3-LE_FCBGA631 N21 GND_35 GND
GND_103 F8
@ P6 GND_36 GND_104 G10
P9 GND_37 GND_105 G27
R12 GND_38 GND_106 G31
R15 GND_39 GND_107 G8
R17 GND_40 GND_108 H14
R20 GND_41 GND_109 H17
T13 GND_42 GND_110 H2
T16 GND_43 GND_111 H20
T18 GND_44 GND_112 H6
T21 GND_45 GND_113 J27
T6 GND_46 GND_114 J31
B B
U15 GND_47 GND_115 K11
U17 GND_48 GND_116 K2
U20 GND_49 GND_117 K22
U9 GND_50 GND_118 K6
V13 GND_51 GND_119
V16 GND_52
V18 GND_53
Y10 GND_54
Y15 GND_55
Y17 GND_56
Y20 GND_57
R11 GND_58 A32
T11 GND_59 VSS_MECH_1 AM1
AA11 GND_60 VSS_MECH_2 AM32
M12 GND_61 VSS_MECH_3
N11 GND_62
V11 GND_63
GND_64

JET-S3-LE_FCBGA631
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_DP Power


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 22 of 59
5 4 3 2 1
5 4 3 2 1

+1.35VGS
For DDR3/GDDR5, 2A@1.35V

CV48

CV51

CV52

CV53

CV54

CV55

CV56

CV217
10U_0603_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

.1U_0402_16V7K

.01U_0402_16V7-K
1 1 1 1 1 1 1 1 UV1D +1.8VGS
(1.8V@100mA PCIE_PVDD)
AM30
PCIE_PVDD

PCIE
MEM I/O

CV46

CV47
2 2 2 2 2 2 2 2

PX@
H13 AB23

10U_0603_6.3V6M
1U_0402_6.3V6K
VDDR1_1 NC#AB23

PX@

PX@

PX@

PX@

PX@

PX@

PX@
H16 AC23 1 1
H19 VDDR1_2 NC#AC23 AD24
J10 VDDR1_3 NC#AD24 AE24
J23 VDDR1_4 NC#AE24 AE25
VDDR1_5 NC#AE25 2 2

PX@

PX@
J24 AE26
J9 VDDR1_6 NC#AE26 AF25
D K10 VDDR1_7 NC#AF25 AG26 D
+1.8VGS +VDD_CT K23 VDDR1_8 NC#AG26 +0.95VGS
(1.8V@13mA VDD_CT) VDDR1_9
K24 (0.95V@1A PCIE_VDDC)
LV7 1 @ 2 0_0402_5% K9 VDDR1_10 L23
L11 VDDR1_11 PCIE_VDDC_1 L24

CV90
L12 VDDR1_12 PCIE_VDDC_2 L25

CV64

CV65

CV66

CV67

CV68

CV69

CV71
1U_0402_6.3V6K
L13 VDDR1_13 PCIE_VDDC_3 L26

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 VDDR1_14 PCIE_VDDC_4
L20 M22 1 1 1 1 1 1 1
L21 VDDR1_15 PCIE_VDDC_5 N22
L22 VDDR1_16 PCIE_VDDC_6 N23
2 VDDR1_17 PCIE_VDDC_7

PX@
N24
PCIE_VDDC_8 2 2 2 2 2 2 2

PX@

PX@

PX@

PX@

PX@
R22

CD@

CD@
PCIE_VDDC_9 T22
LEVEL PCIE_VDDC_10 U22
TRANSLATION PCIE_VDDC_11 V22
AA20 PCIE_VDDC_12 +VGA_CORE
AA21 VDD_CT_1
AB20 VDD_CT_2 AA15
+3VGS AB21 VDD_CT_3 CORE VDDC_1 N15
(3.3V@25mA VDDR3) VDD_CT_4 VDDC_2 N17

CV9

CV73

CV74

CV75

CV76

CV77

CV78

CV79

CV80

CV81

CV82

CV83

CV84

CV85

CV86

CV87

CV100
2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
LV8 1 @ 2 0_0402_5% +VDDR3 VDDC_3 R13

33P_0402_50V8J
I/O VDDC_4 R16

CV93
VDDC_5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AA17 R18

1U_0402_6.3V6K
AA18 VDDR3_1 VDDC_6 Y21
1 VDDR3_2 VDDC_7
AB17 T12
VDDR3_3 VDDC_8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@
AB18 T15
VDDR3_4 VDDC_9

@
T17
2 VDDC_10

PX@
V12 T20
Y12 NC_VDDR4_1 VDDC_11 U13
+1.8VGS U12 NC_VDDR4_2 VDDC_12 U16
NC_VDDR4_3 VDDC_13 For RF
(1.8V@90mA MPLL_PVDD) U18
PX@ VDDC_14 V21
LV4 1 2 +MPLL_PVDD VDDC_15 V15
VDDC_16 V17
CV26

CV34

CV27

CV88

CV101

CV102

CV103

CV104

CV105
GBK160808T-221Y-N
VDDC_17 V20
CV24

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
VDDC_18

POWER
Y13
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

VDDC_19 1 1 1 1 1 1
Y16
.1U_0402_16V7K

1 1 1 VDDC_20
1 Y18
VDDC_21 AA12
VDDC_22 2 2 2 2 2 2

PX@

PX@

PX@

PX@

PX@

PX@
M11
For EMC 2 2 2 VDDC_23 N12
2 VDDC_24 U11
VDDC_25
PX@

PX@

PX@

C C
@

PLL
+0.95VGS

(0.95V@0.8A BIF_VDDC)
+1.8VGS R21
BIF_VDDC_1 U21
(1.8V@75mA SPLL_PVDD) BIF_VDDC_2
PX@ 1
LV5 1 2 +SPLL_PVDD +MPLL_PVDD L8 CV41
MPLL_PVDD
CV29

CV30

BLM15AG121SH1D_2P +VGA_CORE 1U_0402_6.3V6K


CV28

ISOLATED PX@
2
10U_0603_6.3V6M

1U_0402_6.3V6K

CORE I/O
M13
.1U_0402_16V7K

1 1 VDDCI_1
1 +SPLL_PVDD H7 M15
SPLL_PVDD VDDCI_2 M16
+0.95VGS VDDCI_3 M17

CV10

CV218

CV219

CV114

CV115

CV116

CV117
For EMC 2 2 VDDCI_4 M18

CV220
(0.95V@100mA SPLL_VDDC)

33P_0402_50V8J

10U_0603_6.3V6M

10U_0603_6.3V6M
.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
2 PX@ VDDCI_5 M20
VDDCI_6 1 1 1 1 1 1 1 1
PX@

PX@

LV6 1 2 +SPLL_VDDC H8 M21


SPLL_VDDC VDDCI_7 N20
CV35

CV36

BLM15AG121SH1D_2P
VDDCI_8
@

J7
CV33

SPLL_PVSS 2 2 2 2 2 2 2 2

PX@

PX@

PX@

PX@

PX@

PX@

PX@
1U_0402_6.3V6K

.1U_0402_16V7K

@
.1U_0402_16V7K

1 1
1
JET-S3-LE_FCBGA631
For EMC @
2 2
2
For RF
PX@

PX@
@

+1.05VS +0.95VGS
Reserve for GPU support +1.05V
AON6414AL_DFN8-5

1
2
5 3

B B
QV16 @

4
+20VSB
Can change to low cost
1 @ 2 RV120
100K_0402_5%
and small size MOS.

1
1

1
D RV119 CV221
PXS_PWREN# 2 QV15 120K_0402_5% 0.1U_0402_16V4Z
G @ @
2

2
@ S

3
2N7002KW_SOT323-3

+3.3VS TO +3VGS +1.35V TO +1.35VGS


+3VS
Need OPEN +3VGS +1.35V +1.35VGS
Need OPEN
JV1 1 2 @ JV2 1 2 @
1 2 1 2 CV214 CV210 CV211 CV212
JUMP_43X39 CV118 CV119 CV208 CV209 JUMP_43X118
1U_0402_10V6K
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

.1U_0402_16V7K
330U_D2_2V_Y
1
1

1
1 1 1 1 AON6414AL_DFN8-5 1 1 1
RV51 + RV91
470_0603_5% 1 470_0603_5%
QV6 3
S

1 PX@ @ 2 @
2 2 2 2 @ 2 2 2 2
PX@

PX@

PX@

PX@

PX@

PX@
@
LP2301ALT1G_SOT23-3 5 3
2

1 2
D QV10
G
2

+5VALW D QV7 QV9 PX@ 2 PXS_PWREN#


4

2 +20VSB G
PXS_PWREN# 46
1 PX@ 2 RV52 PXS_PWREN# 1 PX@ 2 RV53 G
20K_0402_5% 20K_0402_5% 1 PX@ 2 RV92 S 2N7002KW_SOT323-3

3
1 S 2N7002KW_SOT323-3 499K_0402_1% @
3

CV120 @
1

D 0.1U_0402_16V4Z 1
1

A PXS_PWREN 2 QV8 PX@ D RV118 CV213 A


4,57,58 PXS_PWREN 2
G PXS_PWREN# 2 QV11 499K_0402_1% 0.1U_0402_16V4Z
G PX@ PX@
PX@ S 2
3

2N7002KW_SOT323-3 PX@ S
3

2N7002KW_SOT323-3

Security Classification
Classification LC Future Center Secret Data Title
Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 23 of 59
5 4 3 2 1
5 4 3 2 1

UV1C
DQA0_[31..0]
DQA0_[31..0] 25,26 GDDR5/DDR3 GDDR5/DDR3
DQA1_[31..0] DQA0_0 K27 K17 MAA0
DQA1_[31..0] 25,26 J29 DQA0_0 MAA0_0/MAA_0 J20
DQA0_1 MAA1
DQA0_2 H30 DQA0_1 MAA0_1/MAA_1 H23 MAA2
MAA[15..0] DQA0_3 H32 DQA0_2 MAA0_2/MAA_2 G23 MAA3
MAA[15..0] 25,26 G29 DQA0_3 MAA0_3/MAA_3 G24
DQA0_4 MAA4
A_BA[2..0] DQA0_5 F28 DQA0_4 MAA0_4/MAA_4 H24 MAA5
A_BA[2..0] 25,26 DQA0_5 MAA0_5/MAA_5
D DQA0_6 F32 J19 MAA6 D
DQA0_7 F30 DQA0_6 MAA0_6/MAA_6 K19 MAA7
DQA0_8 C30 DQA0_7 MAA0_7/MAA_7 G20 MAA13
DQA0_9 F27 DQA0_8 MAA0_8/MAA_13 L17 MAA15
DQA0_10 A28 DQA0_9 MAA0_9/MAA_15
DQA0_11 C28 DQA0_10 J14 MAA8
DQA0_12 E27 DQA0_11 MAA1_0/MAA_8 K14 MAA9
DQA0_13 G26 DQA0_12 MAA1_1/MAA_9 J11 MAA10
DQA0_14 D26 DQA0_13 MAA1_2/MAA_10 J13 MAA11
DQA0_15 F25 DQA0_14 MAA1_3/MAA_11 H11 MAA12
DQA0_16 A25 DQA0_15 MAA1_4/MAA_12 G11 A_BA2
DQA0_17 C25 DQA0_16 MAA1_5/MAA_BA2 J16 A_BA0
DQA0_18 E25 DQA0_17 MAA1_6/MAA_BA0 L15 A_BA1
DQA0_19 D24 DQA0_18 MAA1_7/MAA_BA1 G14 MAA14
DQA0_20 E23 DQA0_19 MAA1_8/MAA_14 L16

MEMORY INTERFACE
DQA0_21 F23 DQA0_20 MAA1_9/RSVD
D22 DQA0_21 E32 DQMA#[7..0] 25,26
DQA0_22 DQMA#0
DQA0_23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 DQMA#1
DQA0_24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 DQMA#2
DQA0_25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 DQMA#3 +1.35VGS
DQA0_26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 DQMA#4
DQA0_27 A19 DQA0_26 WCKA1_0/DQMA1_0 D12 DQMA#5
DQA0_28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 DQMA#6 RV136 1 PX@ 2 100_0402_1% MAA0 100_0402_1% 1 PX@ 2 RV137
DQA0_29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 DQMA#7 RV138 1 PX@ 2 100_0402_1% MAA1 100_0402_1% 1 PX@ 2 RV139
DQA0_30 A17 DQA0_29 WCKA1B_1/DQMA1_3 RV140 1 PX@ 2 100_0402_1% MAA2 100_0402_1% 1 PX@ 2 RV141
C17 DQA0_30 H28 QSA[7..0] 25,26 1 2 1 2
DQA0_31 QSA0 RV142 PX@ 100_0402_1% MAA3 100_0402_1% PX@ RV143
DQA1_0 E17 DQA0_31 EDCA0_0/QSA0_0 C27 QSA1 RV144 1 PX@ 2 100_0402_1% MAA4 100_0402_1% 1 PX@ 2 RV145
DQA1_1 D16 DQA1_0 EDCA0_1/QSA0_1 A23 QSA2 RV146 1 PX@ 2 100_0402_1% MAA5 100_0402_1% 1 PX@ 2 RV147
C DQA1_1 EDCA0_2/QSA0_2 C
+1.35VGS DQA1_2 F15 E19 QSA3 RV148 1 PX@ 2 100_0402_1% MAA6 100_0402_1% 1 PX@ 2 RV149
DQA1_3 A15 DQA1_2 EDCA0_3/QSA0_3 E15 QSA4 RV150 1 PX@ 2 100_0402_1% MAA7 100_0402_1% 1 PX@ 2 RV151
DQA1_4 D14 DQA1_3 EDCA1_0/QSA1_0 D10 QSA5 RV152 1 PX@ 2 100_0402_1% MAA8 100_0402_1% 1 PX@ 2 RV153
DQA1_4 EDCA1_1/QSA1_1
1

DQA1_5 F13 D6 QSA6 RV154 1 PX@ 2 100_0402_1% MAA9 100_0402_1% 1 PX@ 2 RV155
RV61 DQA1_6 A13 DQA1_5 EDCA1_2/QSA1_2 G5 QSA7 RV156 1 PX@ 2 100_0402_1% MAA10 100_0402_1% 1 PX@ 2 RV157
40.2_0402_1% DQA1_7 C13 DQA1_6 EDCA1_3/QSA1_3 RV158 1 PX@ 2 100_0402_1% MAA11 100_0402_1% 1 PX@ 2 RV159
E11 DQA1_7 H27 QSA#[7..0] 25,26 1 2 1 2
PX@ DQA1_8 QSA#0 RV160 PX@ 100_0402_1% MAA12 100_0402_1% PX@ RV161
DQA1_9 A11 DQA1_8 DDBIA0_0/QSA0_0B A27 QSA#1 RV162 1 PX@ 2 100_0402_1% MAA13 100_0402_1% 1 PX@ 2 RV163
2

+VDD_MEM15_REFDA DQA1_10 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 QSA#2 RV164 1 PX@ 2 100_0402_1% MAA14 100_0402_1% 1 PX@ 2 RV165
DQA1_11 F11 DQA1_10 DDBIA0_2/QSA0_2B C19 QSA#3 RV166 1 PX@ 2 100_0402_1% MAA15 100_0402_1% 1 PX@ 2 RV167
DQA1_11 DDBIA0_3/QSA0_3B
1

1 DQA1_12 A9 C15 QSA#4


RV65 CV124 DQA1_13 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 QSA#5
100_0402_1% 1U_0402_6.3V6K DQA1_14 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 QSA#6 RV168 1 PX@ 2 100_0402_1% A_BA0 100_0402_1% 1 PX@ 2 RV169
PX@ PX@ DQA1_15 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 QSA#7 RV170 1 PX@ 2 100_0402_1% A_BA1 100_0402_1% 1 PX@ 2 RV171
2 DQA1_16 E7 DQA1_15 DDBIA1_3/QSA1_3B RV172 1 PX@ 2 100_0402_1% A_BA2 100_0402_1% 1 PX@ 2 RV173
2

DQA1_17 A7 DQA1_16 L18 ODTA0


C7 DQA1_17 ADBIA0/ODTA0 K16 ODTA0 25,26
DQA1_18 ODTA1
F7 DQA1_18 ADBIA1/ODTA1 ODTA1 25,26 1
DQA1_19 RV174 PX@ 2 100_0201_1% ODTA0 100_0201_1% 1 PX@ 2 RV175
DQA1_20 A5 DQA1_19 H26 CLKA0 RV176 1 PX@ 2 100_0201_1% ODTA1 100_0201_1% 1 PX@ 2 RV177
E5 DQA1_20 CLKA0 H25 CLKA0 25,26
DQA1_21 CLKA0#
C3 DQA1_21 CLKA0B CLKA0# 25,26
DQA1_22
DQA1_23 E1 DQA1_22 G9 CLKA1 RV178 1 PX@ 2 100_0201_1% RASA0# 100_0201_1% 1 PX@ 2 RV179
G7 DQA1_23 CLKA1 H9 CLKA1 25,26 1
DQA1_24 CLKA1# RV180 PX@ 2 100_0201_1% RASA1# 100_0201_1% 1 PX@ 2 RV181
G6 DQA1_24 CLKA1B CLKA1# 25,26
+1.35VGS DQA1_25
DQA1_26 G1 DQA1_25 G22 RASA0#
G3 DQA1_26 RASA0B G17 RASA0# 25,26 1
DQA1_27 RASA1# RV182 PX@ 2 100_0201_1% CASA0# 100_0201_1% 1 PX@ 2 RV183
DQA1_27 RASA1B RASA1# 25,26
1

B DQA1_28 J6 RV184 1 PX@ 2 100_0201_1% CASA1# 100_0201_1% 1 PX@ 2 RV185 B


RV62 DQA1_29 J1 DQA1_28 G19 CASA0#
DQA1_29 CASA0B CASA0# 25,26
40.2_0402_1% DQA1_30 J3 G16 CASA1#
DQA1_31 J5 DQA1_30 CASA1B CASA1# 25,26 1 RANKA@2 100_0201_1% CSA0#_0 1 RANKA@2 RV187
PX@ RV186 100_0201_1%
DQA1_31 H22 CSA0#_0 RV190 1 RANKA@2 100_0201_1% CSA1#_0 100_0201_1% 1 RANKA@2 RV191
2

K26 CSA0B_0 J22 CSA0#_0 25


+VDD_MEM15_REFSA +VDD_MEM15_REFDA CSA0#_1
MVREFDA CSA0B_1 CSA0#_1 26
+VDD_MEM15_REFSA J26
MVREFSA
1

1 G13 CSA1#_0 RV188 1 RANKB@2 100_0201_1% CSA0#_1 100_0201_1% 1 RANKB@2 RV189


J25 CSA1B_0 K13 CSA1#_0 25 1 RANKB@2 100_0201_1% 1 RANKB@2 RV193
RV66 CV125 CSA1#_1 RV192 CSA1#_1 100_0201_1%
NC#J25 CSA1B_1 CSA1#_1 26
100_0402_1% 1U_0402_6.3V6K RV55 1 2 PX@ K25
PX@ PX@ 120_0402_1% MEM_CALRP0 K20 CKEA0
2 CKEA0 CKEA0 25,26
J17 CKEA1 RV194 1 PX@ 2 100_0201_1% CKEA0 100_0201_1% 1 PX@ 2 RV195
CKEA1 25,26
2

CKEA1 RV196 1 PX@ 2 100_0201_1% CKEA1 100_0201_1% 1 PX@ 2 RV197


G25 WEA0#
WEA0B WEA0# 25,26
DRAMRST L10 H10 WEA1#
DRAM_RST WEA1B WEA1# 25,26 1
RV198 PX@ 2 100_0201_1% WEA0# 100_0201_1% 1 PX@ 2 RV199
PAD @ TV8 1 CLKTESTA K8 RV200 1 PX@ 2 100_0201_1% WEA1# 100_0201_1% 1 PX@ 2 RV201
PAD @ TV9 1 CLKTESTB L7 CLKTESTA
CLKTESTB

JET-S3-LE_FCBGA631
@

DRAMRST RV56 1 PX@ 2 RV57 1 2 PX@


DRAM_RST# 25,26
10_0402_5% 51.1_0402_1%
1

RV58 1
A 4.99K_0402_1% CV121 A
PX@ 120P_0402_50V8-J
PX@
2

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_MEM IF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 24 of 59
5 4 3 2 1
5 4 3 2 1

UV3 UV4 UV5 UV6

VREFCA_UV3 M8 E3 DQA0_19 VREFCA_UV4 M8 E3 DQA0_14 VREFCA_UV5 M8 E3 DQA1_9 VREFCA_UV6 M8 E3 DQA1_26


VREFDQ_UV3 H1 VREFCA DQL0 F7 DQA0_21 VREFDQ_UV4 H1 VREFCA DQL0 F7 DQA0_9 VREFDQ_UV5 H1 VREFCA DQL0 F7 DQA1_14 VREFDQ_UV6 H1 VREFCA DQL0 F7 DQA1_31
VREFDQ DQL1 F2 DQA0_18 VREFDQ DQL1 F2 DQA0_15 VREFDQ DQL1 F2 DQA1_11 VREFDQ DQL1 F2 DQA1_27
MAA0 N3 DQL2 F8 DQA0_22 MAA0 N3 DQL2 F8 DQA0_10 MAA0 N3 DQL2 F8 DQA1_12 MAA0 N3 DQL2 F8 DQA1_29
DQA0_[31..0] MAA1 P7 A0 DQL3 H3 DQA0_17 MAA1 P7 A0 DQL3 H3 DQA0_12 MAA1 P7 A0 DQL3 H3 DQA1_8 MAA1 P7 A0 DQL3 H3 DQA1_25
24,26 DQA0_[31..0] A1 DQL4 Group2 A1 DQL4 Group1 A1 DQL4 Group5 A1 DQL4 Group7
MAA2 P3 H8 DQA0_23 MAA2 P3 H8 DQA0_11 MAA2 P3 H8 DQA1_13 MAA2 P3 H8 DQA1_30
DQA1_[31..0] MAA3 N2 A2 DQL5 G2 DQA0_16 MAA3 N2 A2 DQL5 G2 DQA0_13 MAA3 N2 A2 DQL5 G2 DQA1_10 MAA3 N2 A2 DQL5 G2 DQA1_24
24,26 DQA1_[31..0] P8 A3 DQL6 H7 P8 A3 DQL6 H7 P8 A3 DQL6 H7 P8 A3 DQL6 H7
MAA4 DQA0_20 MAA4 DQA0_8 MAA4 DQA1_15 MAA4 DQA1_28
MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7
MAA[15..0] MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5
24,26 MAA[15..0] R2 A6 D7 R2 A6 D7 R2 A6 D7 R2 A6 D7
MAA7 DQA0_4 MAA7 DQA0_26 MAA7 DQA1_7 MAA7 DQA1_23
QSA[7..0] MAA8 T8 A7 DQU0 C3 DQA0_2 MAA8 T8 A7 DQU0 C3 DQA0_28 MAA8 T8 A7 DQU0 C3 DQA1_3 MAA8 T8 A7 DQU0 C3 DQA1_20
24,26 QSA[7..0] R3 A8 DQU1 C8 R3 A8 DQU1 C8 R3 A8 DQU1 C8 R3 A8 DQU1 C8
D MAA9 DQA0_7 MAA9 DQA0_27 MAA9 DQA1_6 MAA9 DQA1_19 D
QSA#[7..0] MAA10 L7 A9 DQU2 C2 DQA0_0 MAA10 L7 A9 DQU2 C2 DQA0_31 MAA10 L7 A9 DQU2 C2 DQA1_0 MAA10 L7 A9 DQU2 C2 DQA1_18
24,26 QSA#[7..0] R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7
MAA11 DQA0_5 Group0 MAA11 DQA0_25 Group3 MAA11 DQA1_5 Group4 MAA11 DQA1_21 Group6
DQMA#[7..0] MAA12 N7 A11 DQU4 A2 DQA0_1 MAA12 N7 A11 DQU4 A2 DQA0_29 MAA12 N7 A11 DQU4 A2 DQA1_1 MAA12 N7 A11 DQU4 A2 DQA1_17
24,26 DQMA#[7..0] T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8
MAA13 DQA0_6 MAA13 DQA0_24 MAA13 DQA1_4 MAA13 DQA1_22
A13 DQU6 A3 DQA0_3 A13 DQU6 A3 DQA0_30 A13 DQU6 A3 DQA1_2 A13 DQU6 A3 DQA1_16
DQU7 DQU7 DQU7 DQU7
+1.35VGS +1.35VGS +1.35VGS +1.35VGS

M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2


24,26 A_BA0 N8 BA0 VDD_1 D9 N8 BA0 VDD_1 D9 N8 BA0 VDD_1 D9 N8 BA0 VDD_1 D9
A_BA1 A_BA1 A_BA1
24,26 A_BA1 M3 BA1 VDD_2 G7 M3 BA1 VDD_2 G7 M3 BA1 VDD_2 G7 M3 BA1 VDD_2 G7
A_BA2 A_BA2 A_BA2
24,26 A_BA2 BA2 VDD_3 K2 BA2 VDD_3 K2 BA2 VDD_3 K2 BA2 VDD_3 K2
VDD_4 K8 VDD_4 K8 VDD_4 K8 VDD_4 K8
VDD_5 N1 VDD_5 N1 VDD_5 N1 VDD_5 N1
J7 VDD_6 N9 CLKA0 J7 VDD_6 N9 J7 VDD_6 N9 CLKA1 J7 VDD_6 N9
24,26 CLKA0 K7 CK VDD_7 R1 K7 CK VDD_7 R1 24,26 CLKA1 K7 CK VDD_7 R1 K7 CK VDD_7 R1
CLKA0# CLKA1#
24,26 CLKA0# K9 CK VDD_8 R9 K9 CK VDD_8 R9 24,26 CLKA1# K9 CK VDD_8 R9 K9 CK VDD_8 R9
CKEA0 CKEA1
24,26 CKEA0 CKE VDD_9 CKE VDD_9 24,26 CKEA1 CKE VDD_9 CKE VDD_9
+1.35VGS +1.35VGS +1.35VGS +1.35VGS

K1 A1 ODTA0 K1 A1 K1 A1 ODTA1 K1 A1
24,26 ODTA0 L2 ODT VDDQ_1 A8 L2 ODT VDDQ_1 A8 24,26 ODTA1 L2 ODT VDDQ_1 A8 L2 ODT VDDQ_1 A8
CSA0#_0 CSA1#_0
24 CSA0#_0 J3 CS VDDQ_2 C1 J3 CS VDDQ_2 C1 24 CSA1#_0 J3 CS VDDQ_2 C1 J3 CS VDDQ_2 C1
RASA0# RASA1#
24,26 RASA0# K3 RAS VDDQ_3 C9 K3 RAS VDDQ_3 C9 24,26 RASA1# K3 RAS VDDQ_3 C9 K3 RAS VDDQ_3 C9
CASA0# CASA1#
24,26 CASA0# L3 CAS VDDQ_4 D2 L3 CAS VDDQ_4 D2 24,26 CASA1# L3 CAS VDDQ_4 D2 L3 CAS VDDQ_4 D2
WEA0# WEA1#
24,26 WEA0# WE VDDQ_5 E9 WE VDDQ_5 E9 24,26 WEA1# WE VDDQ_5 E9 WE VDDQ_5 E9
VDDQ_6 F1 VDDQ_6 F1 VDDQ_6 F1 VDDQ_6 F1
QSA2 F3 VDDQ_7 H2 QSA1 F3 VDDQ_7 H2 QSA5 F3 VDDQ_7 H2 QSA7 F3 VDDQ_7 H2
QSA0 C7 DQSL VDDQ_8 H9 QSA3 C7 DQSL VDDQ_8 H9 QSA4 C7 DQSL VDDQ_8 H9 QSA6 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9 DQSU VDDQ_9 DQSU VDDQ_9 DQSU VDDQ_9

DQMA#2 E7 A9 DQMA#1 E7 A9 DQMA#5 E7 A9 DQMA#7 E7 A9


DQMA#0 D3 DML VSS_1 B3 DQMA#3 D3 DML VSS_1 B3 DQMA#4 D3 DML VSS_1 B3 DQMA#6 D3 DML VSS_1 B3
DMU VSS_2 E1 DMU VSS_2 E1 DMU VSS_2 E1 DMU VSS_2 E1
VSS_3 G8 VSS_3 G8 VSS_3 G8 VSS_3 G8
QSA#2 G3 VSS_4 J2 QSA#1 G3 VSS_4 J2 QSA#5 G3 VSS_4 J2 QSA#7 G3 VSS_4 J2
QSA#0 B7 DQSL VSS_5 J8 QSA#3 B7 DQSL VSS_5 J8 QSA#4 B7 DQSL VSS_5 J8 QSA#6 B7 DQSL VSS_5 J8
DQSU VSS_6 M1 DQSU VSS_6 M1 DQSU VSS_6 M1 DQSU VSS_6 M1
C VSS_7 VSS_7 VSS_7 VSS_7 C
M9 M9 M9 M9
VSS_8 P1 VSS_8 P1 VSS_8 P1 VSS_8 P1
T2 VSS_9 P9 DRAM_RST# T2 VSS_9 P9 DRAM_RST# T2 VSS_9 P9 DRAM_RST# T2 VSS_9 P9
24,26 DRAM_RST# RESET VSS_10 T1 RESET VSS_10 T1 RESET VSS_10 T1 RESET VSS_10 T1
L8 VSS_11 T9 L8 VSS_11 T9 L8 VSS_11 T9 L8 VSS_11 T9
ZQ VSS_12 ZQ VSS_12 ZQ VSS_12 ZQ VSS_12
1

1
J1 B1 J1 B1 J1 B1 J1 B1
RV67 L1 NC1 VSSQ_1 B9 RV68 L1 NC1 VSSQ_1 B9 RV69 L1 NC1 VSSQ_1 B9 RV70 L1 NC1 VSSQ_1 B9
243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1
RANKA@ L9 NC3 VSSQ_3 D8 RANKA@ L9 NC3 VSSQ_3 D8 RANKA@ L9 NC3 VSSQ_3 D8 RANKA@ L9 NC3 VSSQ_3 D8
MAA15 M7 NC4 VSSQ_4 E2 MAA15 M7 NC4 VSSQ_4 E2 MAA15 M7 NC4 VSSQ_4 E2 MAA15 M7 NC4 VSSQ_4 E2
2

2
MAA14 T7 NC5 VSSQ_5 E8 MAA14 T7 NC5 VSSQ_5 E8 MAA14 T7 NC5 VSSQ_5 E8 MAA14 T7 NC5 VSSQ_5 E8
NC6 VSSQ_6 F9 NC6 VSSQ_6 F9 NC6 VSSQ_6 F9 NC6 VSSQ_6 F9
VSSQ_7 G1 VSSQ_7 G1 VSSQ_7 G1 VSSQ_7 G1
VSSQ_8 G9 VSSQ_8 G9 VSSQ_8 G9 VSSQ_8 G9
VSSQ_9 VSSQ_9 VSSQ_9 VSSQ_9
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W2G1646E-BC1A_FBGA96 K4W2G1646E-BC1A_FBGA96 K4W2G1646E-BC1A_FBGA96 K4W2G1646E-BC1A_FBGA96
@ @ @ @

+1.35VGS +1.35VGS +1.35VGS +1.35VGS


1

+1.35VGS +1.35VGS
RV73 RV74 RV210 RV212
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
RANKA@ RANKA@ RANKA@ RANKA@

CV126

CV127

CV128

CV129

CV130

CV131

CV132

CV133

CV134

CV135

CV136

CV137

CV138

CV139

CV140

CV141

CV142
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
2

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VREFCA_UV3 VREFCA_UV4 VREFCA_UV5 VREFCA_UV6
B B
1

1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

RANKA@

RANKA@

RANKA@

RANKA@
CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@
RV77 CV144 RV78 CV145 RV211 CV224 RV213 CV225
4.99K_0402_1% 0.1U_0402_10V7K 4.99K_0402_1% 0.1U_0402_10V7K 4.99K_0402_1% 0.1U_0402_10V7K 4.99K_0402_1% 0.1U_0402_10V7K
RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@
2 2 2 2
2

+1.35VGS +1.35VGS
CV146

CV147

CV148

CV149

CV150

CV151

CV152

CV153

CV154

CV155

CV156

CV157

CV158

CV159

CV160

CV161

CV162

CV163

CV164

CV165
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1.35VGS +1.35VGS +1.35VGS +1.35VGS

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@

RANKA@
1

RV214 RV217 RV219 RV221


4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
RANKA@ RANKA@ RANKA@ RANKA@
2

VREFDQ_UV3 VREFDQ_UV4 VREFDQ_UV5 VREFDQ_UV6


ACLU1: (10U_0603_6.3V6M)*4 CRB: 10uF *4
1

1 1 1 1 (1U_0402_6.3V6K)*20 1uF *32


RV215 CV226 RV216 CV227 RV218 CV228 RV220 CV229 +1.35VGS
4.99K_0402_1% 0.1U_0402_10V7K 4.99K_0402_1% 0.1U_0402_10V7K 4.99K_0402_1% 0.1U_0402_10V7K 4.99K_0402_1% 0.1U_0402_10V7K (.1U_0402_10V6-K)*13 .1uF *32
RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@
2 2 2 2
2

CV11

CV12

CV13

CV14
33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

1 1 1 1

2 2 2 2
A A
@

CLKA0 RV71 1 2 RANKA@ CLKA1 RV75 1 2 RANKA@


40.2_0402_1% 40.2_0402_1%

CLKA0# RV72 1 2 RANKA@ CLKA1# RV76 1 2 RANKA@


40.2_0402_1% 40.2_0402_1% For RF
1 1
CV143 CV166
.01U_0402_16V7-K .01U_0402_16V7-K Title
RANKA@ RANKA@ Security Classification LC Future Center Secret Data
2 2
Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_VRAM_A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
For Single-Rank: RV71,RV72,RV75,RV76 use 40.2_0402_1% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 1.0
For Dual-Rank: RV71,RV72,RV75,RV76 use 80.6_0402_1% DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 25 of 59
5 4 3 2 1
5 4 3 2 1

UV7 UV8 UV9 UV10

VREFCA_UV7 M8 E3 DQA0_21 VREFCA_UV8 M8 E3 DQA0_9 VREFCA_UV9 M8 E3 DQA1_12 VREFCA_UV10 M8 E3 DQA1_31


VREFDQ_UV7 H1 VREFCA DQL0 F7 DQA0_19 VREFDQ_UV8 H1 VREFCA DQL0 F7 DQA0_14 VREFDQ_UV9 H1 VREFCA DQL0 F7 DQA1_9 VREFDQ_UV10 H1 VREFCA DQL0 F7 DQA1_26
VREFDQ DQL1 F2 DQA0_22 VREFDQ DQL1 F2 DQA0_10 VREFDQ DQL1 F2 DQA1_13 VREFDQ DQL1 F2 DQA1_29
MAA0 N3 DQL2 F8 DQA0_18 MAA0 N3 DQL2 F8 DQA0_15 MAA0 N3 DQL2 F8 DQA1_11 MAA0 N3 DQL2 F8 DQA1_27
DQA0_[31..0] MAA1 P7 A0 DQL3 H3 DQA0_20 MAA1 P7 A0 DQL3 H3 DQA0_11 MAA1 P7 A0 DQL3 H3 DQA1_15 MAA1 P7 A0 DQL3 H3 DQA1_28
24,25 DQA0_[31..0] A1 DQL4 Group2 A1 DQL4 Group1 A1 DQL4 Group5 A1 DQL4 Group7
MAA2 P3 H8 DQA0_16 MAA2 P3 H8 DQA0_12 MAA2 P3 H8 DQA1_10 MAA2 P3 H8 DQA1_24
DQA1_[31..0] MAA3 N2 A2 DQL5 G2 DQA0_23 MAA3 N2 A2 DQL5 G2 DQA0_8 MAA3 N2 A2 DQL5 G2 DQA1_14 MAA3 N2 A2 DQL5 G2 DQA1_30
24,25 DQA1_[31..0] P8 A3 DQL6 H7 P8 A3 DQL6 H7 P8 A3 DQL6 H7 P8 A3 DQL6 H7
MAA4 DQA0_17 MAA4 DQA0_13 MAA4 DQA1_8 MAA4 DQA1_25
MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7
MAA[15..0] MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5
24,25 MAA[15..0] R2 A6 D7 R2 A6 D7 R2 A6 D7 R2 A6 D7
MAA7 DQA0_2 MAA7 DQA0_28 MAA7 DQA1_3 MAA7 DQA1_20
QSA[7..0] MAA8 T8 A7 DQU0 C3 DQA0_4 MAA8 T8 A7 DQU0 C3 DQA0_26 MAA8 T8 A7 DQU0 C3 DQA1_5 MAA8 T8 A7 DQU0 C3 DQA1_23
24,25 QSA[7..0] R3 A8 DQU1 C8 R3 A8 DQU1 C8 R3 A8 DQU1 C8 R3 A8 DQU1 C8
D MAA9 DQA0_0 MAA9 DQA0_31 MAA9 DQA1_0 MAA9 DQA1_18 D
QSA#[7..0] MAA10 L7 A9 DQU2 C2 DQA0_7 MAA10 L7 A9 DQU2 C2 DQA0_27 MAA10 L7 A9 DQU2 C2 DQA1_7 MAA10 L7 A9 DQU2 C2 DQA1_19
24,25 QSA#[7..0] R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7
MAA11 DQA0_3 Group0 MAA11 DQA0_30 Group3 MAA11 DQA1_2 Group4 MAA11 DQA1_16 Group6
DQMA#[7..0] MAA12 N7 A11 DQU4 A2 DQA0_6 MAA12 N7 A11 DQU4 A2 DQA0_24 MAA12 N7 A11 DQU4 A2 DQA1_6 MAA12 N7 A11 DQU4 A2 DQA1_22
24,25 DQMA#[7..0] T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8 T3 A12/BC DQU5 B8
MAA13 DQA0_1 MAA13 DQA0_29 MAA13 DQA1_1 MAA13 DQA1_17
A13 DQU6 A3 DQA0_5 A13 DQU6 A3 DQA0_25 A13 DQU6 A3 DQA1_4 A13 DQU6 A3 DQA1_21
DQU7 DQU7 DQU7 DQU7
+1.35VGS +1.35VGS +1.35VGS +1.35VGS

M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2


24,25 A_BA0 N8 BA0 VDD_1 D9 N8 BA0 VDD_1 D9 N8 BA0 VDD_1 D9 N8 BA0 VDD_1 D9
A_BA1 A_BA1 A_BA1
24,25 A_BA1 M3 BA1 VDD_2 G7 M3 BA1 VDD_2 G7 M3 BA1 VDD_2 G7 M3 BA1 VDD_2 G7
A_BA2 A_BA2 A_BA2
24,25 A_BA2 BA2 VDD_3 K2 BA2 VDD_3 K2 BA2 VDD_3 K2 BA2 VDD_3 K2
VDD_4 K8 VDD_4 K8 VDD_4 K8 VDD_4 K8
VDD_5 N1 VDD_5 N1 VDD_5 N1 VDD_5 N1
J7 VDD_6 N9 CLKA0 J7 VDD_6 N9 J7 VDD_6 N9 CLKA1 J7 VDD_6 N9
24,25 CLKA0 K7 CK VDD_7 R1 K7 CK VDD_7 R1 24,25 CLKA1 K7 CK VDD_7 R1 K7 CK VDD_7 R1
CLKA0# CLKA1#
24,25 CLKA0# K9 CK VDD_8 R9 K9 CK VDD_8 R9 24,25 CLKA1# K9 CK VDD_8 R9 K9 CK VDD_8 R9
CKEA0 CKEA1
24,25 CKEA0 CKE VDD_9 CKE VDD_9 24,25 CKEA1 CKE VDD_9 CKE VDD_9
+1.35VGS +1.35VGS +1.35VGS +1.35VGS

K1 A1 ODTA0 K1 A1 K1 A1 ODTA1 K1 A1
24,25 ODTA0 L2 ODT VDDQ_1 A8 L2 ODT VDDQ_1 A8 24,25 ODTA1 L2 ODT VDDQ_1 A8 L2 ODT VDDQ_1 A8
CSA0#_1 CSA1#_1
24 CSA0#_1 J3 CS VDDQ_2 C1 J3 CS VDDQ_2 C1 24 CSA1#_1 J3 CS VDDQ_2 C1 J3 CS VDDQ_2 C1
RASA0# RASA1#
24,25 RASA0# K3 RAS VDDQ_3 C9 K3 RAS VDDQ_3 C9 24,25 RASA1# K3 RAS VDDQ_3 C9 K3 RAS VDDQ_3 C9
CASA0# CASA1#
24,25 CASA0# L3 CAS VDDQ_4 D2 L3 CAS VDDQ_4 D2 24,25 CASA1# L3 CAS VDDQ_4 D2 L3 CAS VDDQ_4 D2
WEA0# WEA1#
24,25 WEA0# WE VDDQ_5 E9 WE VDDQ_5 E9 24,25 WEA1# WE VDDQ_5 E9 WE VDDQ_5 E9
VDDQ_6 F1 VDDQ_6 F1 VDDQ_6 F1 VDDQ_6 F1
QSA2 F3 VDDQ_7 H2 QSA1 F3 VDDQ_7 H2 QSA5 F3 VDDQ_7 H2 QSA7 F3 VDDQ_7 H2
QSA0 C7 DQSL VDDQ_8 H9 QSA3 C7 DQSL VDDQ_8 H9 QSA4 C7 DQSL VDDQ_8 H9 QSA6 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9 DQSU VDDQ_9 DQSU VDDQ_9 DQSU VDDQ_9

DQMA#2 E7 A9 DQMA#1 E7 A9 DQMA#5 E7 A9 DQMA#7 E7 A9


DQMA#0 D3 DML VSS_1 B3 DQMA#3 D3 DML VSS_1 B3 DQMA#4 D3 DML VSS_1 B3 DQMA#6 D3 DML VSS_1 B3
DMU VSS_2 E1 DMU VSS_2 E1 DMU VSS_2 E1 DMU VSS_2 E1
VSS_3 G8 VSS_3 G8 VSS_3 G8 VSS_3 G8
QSA#2 G3 VSS_4 J2 QSA#1 G3 VSS_4 J2 QSA#5 G3 VSS_4 J2 QSA#7 G3 VSS_4 J2
QSA#0 B7 DQSL VSS_5 J8 QSA#3 B7 DQSL VSS_5 J8 QSA#4 B7 DQSL VSS_5 J8 QSA#6 B7 DQSL VSS_5 J8
DQSU VSS_6 M1 DQSU VSS_6 M1 DQSU VSS_6 M1 DQSU VSS_6 M1
C VSS_7 VSS_7 VSS_7 VSS_7 C
M9 M9 M9 M9
VSS_8 P1 VSS_8 P1 VSS_8 P1 VSS_8 P1
T2 VSS_9 P9 DRAM_RST# T2 VSS_9 P9 DRAM_RST# T2 VSS_9 P9 DRAM_RST# T2 VSS_9 P9
24,25 DRAM_RST# RESET VSS_10 T1 RESET VSS_10 T1 RESET VSS_10 T1 RESET VSS_10 T1
L8 VSS_11 T9 L8 VSS_11 T9 L8 VSS_11 T9 L8 VSS_11 T9
ZQ VSS_12 ZQ VSS_12 ZQ VSS_12 ZQ VSS_12
1

1
J1 B1 J1 B1 J1 B1 J1 B1
RV79 L1 NC1 VSSQ_1 B9 RV80 L1 NC1 VSSQ_1 B9 RV81 L1 NC1 VSSQ_1 B9 RV82 L1 NC1 VSSQ_1 B9
243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1
RANKB@ L9 NC3 VSSQ_3 D8 RANKB@ L9 NC3 VSSQ_3 D8 RANKB@ L9 NC3 VSSQ_3 D8 RANKB@ L9 NC3 VSSQ_3 D8
MAA15 M7 NC4 VSSQ_4 E2 MAA15 M7 NC4 VSSQ_4 E2 MAA15 M7 NC4 VSSQ_4 E2 MAA15 M7 NC4 VSSQ_4 E2
2

2
MAA14 T7 NC5 VSSQ_5 E8 MAA14 T7 NC5 VSSQ_5 E8 MAA14 T7 NC5 VSSQ_5 E8 MAA14 T7 NC5 VSSQ_5 E8
NC6 VSSQ_6 F9 NC6 VSSQ_6 F9 NC6 VSSQ_6 F9 NC6 VSSQ_6 F9
VSSQ_7 G1 VSSQ_7 G1 VSSQ_7 G1 VSSQ_7 G1
VSSQ_8 G9 VSSQ_8 G9 VSSQ_8 G9 VSSQ_8 G9
VSSQ_9 VSSQ_9 VSSQ_9 VSSQ_9
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W2G1646E-BC1A_FBGA96 K4W2G1646E-BC1A_FBGA96 K4W2G1646E-BC1A_FBGA96 K4W2G1646E-BC1A_FBGA96
@ @ @ @

+1.35VGS +1.35VGS +1.35VGS +1.35VGS +1.35VGS +1.35VGS


1

CV167

CV168

CV169

CV170

CV171

CV172

CV173

CV174

CV175

CV176

CV177

CV178

CV179

CV180

CV181

CV182

CV184
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
RV85 RV86 RV223 RV225 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
RANKB@ RANKB@ RANKB@ RANKB@
2

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

RANKB@

RANKB@

RANKB@

RANKB@
CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@

CD@
B VREFCA_UV7 VREFCA_UV8 VREFCA_UV9 VREFCA_UV10 B
1

1 1 1 1
RV88 CV185 RV89 CV186 RV222 CV230 RV224 CV231
4.99K_0402_1% 0.1U_0402_10V7K 4.99K_0402_1% 0.1U_0402_10V7K 4.99K_0402_1% 0.1U_0402_10V7K 4.99K_0402_1% 0.1U_0402_10V7K
RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ +1.35VGS +1.35VGS
2 2 2 2
2

CV188

CV189

CV190

CV191

CV192

CV193

CV194

CV195

CV196

CV197

CV198

CV199

CV200

CV201

CV202

CV203

CV204

CV205

CV206

CV207
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@
+1.35VGS +1.35VGS +1.35VGS +1.35VGS
1

RV233 RV227 RV229 RV231


4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
RANKB@ RANKB@ RANKB@ RANKB@
ACLU1: (10U_0603_6.3V6M)*4 CRB: 10uF *4
2

VREFDQ_UV7 VREFDQ_UV8 VREFDQ_UV9 VREFDQ_UV10 +1.35VGS (1U_0402_6.3V6K)*20 1uF *32


(.1U_0402_10V6-K)*13 .1uF *32
1

1 1 1 1
RV232 CV235 RV226 CV232 RV228 CV233 RV230 CV234
CV17

CV20

CV23

CV22

4.99K_0402_1% 0.1U_0402_10V7K 4.99K_0402_1% 0.1U_0402_10V7K 4.99K_0402_1% 0.1U_0402_10V7K 4.99K_0402_1% 0.1U_0402_10V7K


RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@ RANKB@
33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

2 2 2 2
1 1 1 1
2

2 2 2 2
@

A A

CLKA0 RV83 1 2 RANKB@ CLKA1 RV87 1 2 RANKB@


80.6_0402_1% 80.6_0402_1% For RF
CLKA0# RV84 1 2 RANKB@ CLKA1# RV90 1 2 RANKB@
80.6_0402_1% 80.6_0402_1%
1 1
CV183 CV187
.01U_0402_16V7-K .01U_0402_16V7-K Title
RANKB@ RANKB@ Security Classification LC Future Center Secret Data
2 2
Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_VRAM_B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 26 of 59
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 27 of 59
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 28 of 59
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 29 of 59
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 30 of 59
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 31 of 59
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 32 of 59
5 4 3 2 1
5 4 3 2 1

LCD POWER CIRCUIT CMOS Camera


+LCDVDD +5VALW +3VS
W=60mils +3VS Need short +3VS_CMOS_R
J1 @

1
1 2
1 2

1
R1 1
130_0603_1% R2 C1 JUMP_43X39
100K_0402_5% 4.7U_0603_6.3V6K +3VS_CMOS
CD@

2
2 LP2301ALT1G_SOT23-3

2
Q9 W=40 mils @ W=40mils

3
S

D
D Q8B R4 G Q7 3 1 R3 1 2

.01U_0402_16V7-K
D 5 1 2 2 LP2301ALT1G_SOT23-3 0_0603_5% D

C6
G 220K_0402_5% @ 1 1
2N7002KDWH_SOT363-6 +LCDVDD +LCDVDD_CON C3 C4

G
D
1 1 1

2
S C5 .1U_0402_10V6-K 10U_0603_6.3V6M
L1

4
C2 W=60mils .1U_0402_10V6-K CD@ @
.1U_0402_10V6-K 1 2 @ 2 2
2 FCM2012CF-800T06_2P 2 @2

33P_0402_50V8J
.1U_0402_10V6-K
C7

C8

C43
4.7U_0603_6.3V6K
6
Q8A D 1 1 1 R5 1 @ 2
9 CMOS_ON#
R6 1 2 0_0402_5% 2 100K_0402_5%
4 PCH_ENVDD G
@ 1 1
C9 C10

1
S 2N7002KDWH_SOT363-6 2 2 2 0.01U_0402_25V7K .1U_0402_10V6-K
For EMI

@
R7 @ Close to R5 @
100K_0402_5% 2 2
CD@

2
+3VS
For RF
+3VS
EMI request

2
R8 R9
2

100K_0402_1% 100K_0402_1% DMIC_CLK DISPOFF# INVT_PWM

470P_0402_50V7K
R10

470P_0402_50V7K
100P_0402_50V8J
C11

C12

C13
PCH_ENBKL R11 1 @ 2 4.7K_0402_5% @ @

1
0_0402_5% @ 1 1 1
1

EDP_AUX
R12 1 2 0_0402_5% DISPOFF# B+ +LEDVDD EDP_AUX#
44 BKOFF# 2 2 2
@
2A 80 mil 0_0805_5% 2A 80 mil @ @

2
R14 1 2 0_0402_5% ENBKL R17 2 1 @
4 PCH_ENBKL ENBKL 44

4.7U_0805_25V6-K
@ C14 R13 R15
1

C C
1 1 100K_0402_1% 100K_0402_1%
R16
100K_0402_5% AO3401A_SOT23-3 C15 @ @

1
0.1U_0402_25V6
2 2

D
Q33 3 1 @
2

EMI Request JEDP1


+LEDVDD 1
CD@ 2 1

G
2
3 2
+3VS R179 1 @ 2 LEDVDD_EN# 4 3
B+ 4
100K_0402_5% CPU_EDP_TX0+ C19 1 2 .1U_0402_10V6-K EDP_TX0+ 5
4 CPU_EDP_TX0+ 5
CPU_EDP_TX0- C16 1 2 .1U_0402_10V6-K EDP_TX0- 6
4 CPU_EDP_TX0- 6
2

1
7
R18 R180 CPU_EDP_TX1+ C17 1 2 .1U_0402_10V6-K EDP_TX1+ 8 7
4 CPU_EDP_TX1+ 8
1K_0402_5% 100K_0402_5% CPU_EDP_TX1- C18 1 2 .1U_0402_10V6-K EDP_TX1- 9
4 CPU_EDP_TX1- 9
@ @ 10
CPU_EDP_AUX C20 1 2 .1U_0402_10V6-K EDP_AUX 11 10
4 CPU_EDP_AUX
1

1 2
CPU_EDP_AUX# C21 1 2 .1U_0402_10V6-K EDP_AUX# 12 11
4 CPU_EDP_AUX# 12
R19 1 2 0_0402_5% INVT_PWM Q34 D 13
4 PCH_EDP_PWM 13
@ PCH_ENVDD R181 1 @ 2 2 DISPOFF# 14
0_0402_5% G 15 14
15
1

1 INVT_PWM 16
4 INVT_PWM 16
R20 C132 @ S 17
3

100K_0402_5% .1U_0402_10V6-K 2N7002KW_SOT323-3 +3VS 18 17


@ 19 18
2 4 CPU_EDP_HPD 19
R21 1 @ 2 20
2

0_0402_5% 21 20
1 +LCDVDD_CON 21
W=60mils 22
C22 23 22
Reserve for power consumption test +3VS 23
680P_0402_50V7K 43 DMIC_DATA 24
@ 2 25 24
43 DMIC_CLK 25
26 31
27 26 G1 32
R182 1 @ 2 0_0402_5% USB20_P5_R 28 27 G2 33
9 USB20_P5 28 G3
B R183 1 2 0_0402_5% USB20_N5_R 29 34 B
9 USB20_N5 29 G4
+3VS_CMOS@ 30 35
30 G5
2
Touch Screen .1U_0402_10V6-K C24
W=40mils ACES_50406-03071-001
ME@
R22 1 TS@ 2 C23 1 2 TS@ 0.047U_0402_16V7K
44 EC_TS_ON# 1
100K_0402_5% CD@
+3VS_TS_R +3VS_TS

LP2301ALT1G_SOT23-3
EMI request
S

3 1
Q11 TS@ JTS1
1 1
C25 R28 2 @ 1 10K_0402_5% TS_RS 2 1
G
2

.1U_0402_10V6-K 3 2
@ R23 1 TS@ 2 0_0402_5% USB20_N4_CONN 4 3
2 9 USB20_N4 4
R24 1 TS@ 2 0_0402_5% USB20_P4_CONN 5 7
9 USB20_P4 5 GND1
6 8
6 GND2 For EMI
ACES_87213-00601-P01 L12 @
+3VS +3VS_TS_R +3VS_TS USB20_P4_CONN USB20_P5 1 2 USB20_P5_R
ME@ 1 2
R25 1 TS@ 2 0_0402_5% R26 1 @ 2 0_0402_5% +3VS_TS USB20_N4_CONN Touch Screen USB20_N5 4 3 USB20_N5_R
4 3
3

+3VALW
CMM21T-900M-N_4P
R27 1 @ 2 0_0402_5%
1

@
D2
1

For EMI
L13 @ D1
2

USB20_P4 1 2 USB20_P4_CONN AZC199-02S.R7G_SOT23-3


A 1 2 @ A
2

AZ5215-01F_DFN1006P2E2
USB20_N4 4 3 USB20_N4_CONN
1

4 3
CMM21T-900M-N_4P For EMI

Security Classification
Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 eDP/ CMOS/Touch screen


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Friday, December 20, 2013 Sheet 33 of 59
5 4 3 2 1
5 4 3 2 1

L2 @
HDMI_CLK-_C 1 2 HDMI_CLK-_CON 1 2
1 2 C26 3.3P_0402_50V8-C
@
HDMI_CLK+_C 4 3
HDMI_CLK+_CON 1 2
4 3 C27 3.3P_0402_50V8-C
HDMI2012F2SF-900T04_4P
+3VS
D L3 @ D
HDMI_TX0-_C 1 2 HDMI_TX0-_CON 1 2
1 2 C28 3.3P_0402_50V8-C
@
HDMI_TX0+_C 4 3
HDMI_TX0+_CON 1 2
4 3 C29 3.3P_0402_50V8-C

5
HDMI2012F2SF-900T04_4P

G
Q1B D3
L4 @ HDMI_DET 1 1 10 9 HDMI_DET
HDMI_TX1-_C 1 2 HDMI_TX1-_CON 1 2
1 2 4 3 2 2
C30 3.3P_0402_50V8-C HDMICLK_R HDMIDAT_R 9 8 HDMIDAT_R

S
4 DDPB_CLK

D
@
HDMI_TX1+_C 4 3
HDMI_TX1+_CON 1 2 2N7002KDWH_SOT363-6 HDMICLK_R 4 4 7 7 HDMICLK_R
4 3

2
C31 3.3P_0402_50V8-C

G
HDMI2012F2SF-900T04_4P Q1A +5VS_HDMI 5 5 6 6 +5VS_HDMI

L5 @ 3 3
HDMI_TX2-_C 1 2 HDMI_TX2-_CON 1 2 1 6 HDMIDAT_R

S
1 2 4 DDPB_DATA

D
C32 3.3P_0402_50V8-C 8
@ 2N7002KDWH_SOT363-6
HDMI_TX2+_C 4 3 HDMI_TX2+_CON 1 2
4 3 C33 3.3P_0402_50V8-C AZ1045-04F_DFN2510P10E-10-9
HDMI2012F2SF-900T04_4P @

For EMC
For EMC

C C
HDMI_CLK-_C R29 1 2 470_0402_5% +5VS +5VS_HDMI_F +5VS_HDMI
D5
HDMI_CLK+_C R30 1 2 470_0402_5% +5VS 2 F1
+3VS 1 1 2
HDMI_TX0-_C R31 1 2 470_0402_5% 3

2
D4 RB491D_SOT23-3 0.5A_8V_KMC3S050RY
HDMI_TX0+_C R32 1 2 470_0402_5%

HDMI_TX1-_C R33 1 2 470_0402_5% @ LP2301ALT1G_SOT23-3

2
HDMI_TX1+_C R34 1 2 470_0402_5% BAT54S-7-F_SOT23-3 1 3 Q22

S
R35

1
2
Q12 D4

G
1M_0402_5%
HDMI_TX2-_C R37 1 2 470_0402_5% @ 1
C34

G
1

2
HDMI_TX2+_C R38 1 2 470_0402_5% .1U_0402_10V6-K

2
3 1
4 HDMI_HPD 46 SUSP 2

D
R39 R40
1

D Q13 2N7002KW_SOT323-3 2.2K_0402_5% 2.2K_0402_5%

2
2
+3VS
G 2N7002KW_SOT323-3 R41

1
20K_0402_5%
S JHDMI1
3

HDMI_DET 19

1
R42 1 @ 2 18 HP_DET
17 +5V
100K_0402_5% HDMIDAT_R 16 DDC/CEC_GND
HDMICLK_R 15 SDA
14 SCL
13 Reserved
HDMI_CLK- C35 2 1 .1U_0402_10V6-K HDMI_CLK-_C R43 2 @ 1 0_0402_5% HDMI_CLK-_CON 12 CEC 20
4 HDMI_CLK- CK- GND1
11 21
B HDMI_CLK+ C36 2 1 .1U_0402_10V6-K HDMI_CLK+_C R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10 CK_shield GND2 B
4 HDMI_CLK+ CK+
HDMI_TX0- C37 2 1 .1U_0402_10V6-K HDMI_TX0-_C R45 2 @ 1 0_0402_5% HDMI_TX0-_CON 9 22
4 HDMI_TX0- D0- GND3
8 23
HDMI_TX0+ C38 2 1 .1U_0402_10V6-K HDMI_TX0+_C R46 2 @ 1 0_0402_5% HDMI_TX0+_CON 7 D0_shield GND4
4 HDMI_TX0+ D0+
HDMI_TX1- C39 2 1 .1U_0402_10V6-K HDMI_TX1-_C R47 2 @ 1 0_0402_5% HDMI_TX1-_CON 6
4 HDMI_TX1- D1-
5
HDMI_TX1+ C40 2 1 .1U_0402_10V6-K HDMI_TX1+_C R48 2 @ 1 0_0402_5% HDMI_TX1+_CON 4 D1_shield
4 HDMI_TX1+ D1+
HDMI_TX2- C41 2 1 .1U_0402_10V6-K HDMI_TX2-_C R49 2 @ 1 0_0402_5% HDMI_TX2-_CON 3
4 HDMI_TX2- D2-
2
HDMI_TX2+ C42 2 1 .1U_0402_10V6-K HDMI_TX2+_C R50 2 @ 1 0_0402_5% HDMI_TX2+_CON 1 D2_shield
4 HDMI_TX2+ D2+
FOX_QJ111A1-RC0AH1-8H
ME@

Close to JHDMI1
D6 D7
HDMI_CLK+_CON 1 1 10 9 HDMI_CLK+_CON HDMI_TX1-_CON 1 1 10 9 HDMI_TX1-_CON

HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON

HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON

HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON


A A
3 3 3 3

8 8

AZ1045-04F_DFN2510P10E-10-9 For EMC AZ1045-04F_DFN2510P10E-10-9


@ @ Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 HDMI_CONN


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Tuesday, December 24, 2013 Sheet 34 of 59
5 4 3 2 1
5 4 3 2 1

+1.35V Need open +1.35VS


+3VS +3VS_DVGA +3VS_DVGA +3VS_DVGA JVG1 @
1 2
1 2

4.7U_0603_6.3V6K
@
RVG1 1 2 0_0603_5% LVG1 1 2 VDD33 LVG2 1 2 VDDA33 LVG3 1 2 VDD33VGA JUMP_43X39 1 1
PBY160808T-331Y-N PBY160808T-331Y-N PBY160808T-331Y-N 1 CVG46 CVG47
1 1 1 1 1 1 CVG51 QVG1 4.7U_0603_6.3V6K .1U_0402_10V6-K
CVG1 CVG2 CVG3 CVG4 CVG5 CVG6 @ @
.47U_0402_6.3V6K 1U_0402_6.3V6K .47U_0402_6.3V6K 1U_0402_6.3V6K .47U_0402_6.3V6K 4.7U_0603_6.3V6K 8 1 2 2
@2 7 2
2 2 2 2 2 2 6 3
5

D @ AP4800BGM-HF_SO-8 D

4
RVG36 1 @ 2
46 5VS_GATE
1
10K_0402_5% CVG48
+5VALW .1U_0402_10V6-K
@
2
1
CVG7 +1.2VS
1U_0402_10V6K +1.2VS +1.35VS_DVGA
2
+1.5VS UVG1 RVG34 1 2 0_0603_5%

1
@ 6 +1.35VS_DVGA
VCNTL 1
RVG2 1 2 0_0603_5%
+1.5VS_VIN 5 3 RVG3 CVG8 +1.35VS
9 VIN1 VOUT1 4 10K_0402_1% 10U_0603_6.3V6M
1 VIN2 VOUT2 RVG35 1 @ 2 0_0603_5% LVG4 1 2 VDD12 LVG5 1 2 VDDRX
CVG9 EN 8 2 PBY160808T-331Y-N PBY160808T-331Y-N

2
4.7U_0603_6.3V6K POK 7 EN 2 FB 1 1 1 1

GND
2 POK FB CVG10 CVG11 CVG12 CVG13
RVG4

1
.47U_0402_6.3V6K 1U_0402_6.3V6K .47U_0402_6.3V6K 1U_0402_6.3V6K
1

1 2 APL5930KAI-TRG_SO8 RVG5

1
44,46,55,56,57,58 SUSP# 2 2 2 2
10K_0402_5% RVG6 20K_0402_1%
1 100K_0402_5%
@

2
CVG14
2

.1U_0402_10V6-K
2
VFB=0.8V +3VS
C Vo=VFB*(1+RVG3/RVG5) +3VS_DVGA C
+3VS_DVGA
OCP:Min 4A
CSDA RVG7 1 2 4.7K_0402_5% CFG RVG9 1 @ 2 4.7K_0402_5%

CSCL RVG8 1 2 4.7K_0402_5%


CVG151 2 .1U_0402_10V6-K DRX0N Initial code loading selection, internal pull down ~80kΩ:
4 VGA_TX0-
CVG161 2 .1U_0402_10V6-K DRX0P
4 VGA_TX0+
CVG171 2 .1U_0402_10V6-K DRX1N
L: Loading initial code from internal MTP ROM
4 VGA_TX1- H: No initial code loading, external I2C control is expected
CVG181 2 .1U_0402_10V6-K DRX1P
4 VGA_TX1+
CVG191 2 .1U_0402_10V6-K AUXN
4 VGA_AUX#
CVG201 2 .1U_0402_10V6-K AUXP UVG2
4 VGA_AUX
VGA_SDA 1 40 VGA_SCL
RVG111 2 1K_0402_5% DP_HPD 6.65K_0402_1% 1 2 RVG12 RVGA 2 VGA_SDA VGA_SCL 39 RED
4 VGA_HPD 1 2 RVG10 REXT 3 RVGA RED 38 +3VS_DVGA
4.99K_0402_1%
VDDA33 4 REXT GNDVGA3 37 GREEN
VDD33 5 VDDA33 GREEN 36
6 VDD33 GNDVGA2 35 VDD33VGA CVG21 1 2 .1U_0402_10V6-K
GND1 VDD33VGA

2
VDD12 7 34 BLUE
XTLO 8 VDD12_1 BLUE 33 RVG14
XTLO GNDVGA1
CVG22

CVG23

CVG24

CVG25

XTLI 9 32 VGA_HS 4.7K_0402_5%


+3VS_DVGA XTLI VGA_HS VGA_HS 36
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.01U_0402_16V7-K

AUXN 10 31 VGA_VS
AUXN VGA_VS VGA_VS 36 @
1 1 1 1 AUXP 11 30 GPIO1

1
DP_HPD 12 AUXP GPIO1 29 GPIO1 36
VDDRX 13 DP_HPD TESTMODE 28 CSDA GPIO3/TSCK_O
VDDRX CSDA
1

DRX0P 14 27 CSCL
2 2 2 2 DRX0p CSCL
CVG26

CVG27

RVG13 DRX0N 15 26 GPIO3/TSCK_O


DRX0n GPIO3/TSCK_O

2
.1U_0402_10V6-K

.01U_0402_16V7-K

10K_0402_5% 16 25 VDD12
DRX1P 17 GND2 VDD12_2 24 GPIO0 1 TVG1 PAD @ RVG15
1 1 DRX1p GPIO0

CVG28

CVG29
CD@ DRX1N 18 23 4.7K_0402_5%
2

B DRX1n GND3

.01U_0402_16V7-K
B

.1U_0402_10V6-K
RST# 19 22 GPIO2/INTRQ 1
RST# GPIO2/INTRQ @
RST# PD# PD# 20 21 CFG TVG2 PAD @ 1 1

1
2 2 PD# CFG
1 1 41
EPAD
CVG30 CVG31 2 2
.1U_0402_10V6-K 1U_0402_6.3V6K I2C address, 3-state inputs:
2 2 PS8613TQFN40GTR2-A1_TQFN40_5X5
CD@
L: 0x50h ~ 0x6Fh
M: 0x90h ~ 0xAFh
Update DP Convert Version from A0 to A1 H: 0x30h ~ 0x4Fh

RED RVG17 1 2 10_0402_5%


CRT_R 36
GREEN RVG18 1 2 10_0402_5%
CRT_G 36
RVG16 1 2 1M_0402_5% BLUE RVG20 1 2 10_0402_5%
CRT_B 36
VGA_SCL RVG23 1 @ 2 0_0402_5%
CRT_DDC_CLK 36
YVG1 VGA_SDA RVG24 1 @ 2 0_0402_5%
CRT_DDC_DAT 36
XTLI 1 4
OSC1 GND2
2 3 XTLO
GND1 OSC2

A 27MHZ_10PF_7V27000050 A
1 1
CVG32 CVG33
15P_0402_50V8J 12P_0402_50V8J
2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 DP to CRT Converter(PS8613)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 35 of 59
5 4 3 2 1
5 4 3 2 1

CRT Connector
+CRT_VCC_CON +5VS_HDMI

+5VS @
+CRT_VCC RVG39 1 2 0_0603_5%
DVG1
@ 2 FVG1
1 1 2 @ +CRT_VCC_CON
3 1
D PMEG2010ET_SOT23-3 0.5A_8V_KMC3S050RY D

1
CVG34
.1U_0402_10V6-K DVG2
W=40mils

1
2
AZ5425-01F_DFN1006P2E2
CD@
@

2
2
JCRT1
6
@ PAD TVG3 1 CRT_DET# 11
LVG6 1 2 CRT_R_CON 1
35 CRT_R 7
BLM18BA100SN1D For EMC
CRT_DDC_DAT 12
1 2 35 CRT_DDC_DAT CRT_G_CON 2
LVG7
35 CRT_G 8
BLM18BA100SN1D
HSYNC_CON 13
LVG8 1 2 CRT_B_CON 3
35 CRT_B 9
BLM18BA100SN1D

5P_0402_50V8-C

5P_0402_50V8-C

5P_0402_50V8-C

3.3P_0402_50V8-C

3.3P_0402_50V8-C

3.3P_0402_50V8-C
VSYNC_CON 14
1

1
1 1 1 1 1 1 4

CVG35

CVG36

CVG37

CVG38

CVG39

CVG40
RVG25 RVG26 RVG27 10 G 16
75_0402_1% 75_0402_1% 75_0402_1% CRT_DDC_CLK 15 G 17
35 CRT_DDC_CLK 5
2 2 2 2 2 2
1
2

CVG41 SUYIN_070546HR015M25KZR
+3VS_DVGA 100P_0402_50V8J ME@
@
2
CLOSE TO UVG1

1
RVG28
C 4.7K_0402_5% C

2
RVG29 1 @ 2
35 GPIO1
0_0402_5%

1
RVG42
0_0402_5%
@ +5VS
+5VS

2
2

CVG49 RVG37

2
RVG40 1 2 @ 1 @ 2
0_0402_5% 1K_0402_5% RVG41

2
@ .1U_0402_10V6-K 0_0402_5%
5

@ RVG30 RVG31
1

2.2K_0402_5% 2.2K_0402_5%
OE#
P

1
VGA_HS RVG43 1 2 0_0402_5% 2 4 CRT_HSYNC RVG44 1 2 0_0402_5% RVG32 1 2 33_0402_5% CRT_HSYNC_R LVG9 1 2 HSYNC_CON
35 VGA_HS A Y BLM18BA100SN1D

1
G

@ UVG3 @
74AHCT1G125GW_SOT353-5 1
3

@ CRT_DDC_CLK
CVG42
15P_0402_50V8-J CRT_DDC_DAT
2

1 1
CVG43 CVG44
100P_0402_50V8J 68P_0402_50V8J
B @ 2 2 @ B
+5VS
2

CVG50 RVG38
2

1 2 @ 1 @ 2 RVG46
RVG47 1K_0402_5% 0_0402_5%
0_0402_5% .1U_0402_10V6-K @
5

@
1
OE#
P
1

VGA_VS RVG45 1 2 0_0402_5% 2 4 CRT_VSYNC RVG48 1 2 0_0402_5% RVG33 1 2 33_0402_5% CRT_VSYNC_R LVG10 1 2 VSYNC_CON
35 VGA_VS A Y BLM18BA100SN1D
G

@ UVG4 @ 1
74AHCT1G125GW_SOT353-5
3

@ CVG45
15P_0402_50V8-J
2

DVG3 DVG4
CRT_B_CON 1 1 10 9 CRT_B_CON VSYNC_CON 1 1 10 9 VSYNC_CON

CRT_G_CON 2 2 9 8 CRT_G_CON HSYNC_CON 2 2 9 8 HSYNC_CON

CRT_R_CON 4 4 7 7 CRT_R_CON CRT_DDC_CLK 4 4 7 7 CRT_DDC_CLK

CRT_DET# 5 5 6 6 CRT_DET# CRT_DDC_DAT 5 5 6 6 CRT_DDC_DAT

3 3 3 3
A A
8 8

AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
@ @
For EMC
Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 CRT


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 36 of 59
5 4 3 2 1
5 4 3 2 1

+3VALW TO +3VALW_LAN
+3VALW_LAN rising time (10%~90%):
+3VALW +3VALW_LAN
0.5ms<
< spec<
< 100ms +3VALW_LAN +LAN_VDDREG
Need short
@
JL1 1 2 @ width : 40 mils RL1 1 2
1 2 0_0603_5%
JUMP_43X79
D D
1 1
+3VALW LP2301ALT1G_SOT23-3 CL1 CL2

.1U_0402_10V6-K

.1U_0402_10V6-K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 1 4.7U_0603_6.3V6K .1U_0402_10V6-K

D
Q14 3 1 @ CL4 CL5 CL6 CL7

.1U_0402_10V6-K

.01U_0402_16V7-K
1
2 2 CD@
RL2 1 1
100K_0402_5% CL8 CL9 @ 2 @ 2 2 2

G
2
@
2

2 2
RL3 1 @ 2 @ @
44 LAN_PWR_ON#
47K_0402_5%
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32
+3VALW_LAN +3VS

+3VALW_LAN

2
RL4

G
2
10K_0402_5% QL1
RL5 @
10K_0402_5% UL1

1
@ LAN_CLKREQ#_R 1 3 @
LAN_CLKREQ# 8

S
1

2N7002KW_SOT323-3
RL7 1 @ 2 0_0402_5% PCIE_WAKE#_R
8,9,40,44 PCIE_WAKE#
40,44 LAN_WAKE# RL6 1 2 0_0402_5%
33 0_0402_5% 2 1 RL18
C +3VALW_LAN 32 GND 16 CLK_PCIE_LAN# @ C
1 2 RSET 31 AVDD33_2 REFCLK_N 15 CLK_PCIE_LAN CLK_PCIE_LAN# 8
RL8
30 RSET REFCLK_P 14 CLK_PCIE_LAN 8
2.49K_0402_1% +LAN_VDD10 PCIE_PTX_C_DRX_N3
29 AVDD10 HSIN 13 PCIE_PTX_C_DRX_N3 9
LAN_XTALO PCIE_PTX_C_DRX_P3
CKXTAL2 HSIP PCIE_PTX_C_DRX_P3 9
LAN_XTALI 28 12 LAN_CLKREQ#_R
+3VS TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
LAN_PWR_ON# RL121 @ 2 LAN_DISABLE# 26 LED0 AVDD33_1 10 LAN_MDI3-
LED1/GPIO MDIN3 LAN_MDI3- 38
0_0402_5% TL4 @ 1 25 9 LAN_MDI3+
LED2 MDIP3 LAN_MDI3+ 38
1

+LAN_REGOUT 24 8 +LAN_VDD10
RL9 +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
22 VDDREG MDIN2 6 LAN_MDI2- 38
1K_0402_1% +LAN_VDD10 LAN_MDI2+
PCIE_WAKE#_R 21 DVDD10 MDIP2 5 LAN_MDI1- LAN_MDI2+ 38
LANWAKEB MDIN1 LAN_MDI1- 38
ISOLATE# 20 4 LAN_MDI1+
2

19 ISOLATEB MDIP1 3 LAN_MDI1+ 38


PLT_RST# +LAN_VDD10
8,19,40,44 PLT_RST# PERSTB AVDD10_1
9 PCIE_PRX_DTX_N3 CL10 1 2 .1U_0402_10V6-K PCIE_PRX_C_DTX_N3 18 2 LAN_MDI0-
HSON MDIN0 LAN_MDI0- 38
ISOLATE# RL10 1 @ 2 LAN_PWR_ON#
9 PCIE_PRX_DTX_P3 CL11 1 2 .1U_0402_10V6-K PCIE_PRX_C_DTX_P3 17 1 LAN_MDI0+
HSOP MDIP0 LAN_MDI0+ 38
0_0402_5% CL10 close to Pin18
1

RL11 CL11 close to Pin17


15K_0402_5%
@
2

RTL8111GUL-CG_QFN32_4X4
GIGA@

B B

LAN_XTALI For RTL8111GUL/ RTL8106EUL (SWR mode)


+LAN_VDD10
YL1 LAN_XTALO

1 4
OSC1 GND2 +LAN_REGOUT LL1 1 2
2 3 2.2UH_NLC252018T-2R2J-N_5%
GND1 OSC2
1 1 1 1 1 1 1 1
1 1
CL12 CL13 CL15 CL16 CL17 CL18 CL19 CL20 CL21 CL22
10P_0402_50V8J 25MHZ_10PF_7V25000014 10P_0402_50V8J 4.7U_0603_6.3V6K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K 1U_0402_6.3V6K .1U_0402_10V6-K
2 2 CD@ 2 2 2 2 2 @ 2 @
2 2

Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)


Layout Note: LL1 must be
within 200mil to Pin24,
CL15,CL16 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 LAN_RTL8111GUL/RTL8106EUL


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 37 of 59
5 4 3 2 1
5 4 3 2 1

DL1/DL2
1'S PN:SC300003M00
TL1 GIGA@
24 1 MCT
D MCT1 TCT1 D
LAN_MDI0- 23 2 LAN_MDO0-
37 LAN_MDI0- MX1+ TD1+
DL1 @
LAN_MDI2+ 9 3 LAN_MDI3+ LAN_MDI0+ 22 3 LAN_MDO0+
I/O4 I/O2 37 LAN_MDI0+ MX1- TD1-

1
2
NC1 10 21 4 MCT RL17
4 NC5 MCT2 TCT2 20_0603_5%
NC2

1
5 11 LAN_MDI1- 20 5 LAN_MDO1-
+3VALW_LAN VDD GND 37 LAN_MDI1- MX2+ TD2+ DL3

1
2
6 8 LAN_MDI1+ 19 6 LAN_MDO1+ BS4200N-C-LV_SMB-F2
NC3 NC4 37 LAN_MDI1+ MX2- TD2-

2
LAN_MDI2- 7 1 LAN_MDI3- 18 7 MCT
I/O3 I/O1 MCT3 TCT3

2
AZ3033-04F_DFN2525P10E10 LAN_MDI2+ 17 8 LAN_MDO2+
37 LAN_MDI2+ MX3+ TD3+
LAN_MDI2- 16 9 LAN_MDO2-
37 LAN_MDI2- MX3- TD3-
15 10 MCT
MCT4 TCT4
1 1
LAN_MDI3+ 14 11 LAN_MDO3+ CL25
37 LAN_MDI3+ MX4+ TD4+

68P_0402_50V8J
DL2 CL32 1000P_1206_2KV7-K
LAN_MDI1+ 9 3 LAN_MDI0+ 1 LAN_MDI3- 13 12 LAN_MDO3- 0.022U_0603_50V7K @
I/O4 I/O2 37 LAN_MDI3- MX4- TD4- 2 2

CL24
2
NC1 10
C NC5 C
4 GST5009 LF
5 NC2 11 2
+3VALW_LAN VDD GND
6 8
NC3 NC4
LAN_MDI1- 7 1 LAN_MDI0-
I/O3 I/O1 CHASSIS1_GND
AZ3033-04F_DFN2525P10E10
@

Place Close to TL1

JRJ1 ME@
12
GND_4
11
GND_3
10
LAN_MDO0+ 1 GND_2
PR1+ 9
B B
LAN_MDO0- 2 GND_1
PR1-
@ LAN_MDO1+ 3
RL14 1 2 0_0603_5% PR2+ CHASSIS1_GND
@ LAN_MDO2+ 4
RL15 1 2 0_0603_5% PR3+
@ LAN_MDO2- 5
RL16 1 2 0_0603_5% PR3-
LAN_MDO1- 6
PR2-
LAN_MDO3+ 7
PR4+
CHASSIS1_GND LAN_MDO3- 8
Reserve for EMI go rural solution PR4-

SANTA_130460-3

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 LAN_Transformer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 38 of 59
5 4 3 2 1
5 4 3 2 1

D D

Close to U1
SMSC thermal sensor REMOTE1+
Near GPU&VRAM
REMOTE+_R 1
placed near DIMM

1
1 C45 C
C44 100P_0402_50V8J 2 Q15
2200P_0402_50V7K @ B MMBT3904WH_SOT323-3
+3VS 2 E PX@

3
2 REMOTE-_R U1 REMOTE1-
1 8 EC_SMB_CK2
VDD SCL EC_SMB_CK2 7,20,44

1 REMOTE+_R 2 7 EC_SMB_DA2
D+ SDA EC_SMB_DA2 7,20,44
C47 REMOTE-_R 3 6
.1U_0402_10V6-K D- ALERT#
CD@ 2 R51 2 @ 1 4 5 REMOTE2+
Near CPU core
+3VS T_CRIT# GND
10K_0402_5% 1

1
NCT7718W_MSOP8 C46 C
100P_0402_50V8J 2 Q16
@ B MMBT3904WH_SOT323-3
2 E UMA@
Address 1001_100xb

3
REMOTE2-

REMOTE1+ R175 1 @ 2 0_0402_5%

REMOTE2+ R176 1 UMA@ 2 0_0402_5% REMOTE+_R

C REMOTE2- R177 1 UMA@ 2 0_0402_5% REMOTE-_R C

REMOTE1- R178 1 @ 2 0_0402_5%

REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:


Trace width/space:10/10 mil
Trace length:<8"

FAN Conn
B B

+5VS
@ JFAN1
R52 1 2 0_0603_5% +5VS_FAN 1
2 1
44 EC_FAN_SPEED 2
1 1 44 EC_FAN_PWM 3
C50 4 3
C49 .1U_0402_10V6-K 5 4
10U_0805_10V6K @ 6 GND1
2 2 GND2
ACES_85205-04001
ME@

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 Thermal sensor/FAN CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 39 of 59

5 4 3 2 1
A B C D E

Mini-Express Card(WLAN/WiMAX) +3VS_WLAN

+3VS Need short +3VS_WLAN JWLAN1


J2 @ 1 2
1 2 3 GND1 3.3VAUX1 4
1 2 9 USB20_P6 5 USB_D+ 3.3VAUX2 6 1 @ T2
9 USB20_N6 USB_D- LED#1
JUMP_43X79 7 8
GND2 NC
9 NC NC 10
+3VALW 11 NC NC 12
LP2301ALT1G_SOT23-3 13 14
NC NC 16 1
15 @ T3
NC LED#2 18

D
Q17 3 1 AOAC@ 17
1 MLDIR_SENSE GND16 20 1

.01U_0402_16V7-K
19
21 DP_ML3N DP_AUXN 22
1 1 1 DP_ML3P DP_AUXP 24
C51 C52 C53 23

G
2
.1U_0402_10V6-K @ .1U_0402_10V6-K 25 GND3 GND13 26
@ AOAC@ 27 DP_ML2N DP_ML1N 28
2 2 2 29 DP_ML2P DP_ML1P 30
R54 1 AOAC@ 2 31 GND4 GND14 32
44 AOAC_ON#
1 33 DP_HPD DP_ML0N 34
100K_0402_5% C54 35 GND5 DP_ML0P 36
9 PCIE_PTX_C_DRX_P4
.1U_0402_10V6-K 37 PETP0 GND15 38 EC_TX_RSVD R62 1 @ 2 0_0402_5% EC_TX_R
9 PCIE_PTX_C_DRX_N4
AOAC@ 39 PETN0 RESERVED1 40 EC_RX_RSVD R63 1 @ 2 0_0402_5% BT_OFF#
2 41 GND6 RESERVED2 42
9 PCIE_PRX_DTX_P4
43 PERP0 RESERVED3 44
9 PCIE_PRX_DTX_N4 45 PERN0 COEX3 46
47 GND7 COEX2 48
8 CLK_PCIE_WLAN
49 REFCLKP0 COEX1 50 SUSCLK_R R55 1 @ 2 0_0402_5%
8 CLK_PCIE_WLAN# 51 REFCLKN0 SUSCLK 52 SUSCLK 8
PLT_RST#
PLT_RST# 8,19,37,44
WLAN_CLKREQ_Q# 53 GND8 PERST0# 54 BT_OFF# R53 1 2 1K_0402_5%
55 CLKREQ0# RESERVED/W_DISABLE#2 56 1 2 PCH_BT_OFF# 9
WLAN_OFF# R56 @ 0_0402_5%
8,9,37,44 PCIE_WAKE# PCH_WLAN_OFF# 9
57 PEWAKE0# W_DISABLE#1 58 SMB_DATA_S3_R R58 1 @ 2 0_0402_5%
SMB_DATA_S3 7,14,15
R57 1 @ 2 0_0402_5% 59 GND9 I2C_DATA 60 SMB_CLK_S3_R R59 1 @ 2 0_0402_5%
37,44 LAN_WAKE# 61 PETP1 I2C_CLK 62 1 SMB_CLK_S3 7,14,15
@ T4
63 PETN1 I2C_ALERT# 64 EC_TX_R
65 GND10 RESERVED4 66
67 PERP1 PERST1# 68 +3VS_WLAN
69 PERN1 CLKREQ1# 70
71 GND11 PEWAKE1# 72
73 REFCLKP1 3.3VAUX4 74
+3VS 75 REFCLKN1 3.3VAUX5
+3VS_WLAN GND12
76 77 EC_TX_R R184 1 2 100_0402_1%
PEG1 PEG2 EC_TX 44
2

JAE_SM3ZS067U410BAR1000 BT_OFF# R185 1 2 100_0402_1%


EC_RX 44
2

R60 ME@
G

Q18 10K_0402_5%

1
AOAC@
R186
1

2 8 WLAN_CLKREQ# AOAC@ 3 1 WLAN_CLKREQ_Q# 100K_0402_5% 2


S

2N7002KW_SOT323-3

2
R61 1 @ 2 0_0402_5%

If support AOAC, NC R61;


if not support AOAC, stuff R61.

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 NGFF WLAN


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 40 of 59
A B C D E
A B C D E

+USB_VCCA

LEFT SIDE USB3.0 PORT X2 C55 1 2

+
220U_6.3V_M
U2 +USB_VCCA C56 1 2
+5VALW @ 1U_0603_25V6M
1 8
GND VOUT3 C57 1 2
1 2 7 @ 470P_0402_50V7K 1
2.2U_0603_10V6-K VIN1 VOUT2
C58 1 2 3 6
VIN2 VOUT1 JUSB1 ME@
44,45 USB_ON# USB_ON# 4 5 USB_OC1# 1
EN/EN FLAG USB_OC1# 9 USB20_N2 R65 1 @ 2 0_0402_5% USB20_N2_R 2 VBUS
9 USB20_N2 D-
1 USB20_P2 R64 1 @ 2 0_0402_5% USB20_P2_R 3
9 USB20_P2 D+
AP2820CMMTR-G1_MSOP8 C61 4 5
1000P_0402_50V7K GND GND1 6
@ GND2 7
Low Active 2A 2 GND3 8
GND4
C-K_20267-5K11-02

USB20_P2_R
+USB_VCCA
USB20_N2_R

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
1

1
D9 D10 D11

1
2 2

2
@ @ @

2
USB20_P1_R
L8 D12 @
USB20_P2 1 2 USB20_P2_R USB30_RX_R_N1 9 10 1 1USB30_RX_R_N1 USB20_N1_R
1 2

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
USB30_RX_R_P1 8 9 2 2 USB30_RX_R_P1

1
USB20_N2 4 3 USB20_N2_R D13 D14
4 3 USB30_TX_R_N1 7 4 USB30_TX_R_N1
7 4

1
CMM21T-900M-N_4P
USB30_TX_R_P1 6 6 5 5 USB30_TX_R_P1

3 3

2
8 @ @

2
AZ1045-04F_DFN2510P10E-10-9

3 3
L9 For EMC
USB30_RX_N1 3 4 USB30_RX_R_N1
3 4

USB30_RX_P1 2 1 USB30_RX_R_P1
2 1 +USB_VCCA
DLW21SN900HQ2L_4P
C62 1 2
@ 1U_0603_25V6M
L10
USB30_TX_C_N1 3 4 USB30_TX_R_N1 C63 1 2
3 4 @ 470P_0402_50V7K

USB30_TX_C_P1 2 1 USB30_TX_R_P1
2 1 JUSB2 ME@
DLW21SN900HQ2L_4P USB30_TX_P1 C64 1 2 .1U_0402_10V6-K USB30_TX_C_P1 R68 1 @ 2 0_0402_5% USB30_TX_R_P1 9
9 USB30_TX_P1 StdA_SSTX+
1
L11 USB30_TX_N1 C65 1 2 .1U_0402_10V6-K USB30_TX_C_N1 R69 1 @ 2 0_0402_5% USB30_TX_R_N1 8 VBUS
9 USB30_TX_N1 StdA_SSTX-
USB20_N1 1 2 USB20_N1_R USB20_P1 R70 1 @ 2 0_0402_5% USB20_P1_R 3
1 2 9 USB20_P1 D+
7
USB20_N1 R71 1 @ 2 0_0402_5% USB20_N1_R 2 GND_DRAIN 10
9 USB20_N1 D- GND_1
USB20_P1 4 3 USB20_P1_R USB30_RX_P1 R72 1 @ 2 0_0402_5% USB30_RX_R_P1 6 11
4 3 9 USB30_RX_P1 StdA_SSRX+ GND_2
4 12
CMM21T-900M-N_4P USB30_RX_N1 R73 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_5 GND_3 13
9 USB30_RX_N1 StdA_SSRX- GND_4
SUYIN_020053GR009M2736L
4 4
For EMC

Security Classification
Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 USB2.0/USB3.0 PORT (LEFT)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 41 of 59

A B C D E
A B C D E F G H

SATA HDD Conn.


FOR 14"
JHDD1 ME@

1
SATA ODD Conn.
SATA_PTX_DRX_P0 C66 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P0 2 GND_1
7 SATA_PTX_DRX_P0 A+
7 SATA_PTX_DRX_N0 SATA_PTX_DRX_N0 C67 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N0 3
4 A-
1 SATA_PRX_DTX_N0 C68 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N0 5 GND_2 1
7 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P0 6 B- JODD1
7 SATA_PRX_DTX_P0 7 B+ 1
GND_3 SATA_PTX_DRX_P1 14@ C70 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1_14 2 GND_1
7 SATA_PTX_DRX_P1 RX+
7 SATA_PTX_DRX_N1 SATA_PTX_DRX_N1 14@ C71 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N1_14 3
8 4 RX-
9 V33_1 SATA_PRX_DTX_N1 14@ C72 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1_14 5 GND_2
10 V33_2 7 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 14@ C73 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1_14 6 TX-
+5VS +5VS_HDD 11 V33_3 7 SATA_PRX_DTX_P1 7 TX+
Need short 12 GND_4 GND_3
J3 @ 13 GND_5 ODD_DETECT#_R 8
1 2 14 GND_6 9 DP
1 2 15 V5_1 +5V_ODD 10 +5V_1
JUMP_43X79 16 V5_2 ODD_DA#_R 11 +5V_2 14
17 V5_3 12 MD GND1 15
18 GND_7 13 GND_4 GND2
19 DAS/DSS GND_5
+5VS_HDD 20 GND_8 SUYIN_127382FB013S255ZL
21 V12_1 ME@
22 V12_2
V12_3
1 1 1 1 1
C74 C75 C76 C77 C78 SUYIN_127043HR022M32QZR
1000P_0402_50V7K .1U_0402_10V6-K 1U_0402_10V6K 10U_0805_10V6K 10U_0805_10V6K
CD@ CD@ @
2 2 2 2 2

FOR 15"
2 2

For EMC SATA ODD FFC Conn

JODD2
SATA_PTX_DRX_P1 15@ C79 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1_15 1
SATA_PTX_DRX_N1 15@ C80 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N1_15 2 1
3 2
SATA_PRX_DTX_N1 15@ C81 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1_15 4 3
SATA_PRX_DTX_P1 15@ C82 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1_15 5 4
6 5
R74 1 2 0_0402_5% ODD_DETECT#_R 7 6
7 ODD_DETECT# 8 7
+5V_ODD 9 8
@ 9

2
ODD_DA#_R 10
R92 10
Need Short 0_0402_5% 11
@ 12 GND_1
J4 GND_2

1
1 2 ACES_51524-01001-003
1 2 ME@
JUMP_43X79

+5VALW +5VS +5V_ODD


LP2301ALT1G_SOT23-3
3 3

3
S

1 Q19
.1U_0402_10V6-K

.01U_0402_16V7-K
1

+3VS
C83

C84

@
10U_0805_10V6K

.1U_0402_10V6-K
1 1
R75 R76
G

1 1
2

10K_0402_5% 10K_0402_5%
@ @

1
@2 @2
2

1
2 2
C86

R77
C85

ODD_EN# 1 2 R78 R79 10K_0402_5%


100K_0402_5% 1 470_0603_5%
@ C87 CD@ @ @

2
.01U_0402_16V7-K
2
1

Q20 D @ R80 1 @ 2 0_0402_5% ODD_DA#_R


2 2 9 ODD_DA#
9 ODD_EN
G R86 1 @ 2 0_0402_5%

100P_0402_50V8J
44 ODD_DA_EC#
1

Q21 D
2

C139
S 2N7002KW_SOT323-3 ODD_EN# 2 1
3

R81 @ G
100K_0402_5%
@ S 2N7002KW_SOT323-3
3

@ @2
1

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 HDD/ODD CONN


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 42 of 59
A B C D E F G H
5 4 3 2 1

+3VS

+3VS +1.5VS RA3 1 @ 2 0_0603_5%


@ +3VALW +5VA AVDD_HP

.1U_0402_10V6-K

.1U_0402_10V6-K
RA2 1 2 0_0603_5% +3.3VD RA8 1 @ 2 0_0402_5%
+3VS

CA11

CA12
RA5 1 @ 2 0_0603_5% AVDD_HP 2 2
+3VL
RA11 1 @ 2 0_0402_5% DVDD_IO
RA43 1 2 0_0603_5%
+5VS 1 1

.1U_0402_10V6-K
@ 2
RA7 1 2 0_0603_5% +5VA CA1
D @ D
RA10 1 2 0_0603_5% +5VD 1 Close to Pin28 Close to Pin24
Close to Pin3

Close to Pin7
DA1
2
44 BEEP#

.1U_0402_10V6-K

4.7U_0603_10V6-K
.1U_0402_10V6-K CA16 close to Pin18
1 PC_BEEP1 CA2 1 2 PC_BEEP 2 1 CA17 close to Pin2
Close to Pin27

1
3
9 PCH_BEEP
RA14
1 2

CA3

1U_0402_6.3V6K
.1U_0402_10V6-K
BAT54CW_SOT323-3 10K_0402_5%

CA4

CA7

CA8
2 1

.1U_0402_10V6-K

2.2U_0603_6.3V6K
UA1
2

2 1

CA5

CA6
HDA_RST_AUDIO# 9 3 FILT_1.8V
7 HDA_RST_AUDIO# RESET# FILT_1.8V 7 DVDD_IO CD@ 1 2
VDD_IO 2
HDA_BITCLK_AUDIO 5 VDDO_3.3 18 +3.3VD 1 2
7 HDA_BITCLK_AUDIO BIT_CLK DVDD_3.3
HDA_SYNC_AUDIO 8 27 AVDD_3.3
7 HDA_SYNC_AUDIO RA16 SYNC AVDD_3.3 29 VREF_1.65V
33_0402_5% 1 2 SDATA_IN 6 VREF_1.65V 28 +5VA
7 HDA_SDIN0 SDATA_IN AVDD_5V

.1U_0402_10V6-K

1U_0402_6.3V6K
HDA_SDOUT_AUDIO 4
7 HDA_SDOUT_AUDIO SDATA_OUT

CA9

CA10
MICBIASB
CX20751-11Z
+3.3VD

2 1
PC_BEEP 10 12 SPK_L+
SPKR_MUTE# 39 PC_BEEP LEFT+ 14 SPK_L-
SPKR_MUTE# LEFT- DA2
JSENSE 38 17 SPK_R+ BAT54AWT1G_SOT323-3 1 2

LINE_B_R

LINE_B_L
JSENSE RIGHT+
2

1
37 15 SPK_R-
GPIO1/PORTC_R_MIC RIGHT-

1
C RA15 C
5.11K_0402_1% 36 35 RA42 RA41
33_0402_5% 1 RA18 2 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34
33 DMIC_CLK
DMIC_CLK_R
DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB
MICBIASB 0_0402_5% 0_0402_5% Close to Pin29
RA19 1 @ 2 DMIC_DATA_R 1 @ @
1

33 DMIC_DATA DMIC_DAT/GPIO1

1
0_0402_5% 33 LINE_B_R

2
RA17 1 2 JSENSE .1U_0402_10V6-K PORTB_R_LINE 32 LINE_B_L
45 PLUG_IN +5VD 1 2 11 PORTB_L_LINE
39.2K_0402_1% RA39 RA40
CA13 CLASS-D_REF 30 PORTD_A_MIC 100_0402_5% 100_0402_5%
RA36 1 2 13 PORTD_A_MIC 31 PORTD_B_MIC

2
LPWR_5.0 PORTD_B_MIC

3K_0402_1%

3K_0402_1%
20K_0402_1% 16
RPWR_5.0

1
25 RING2_CONN 1 1
HGNDA

RA37

RA38
CA14 1 2 1U_0402_6.3V6K 19 26 RING3_CONN
20 FLY_P HGNDB CA35 CA36
FLY_N 24 AVDD_HP 4.7U_0603_10V6-K 4.7U_0603_10V6-K
CA17 1 2 2.2U_0603_6.3V6K 21 AVDD_HP 2 2

2
AVEE 23 HPOUT_R RA20 1 2 82.5_0402_1%
41 PORTA_R 22 HP_OUTR 45
HPOUT_L RA21 1 2 82.5_0402_1%
GND PORTA_L HP_OUTL 45

CD@ CD@ +5VD Stuff DA2 to prevent RA22


CX20752-21Z_QFN40_5X5 cross-talk between PORTD_A_MIC 1 2 100_0402_5% CA20 1 2 2.2U_0603_6.3V6K
1 2 100_0402_5% RING3_CONN 45
PORTD_B_MIC CA21 1 2 2.2U_0603_6.3V6K
HPOUT_R/L,if NC RING2_CONN 45
CA15

CA16

CA18

CA19
4.7U_0603_10V6-K

4.7U_0603_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

DA2,RA37/RA38 need change RA23


1 1 2 2
RA1 1 @ 2 0_0402_5% to 2.2K.
RA4 1 @ 2 0_0402_5%
2 2 1 1
RA6 1 @ 2 0_0402_5%

RA9 1 @ 2 0_0402_5%

B RA12 1 @ 2 0_0402_5% B
+3.3VD

Close to Pin11,13,16 RA13 1 @ 2 0_0402_5%

RA24 1 @ 2
1

0_0402_5% GND GNDA


RA28
47K_0402_5% Use 250mils wide trace bridging
RB751V-40_SOD323-2 @ AGND and DGND at codec
HDA_RST_AUDIO# DA3 1 2 @
2

SPKR_MUTE#
RB751V-40_SOD323-2
EC_MUTE# DA4 1 2 @ JSPK1
44 EC_MUTE# 1 CD@ 2 1 2 1
HDA_RST_AUDIO# 15_0402_5% RA25 SPK_R+ RA26 BLM18PG221SN1D_2P SPK_R+_CONN
15_0402_5% 1 2 RA29 SPK_R- RA31 1 2 BLM18PG221SN1D_2P SPK_R-_CONN 2 1
HDA_SYNC_AUDIO 15_0402_5% 1 2 RA32 SPK_L+ RA30 1 2 BLM18PG221SN1D_2P SPK_L+_CONN 3 2
15_0402_5% 1 CD@ 2 RA33 SPK_L- RA34 1 2 BLM18PG221SN1D_2P SPK_L-_CONN 4 3
RA35 1 2 HDA_SDOUT_AUDIO 4
CD@
0_0402_5% CD@ 5
RA27 1 @ 2 HDA_BITCLK_AUDIO 6 GND1
GND2
220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K
CA27

CA28

CA29

27_0402_5% CA30
DMIC_CLK HDA_SDIN0 2 2 2 2 1 1 1 1 ACES_88231-04001

CA31

CA32

CA33

CA34
ME@
CA23

CA24

CA25

CA26
68P_0402_50V8J

22P_0402_50V8-J

22P_0402_50V8-J

33P_0402_50V8J

33P_0402_50V8J

DMIC_DATA
1 1 1 1 2 2 2 2
1 1 1 1 1
CA22
100P_0402_50V8J

100P_0402_50V8J
CA37

CA38

1 1 2 2 2 2 2
@

A A
CD@ CD@ CD@ CD@
2 2
@ @ For EMI

Security Classification LC Future Center Secret Data Title


For EMI
Issued Date 2013/08/08 Deciphered Date 2013/08/05 Codec_CX20752
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 43 of 59
5 4 3 2 1
5 4 3 2 1

For EMI RE1 1 @ 2 0_0603_5%


For ESD +3VL
PLT_RST# CLK_PCI_EC RE2 1 @ 2 10_0402_5%
@
RE3 1 2 0_0603_5%
1 1 Close EC +3VALW
CE1 CE2 +3VALW_EC
220P_0402_50V7K 10P_0402_50V8J CE3 +3VALW_R +3VALW_R
2 @ 2 1 2 VCOREVCC
LE1 1 2 HCB1608KF-181T20
.1U_0402_10V6-K +3VALW_R All capacitors close to EC +3VALW_R
1 1
CE4

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
1 1 1 1 1 1 .1U_0402_10V6-K CE5

1
+3VS +3VALW_EC CE6 CE7 CE8 CE9 CE10 CE11 1000P_0402_50V7K
VCCRTC RE4 1 @ 2 0_0402_5% LE2 1 2 HCB1608KF-181T202 EC_AGND 2 RE5
D D
@ 10K_0402_5%
2 2 2 2 2 2
RE6 1 2 0_0402_5% EC_AGND

2
@
CD@ LAN_WAKE# LAN_WAKE# 37,40

minimum trace width 12 mil

114
121
127
Change RE6 to 0ohm jump

12

11

26
50
92

74
3
UE1

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

AVCC
VBAT

VSTBY(PLL)
VCORE
+3VS

20 WRST# EC_FAN_SPEED RE10 1 2 10K_0402_5%


4 24
+3VALW_R 9 KBRST# 5 KBRST#/GPB6 PWM0/GPA0 25 PWR_LED# 45
EC_FAN_PWM RE11 1 @ 2 10K_0402_5%
9 SERIRQ SERIRQ/GPM6 PWM1/GPA1 BATT_CHG_LED# 45
LPC_FRAME# 6 28
7 LPC_FRAME# 7 LFRAME#/GPM5 PWM2/GPA2 29 BATT_LOW_LED# 45 1 2 10K_0402_5%
LPC_FRAME# RE7
7 LPC_AD3 LAD3/GPM3 PWM3/GPA3 BATT_LEN# 52
DE1 1 2 @ 8 PWM 30
7 LPC_AD2 LAD2/GPM2 PWM4/GPA4 SYS_PWROK 8
9 31 EC_FAN_PWM ENBKL RE9 1 @ 2 100K_0402_5%
7 LPC_AD1 10 LAD1/GPM1 PWM5/GPA5 32 EC_FAN_PWM 39
RB751V-40_SOD323-2 7 LPC_AD0 LAD0/GPM0 PWM6/SSCK/GPA6 BEEP# 43
CLK_PCI_EC 13 LPC 34 SUS_VCCP
1 2 100K_0402_5% 8 CLK_PCI_EC 14 LPCCLK/GPM4 PWM7/RIG1#/GPA7 120 SUS_VCCP 57
RE8 WRST# LAN_WAKE#
15 WRST# TMRI0/GPC4 124 SUSP# +5VS +3VS
9 EC_SMI# ECSMI#/GPD4 TMRI1/GPC6 SUSP# 35,46,55,56,57,58
1 EC_RX 16
40 EC_RX 17 PWUREQ#/BBO/SMCLK2ALT/GPC7 66
EC_TX NTC_V 52
40 EC_TX LPCPD#/GPE6 ADC0/GPI0

2
CE12 PLT_RST# 22 67
1U_0402_6.3V6K 8,19,37,40 PLT_RST# LPCRST#/GPD2 ADC1/GPI1 TURBO_V 52
23 68 BATT_TEMP RE52 RE51
2 9 EC_SCI# ECSCI#/GPD3 ADC2/GPI2 BATT_TEMP 52,53
@ 1 PAD 126 ADC 69 0_0402_5% 0_0402_5%
IT9 GA20/GPB5 ADC3/GPI3 VR_IMVP_IMON 59
70 @
IT8586E/AX ADC4/GPI4 71 VR_CPU_PWROK
ADP_I 52,53
10,59

1
ADC5/DCD1#/GPI5 72

45 KSI[0..7]
KSI[0..7] KSI0 58
KSI0/STB#
LQFP-128L ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
73 ADAPTER_ID 51,53
VGA_IMON 58
TP_CLK RE12 2 1 4.7K_0402_5%
KSI1 59 78
KSO[0..17] KSI1/AFD# DAC2/TACH0B/GPJ2 SUSWARN# 8
KSI2 60 79 @ TP_DATA RE13 2 1 4.7K_0402_5%
45 KSO[0..17] KSI2/INIT# DAC3/TACH1B/GPJ3 MAINPWON 52
C KSI3 61 DAC 80 H_PROCHOT#_EC RE14 1 2 0_0402_5% C
62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 PROCHOT# 52
KSI4 ENBKL 33
KSI4 DAC5/RIG0#/GPJ5
+3VALW_R
KSI5 63
KSI5 Change RE14 to 0ohm jump
KSI6 64 85 +5VALW
65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 VGA_PWRGD 9,19,58
KSI7
KSI7 PS2DAT0/TMB1/GPF1 PBTN_OUT# 8
KSO0 36 87
1 37 KSO0/PD0 GPF2 88 PM_SLP_SUS# 8
EC_SMB_CK1 PAD @ KSO1 Int. K/B PS2 USB_ON# RE15 1 2 100K_0402_5%
IT1 KSO1/PD1 GPF3 SUSACK# 8
1 RE16 2 2.2K_0402_5% EC_SMB_CK1 EC_SMB_DA1 PAD 1 @ KSO2 38 89 TP_CLK
1
IT2
KSO3 39 KSO2/PD2 Matrix PS2CLK2/GPF4 90 TP_DATA
TP_CLK 45
PAD @
1 RE17 2 2.2K_0402_5% 1 IT3 40 KSO3/PD3 PS2DAT2/GPF5 TP_DATA 45
EC_SMB_DA1 PAD @ KSO4
IT4 KSO4/PD4
PAD 1 @ KSO5 41 EXTERNAL SERIAL FLASH 96 +3VALW_R
IT5 42 KSO5/PD5 GPH3/ID3 97 CAPS_LED# 45
KSO6
KSO6/PD6 GPH4/ID4 PCH_PWR_EN 46,52
KSO7 43 98
KSO7/PD7 GPH5/ID5 ACOFF 53
KSO8 44 99
+3VS 1 45 KSO8/ACK# GPH6/ID6 PCH_PWROK 8,10
KSI7 PAD @ KSO9 SUSP# RE18 1 @ 2 100K_0402_5%
IT6 KSO9/BUSY
KSI6 PAD 1 @ KSO10 46 101 EC_SPI_CS0#
1 IT7 51 KSO10/PE NC1 102
WRST# PAD @ KSO11 EC_SPI_SI SUSP# RE19 1 2 100K_0402_5%
IT8 KSO11/ERR# NC2
1 RE20 2 2.2K_0402_5% EC_SMB_CK2 KSO12 52 SPI Flash ROM 103 EC_SPI_SO
KSO13 53 KSO12/SLCT NC3 105 EC_SPI_CLK SYSON RE21 1 2 100K_0402_5%
1 RE22 2 2.2K_0402_5% 54 KSO13 NC4
EC_SMB_DA2 For factory EC flash KSO14
KSO14
KSO15 55 SUS_VCCP RE23 1 2 100K_0402_5%
KSO16 56 KSO15 108 ACIN#
KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW# EC_ADAPTER_R RE28 1 @ 2 100K_0402_5%
KSO17/SMISO/GPC5 UART LID_SW# LID_SW# 45

45 ON/OFF ON/OFF 110 82 VGA_GATE#


111 PWRSW# EGAD/GPE1 83 VGA_GATE# 4
54 EC_ON XLP_OUT SM Bus EGCS#/GPE2 VDDQ_PGOOD 55
EC_SMB_CK1 115 84 ADAPTER_ID_ON# 53 @
52,53 EC_SMB_CK1 SMCLK1/GPC1 EGCLK/GPE3
EC_SMB_DA1 116 0_0402_5% 2 1 RE26
52,53 EC_SMB_DA1 SMDAT1/GPC2 EC_ADAPTER 51
5 H_PECI RE24 1 2 43_0402_5% PECI_EC 117 GPIO 77
SMCLK2/PECI/GPF6 GPJ1 EC_MUTE# 43
118 100 GPG2
37 LAN_PWR_ON# 94 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 106
EC_SMB_CK2 EC_ADAPTER_R RE25 2 @ 1 0_0402_5%
7,20,39 EC_SMB_CK2 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 PM_SLP_S5# 8
EC_SMB_DA2 95 104 SYSON
+3VL 7,20,39 EC_SMB_DA2 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 ME_FLASH 7
107 SYSON
DTR1#/SBUSY/GPG1/ID7 119 SYSON 55
BKOFF#
CRX0/GPC0 BKOFF# 33
@ 123
RE27 1 2 0_0402_5% 112 CTX0/TMA0/GPB2 18 AOAC_ON# 40 EMC Request 1
VSTBY0 RI1#/GPD0 PM_SLP_S3# 8
125 21 PM_SLP_S4# 8 RE29 1 2 0_0402_5%
B 59 EC_VR_ON GPE4 RI2#/GPD1 PCIE_WAKE# 8,9,37,40 B
WAKE UP 76 NOVO# 45 @ CE13
TACH2/GPJ0 48 .1U_0402_10V6-K
TACH1A/TMA1/GPD7 EC_TS_ON# 33 2
47 EC_FAN_SPEED EC_FAN_SPEED 39
USB_ON# 33 TACH0A/GPD6 19 RE30 1 @ 2 0_0402_5% VGA_AC_DET
41,45 USB_ON# GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 VGA_AC_DET 20
35 GPIO 20
8 DPWROK_EC RTS1#/GPE5 L80LLAT/GPE7 NUM_LED# 45
93
8 EC_RSMRST# CLKRUN#/GPH0/ID0 ODD_DA_EC# 42

2 Reserve for VGA_AC_DET


9 EC_LID_OUT# CK32KE/GPJ7
128 Clock
+3VL 8 AC_PRESENT CK32K/GPJ6

Change RE30 to 0ohm jump


RE34 1 2 0_0402_5% H_PROCHOT# 5,51,52
59 VR_HOT# +5VS +3VS
AVSS

RE35 1 2 10K_0402_5% ON/OFF


VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

@ @
@

1
RE36 1 @ 2 10K_0402_5% BKOFF# QE1 D 1 RE37 1 2 0_0402_5%
IT8586E-AX_LQFP128_14X14 H_PROCHOT#_EC 2 CE14
1

27
49
91
113
122

75

RE38 1 2 10K_0402_5% LID_SW# G 47P_0402_50V8J RE39 1 @ 2 0_0402_5% J80P1


@ 1
2N7002KW_SOT323-3 S 2 EC_TX 2 1

3
EC_RX 3 2
RE40 1 2 10K_0402_5% BKOFF# 4 3
4

1
EC_AGND +3VL 5
RE41 6 GND1
100K_0402_5% GND2
@ ACES_85205-04001
for EC version update to EX, manual modify PN to FX

1
ME@

2
RE42
10K_0402_5%
PECI_EC @ CE15 1 2 47P_0402_50V8J

2
+3VL BATT_TEMP @ CE16 1 2 100P_0402_50V8J +3VS ACIN#
8,53 ACIN#
+3VALW_R ACIN# @ CE17 1 2 100P_0402_50V8J

1
1 D QE2
A GPG2 RE43 2 @ 1 10K_0402_5% ON/OFF @ CE18 1 2 1U_0402_6.3V6K CE19 2 A
.1U_0402_10V6-K G ACIN 53
@
GPG2 RE44 2 1 10K_0402_5% EC_SPI_CS0# RE45 2 1 0_0402_5% SPI_CS0#
SPI_CS0# 7 NOVO# 2 2N7002KW_SOT323-3 S

3
GPG2 RE46 2 @ 1 10K_0402_5% @
EC_SPI_SI RE47 2 1 0_0402_5% SPI_SI
SPI_SI 7
.01U_0402_16V7-K

when mirror, GPG2 pull high


C48

@
when no mirror, GPG2 pull low EC_SPI_SO RE48 2 1 0_0402_5% SPI_SO
SPI_SO 7 1
@ Title
EC_SPI_CLK RE49 2 1 0_0402_5% SPI_CLK Security Classification LC Future Center Secret Data
SPI_CLK 7 @2
Issued Date 2013/08/08 Deciphered Date 2013/08/05 EC ITE8586LQFP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 44 of 59
5 4 3 2 1
5 4 3 2 1

ON/OFF switch
+3VL +3VALW
K/B Connector +3VS

2
KSI[0..7]
R82 R83
KSI[0..7] 44
14" 15"

1
@ 100K_0402_5% 100K_0402_5% KSO[0..17]
KSO[0..17] 44
PWR_CAPS_LED C133 1 2 @ 100P_0402_50V8J JKB2 R84 R90
300_0402_5% 300_0402_5%

1
D15 PWR_NUM_LED C134 1 2 @ 100P_0402_50V8J 27 JKB1
NOVO# 2 GND1 28 NUM_LED# 30 31
44 NOVO# 44 NUM_LED#

2
CAPS_LED# C117 1 2 @ 100P_0402_50V8J KSO16 C91 1 2 @ 100P_0402_50V8J CAPS_LED# 26 GND2 PWR_NUM_LED 29 30 GND1 32
1 44 CAPS_LED# 25 26 28 29 GND2
NOVO_BTN# PWR_CAPS_LED CAPS_LED#
@ NUM_LED# C118 1 2 @ 100P_0402_50V8J KSO17 C88 1 2 @ 100P_0402_50V8J KSO15 24 25 PWR_CAPS_LED 27 28
ON/OFF R85 1 2 0_0402_5% 3 KSO10 23 24 KSO17 26 27
KSO2 C89 1 2 @ 100P_0402_50V8J KSO1 C90 1 2 @ 100P_0402_50V8J KSO11 22 23 KSO16 25 26
D D
BAT54CW_SOT323-3 KSO14 21 22 KSO15 24 25
KSO15 C92 1 2 @ 100P_0402_50V8J KSO7 C93 1 2 @ 100P_0402_50V8J KSO13 20 21 KSO10 23 24
KSO12 19 20 KSO11 22 23
KSO6 C94 1 2 @ 100P_0402_50V8J KSI2 C95 1 2 @ 100P_0402_50V8J KSO3 18 19 KSO14 21 22
+3VALW +3VL KSO6 17 18 KSO13 20 21
KSO8 C96 1 2 @ 100P_0402_50V8J KSO5 C97 1 2 @ 100P_0402_50V8J KSO8 16 17 KSO12 19 20
KSO7 15 16 KSO3 18 19
15 18

2
KSO13 C98 1 2 @ 100P_0402_50V8J KSI3 C99 1 2 @ 100P_0402_50V8J KSO4 14 KSO6 17
R111 R114 KSO2 13 14 KSO8 16 17
100K_0402_5% 100K_0402_5% KSO12 C100 1 2 @ 100P_0402_50V8J KSO14 C101 1 2 @ 100P_0402_50V8J KSI0 12 13 KSO7 15 16
@ KSO1 11 12 KSO4 14 15
KSO11 C102 1 2 @ 100P_0402_50V8J KSI7 C103 1 2 @ 100P_0402_50V8J KSO5 10 11 KSO2 13 14

1
@ KSI3 9 10 KSI0 12 13
ON/OFFBTN# R119 1 2 0_0402_5% ON/OFF KSO10 C104 1 2 @ 100P_0402_50V8J KSI6 C105 1 2 @ 100P_0402_50V8J KSI2 8 9 KSO1 11 12
ON/OFF 44 7 8 10 11
KSO0 KSO5
KSO3 C106 1 2 @ 100P_0402_50V8J KSI5 C107 1 2 @ 100P_0402_50V8J KSI5 6 7 KSI3 9 10
J5 1 2 KSI4 5 6 KSI2 8 9
KSO4 C108 1 2 @ 100P_0402_50V8J KSI4 C109 1 2 @ 100P_0402_50V8J KSO9 4 5 KSO0 7 8
SHORT PADS KSI6 3 4 KSI5 6 7
KSI0 C110 1 2 @ 100P_0402_50V8J KSO9 C111 1 2 @ 100P_0402_50V8J KSI7 2 3 KSI4 5 6
J6 1 2 KSI1 1 2 KSO9 4 5
KSO0 C112 1 2 @ 100P_0402_50V8J KSI1 C113 1 2 @ 100P_0402_50V8J 1 KSI6 3 4
SHORT PADS ACES_88514-02601-071 KSI7 2 3
KSI1 1 2
ME@ 1
ACES_50504-3041-001
For EMC ME@

+5VS TP_PWR TP_CLK

C R160 1 @ 2
TP/B Connector TP_DATA PWR/B Connector C
USB I/O Connector

2
+3VS 0_0402_5%
JTP1 DT1
R141 1 2 1
0_0402_5% TP_CLK 2 1
44 TP_CLK 2
TP_DATA 3
44 TP_DATA 3
.1U_0402_10V6-K

1 4
@ 1 @ 1 TP_P5 5 4
5
Right Side USB2.0 Port X 1 (USB/B)
100P_0402_50V8J

100P_0402_50V8J

TP_P6 6 7
6 GND1 8
2 GND2
C114

2 2 ACES_50503-0060N-001
C115

C116

ME@ @ AZC199-02S.R7G_SOT23-3 +3VL +5VALW U3 +USB_VCCB

1
For EMC
JPWRB1 1 8
1 2.2U_0603_10V6-K GND VOUT3 +USB_VCCB
NOVO_BTN# 2 1 C119 1 2 2 7
ON/OFFBTN# 3 2 VIN1 VOUT2 +3VS JUSB3
3
TP_LEFT Button TP_LEFT Button LID_SW# 4
4
3
VIN2 VOUT1
6 18
18 G2
20
TP_P5 TP_P5 5 17 19
6 5 7 USB_ON# 4 5 USB_OC2# @ 16 17 G1

AZ5215-01F_DFN1006P2E2
6 GND1 41,44 USB_ON# EN/EN FLAG USB_OC2# 9 16

1
8 R67 1 2 0_0402_5% USB20_P0_CONN 15
GND2 9 USB20_P0 1 2 0_0402_5% USB20_N0_CONN 14 15
D17 1 R66

1
9 USB20_N0 14
1

5
AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2
ACES_50503-0060N-001 AP2820CMMTR-G1_MSOP8 C120 @ 13
SW1 SW2 ME@ 1000P_0402_50V7K USB20_P3 12 13
A

A
A1

GND1

A1

GND1
EVQPLHA15_4P

EVQPLHA15_4P 9 USB20_P3 12
1

1
DT2 DT3 @ USB20_N3 11
Low Active 2A 2 9 USB20_N3 11

2
10
For 14" For 15"
1

1
@ 9 10

2
9
GND2

GND2

8
LID_SW# 44 7 8
HP_OUTR
1 VDD 1 VDD
B1

B1

43 HP_OUTR 7
B

B
2

2
14@ 15@ HP_OUTL 6
43 HP_OUTL 6
@ @ 5
3

2
RING2_CONN 4 5
43 RING2_CONN 3 4
2 CLK 2 CLK For EMC 3
RING3_CONN 2
43 RING3_CONN PLUG_IN 1 2
43 PLUG_IN 1
TP_RIGHT Button TP_P6
TP_RIGHT Button TP_P6 USB20_P0 1
L14
2 USB20_P0_CONN ACES_50505-0184N-P01
3 DAT 3 DAT 1 2 ME@

USB20_N0 4 3 USB20_N0_CONN
4 3
1

B B
AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2

4 GND 4 GND SW3 SW4 @ CMM21T-900M-N_4P


A

A
A1

GND1

A1

GND1
EVQPLHA15_4P

EVQPLHA15_4P
1

DT4 DT5
1

5 TP-L 5 TP-L
GND2

GND2
B1

B1
B

B
2

14@ 15@
@ @
6 TP-R 6 TP-R
3

For 14" For 15"

PWR_LED# LED1 1 2 14@ R142 1 2 1.5K_0402_5%


LED 44 PWR_LED# +5VALW
1

D16 LTW-C193TS5
AZ5425-01F_DFN1006P2E2
1

LED4 1 2 15@
2

LTW-C193TS5
@
2

BATT_LOW_LED# LED2 1 2 14@ R143 1 2 470_0402_5%


44 BATT_LOW_LED# +3VALW
LTST-C193KFKT-LC
1

D18
AZ5425-01F_DFN1006P2E2
1

LED5 1 2 15@

A
LTST-C193KFKT-LC A
2

@
2

BATT_CHG_LED# LED3 1 2 14@ R144 1 2 1.5K_0402_5%


44 BATT_CHG_LED# +5VALW
LTW-C193TS5
1

D19
AZ5425-01F_DFN1006P2E2
1

LED6 1 2 15@ Title


Security Classification LC Future Center Secret Data
LTW-C193TS5
Issued Date 2013/08/08 Deciphered Date 2013/08/05 KBD/PWR/IO/LED/TP Conn.
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2

Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 45 of 59
5 4 3 2 1
A B C D E

+5VALW to +5VS +3VALW to +3VS

AP4800BGM AP4800BGM
VGS=10V, ID=9A, Rds=18m ohm VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V VGS=+-25V

+5VALW +5VS +3VALW +3VS


Q23 Q24

8 1 8 1
7 2 1 1 7 2 1 1
1 6 3 1 6 3
1 C124 5 C121 C122 C125 5 C123 C126 1
10U_0805_25V6K 10U_0805_10V6K 1U_0603_25V6M 10U_0805_25V6K 10U_0603_6.3V6M 1U_0603_25V6M

1
@ AP4800BGM-HF_SO-8 2 CD@ 2 CD@ @ AP4800BGM-HF_SO-8 2 CD@ 2 CD@

4
2 R145 2 @ R146
@ 470_0603_5% 470_0603_5%

2
R148 2 R147 1 5VS_GATE
5VS_GATE_R 1 2 5VS_GATE 2 R149 1 5VS_GATE 35
+20VSB 0_0402_5%
82K_0402_1% 150K_0402_5%
3VS_GATE_R 1 R150 2 2 R151 1 3VS_GATE 2 R152 1 +20VSB

1
1 D Q25 Q26 D 0_0402_5% 0_0402_5% @ 470K_0402_5%
R153 2 SUSP 2 @

1
C127 820K_0402_5% G G 1 D Q27 Q28 D
0.01U_0402_25V7K @ R154 2 SUSP 2
2 S 2N7002KW_SOT323-3 @ S 2N7002KW_SOT323-3 C128 820K_0402_5% G G

3
0.01U_0402_25V7K @
2 S 2N7002KW_SOT323-3 @ S 2N7002KW_SOT323-3

3
@

+5VALW

+3VALW Need short +3VALW_PCH VCCRTC +5VALW


2 2

1
J7 @
1 2
1 2

1
R155
100K_0402_5% R156 R157 +0.675VS
JUMP_43X79
@ 100K_0402_5% 100K_0402_5%
2

1
PCH_PWR_EN#_R R158 1 @ 2 100K_0402_5% PCH_PWR_EN#

2
LP2301ALT1G_SOT23-3 Id=3.2A R159
SUSP 47_0603_5%
34 SUSP
1

D
Q30 D Q29 3 1 @
PCH_PWR_EN 2
44,52 PCH_PWR_EN

2
G 1 1
C129 C130

G
2

3
@ S 2N7002KW_SOT323-3 .1U_0402_10V6-K 0.01U_0402_25V7K Q6A D D Q6B
3
1

@ @ 2 5 SUSP
2 2 35,44,55,56,57,58 SUSP# G G
R162
100K_0402_5% PCH_PWR_EN#_R 2N7002KDWH_SOT363-6 S S 2N7002KDWH_SOT363-6

4
2

1
C131
.1U_0402_10V6-K
@
2

3 3

+1.8VGS +0.95VGS +VGA_CORE


1

1
R171 R165 R166
470_0603_5% 470_0603_5% 470_0603_5%
@ @ @
1 2

1 2

1 2
Q31 D Q4 D Q5 D
PXS_PWREN# 2 PXS_PWREN# 2 PXS_PWREN# 2
23 PXS_PWREN# G G G

@ S 2N7002KW_SOT323-3 @ S 2N7002KW_SOT323-3 @ S 2N7002KW_SOT323-3


3

3
GPU Power Discharger

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 DC V TO VS INTERFACE


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 46 of 59

A B C D E
5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 2 D

Q25,+3V_PCH

V
V
AC A1
MODE VIN

V V
A2 A4 B5
3 +3V_PCH

V
PU301 PU904

V
B+
+3VALW
BATT BATT V 1
DPWROK_EC
V
MODE

V V V
B1
4
PCH_RSMRST#
EC 14
PM_DRAM_PWRGD
5 PBTN_OUT#

V
EC_ON PM_SLP_S3# PCH 15
PM_SLP_S4# H_CPUPWRGD CPU

V V
A3 B4 PM_SLP_S5#
PM_SLP_SUS# 6

V
CPU_PLTRST# 16
12
PCH_PWROK

V V
C C

B3 13
SYS_PWROK

V
ON/OFF V
NOVO

NVDD_PWR_EN
(DIS)
Vb
+VGA_CORE

V
11 VR_REDY SYSON 7 +1.35V
PU801
PU501

V
DGPU_PWROK
DGPU_PWR_EN
10 Va (DIS)

V
PU901 VR_ON +1.5VS_VGA

V
Q31
V

PU601

V
+CPU_CORE
+5VS

B B

V
Q32 +1.05VSP_VGA

V
SUSP#,SUSP 9 +3VS PU702

V
VGA

V
PU602
+1.5VS +3VS_VGA

V
Q27

V
PU502
+0.675V
8
SUS_VCCP PU701
V
+1.05VS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Power sequence Block


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 47 of 59
5 4 3 2 1
5 4 3 2 1

UL1 100M@ TL1 100M@ UV1 JET@ RV16 JET@ RV19 JET@ UV1 TOPAZ@ RV16 TOPAZ@ RV19 TOPAZ@ ZZZ4 14@ ZZZ5 15@

RTL8106EUL-CG TST1284A LF AMD Jet-LE GPU 0_0402_5% 0_0402_5% AMD Topaz-XT GPU 100_0402_1% 100_0402_1% PCB PN PCB PN
SA000060Q00 SP050008C00 SA000064J00 SD02800008J SD02800008J SA000062R00 SD03410008J SD03410008J DAZ0TG00200 DAZ0TH00200
LAN chip Transformer Jet-LE GPU Topaz-XT GPU PCB_MB

D D
UV3 H4@ UV4 H4@ UV5 H4@ UV6 H4@

Hynix_H5TC4G63AFR-11C Hynix_H5TC4G63AFR-11C Hynix_H5TC4G63AFR-11C Hynix_H5TC4G63AFR-11C


SA00005YL00 SA00005YL00 SA00005YL00 SA00005YL00

RV36 H4@

4.75K_0402_1%
SD03447518J

VRAM_Hynix_256M*16

UV3 M4@ UV4 M4@ UV5 M4@ UV6 M4@ RV33 M4@

Micron_MT41J256M16HA-093G Micron_MT41J256M16HA-093G Micron_MT41J256M16HA-093G Micron_MT41J256M16HA-093G 4.53K_0402_1%


SA000060I10 SA000060I10 SA000060I10 SA000060I10 SD03445318J

RV36 M4@
C C

2K_0402_1%
SD03420018J

VRAM_Micron_256M*16

UV3 S4@ UV4 S4@ UV5 S4@ UV6 S4@ RV33 S4@

Samsung_K4W4G1646D-BC1A Samsung_K4W4G1646D-BC1A Samsung_K4W4G1646D-BC1A Samsung_K4W4G1646D-BC1A 8.45K_0402_1%


SA000063F10 SA000063F10 SA000063F10 SA000063F10 SD000011R00

RV36 S4@

2K_0402_1%
SD03420018J

VRAM_Samsung_256M*16

B B

Board ID
ZZZ1 ZZZ2 ZZZ3
BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 Description Stuff Resistor

0 0 0 0 14" + Jet-LE sku RC107,RC108,RC109,RC123


*
Hynix Micron Samsug
0 1 0 0 15" + Jet-LE sku RC107,RC101,RC109,RC123 H4GX4@ M4GX4@ S4GX4@
* X7602912002 X7602912051 X7602912004

1 0 0 0 14" + Topaz-XT sku RC100,RC108,RC109,RC123 X76 BOM

1 1 0 0 15" + Topaz-XT sku RC100,RC101,RC109,RC123

A A

Security Classification
Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Virtual symbol


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 48 of 59
5 4 3 2 1
5 4 3 2 1

PCB Fedical Mark PAD


NH1 NH3 NH4 NH5
HOLEA HOLEA HOLEA HOLEA FD1 FD2 FD3 FD4 FD5 FD6

1
D D

pad_c2p3d2p3n pad_o2p3x2p8d2p3x2p8n pad_o2p3x2p8d2p3x2p8n pad_c2p3d2p3n

H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12


HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

H1
1

1
HOLEA

PAD_SHAPET5P0X6P0B7P0D2P3
Pad_ct8p0b9p0d2p8 Pad_ct8p0b9p0d2p8 pad_shapet8p8x8p0cb9p0d2p8 pad_shapet8p8x8p0cb9p0d2p8 PAD_CT6P5B5P0D4P0 PAD_CT6P5B5P0D4P0 PAD_CT6P5B5P0D4P0 PAD_CT6P5B5P0D4P0 pad_ct6p0d4p3 Pad_ct6p0b8p0d4p6
1

pad_SHT7P0X7P05BR10P65X10P3D2P8

C C

H21
H13 H14 H15 H16 H17 H18 H19 H20 H22 H23 H24 HOLEA
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

1
1

1
CHASSIS1_GND

pad_cb8p0d7p0 pad_ct6p0shapeb8p0x6p75d2p3 PAD_CT6P0shapeb10p04x10p0d2p8 pad_ct6p0b7p0d2p3 pad_shapet6p8x8p0cb8p0d2p5 PAD_ShapeT5P0X6P0-D PAD_shapeT5P0X6P0-U pad_ct5p5b6p0d3p3 pad_ct5p5b6p0d3p3 pad_ct5p5b6p0d3p3 pad_ct5p5b6p0d3p3 pad_ct5p5b8p0d2p5

B B
GP1 GP2 GP3 GP4 GP5 GP6 GP7 GP8
PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2
@ @ @ @ @ @ @ @
1

1
+VGA_CORE +3VS +5VALW +3VALW
1

1
C137 1 2 .1U_0402_10V6-K
@
1 1
C135 C136
.1U_0402_10V6-K .1U_0402_10V6-K
GP9 GP10 @ @
PAD_RT2P21X2P99 PAD_RT2P21X2P99 GP11 GP12 2 2 C138 1 2 .1U_0402_10V6-K
@ @ PAD_RT2P45X2P5 PAD_RT2P45X2P5 @
1

@ @
FFC CONN GROUND PAD
1

1
1

For EMC
A A

Security Classification LC Future Center Secret Data Title


Issued Date 2013/08/08 Deciphered Date 2013/08/05 Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 49 of 59
5 4 3 2 1
5 4 3 2 1

B+
+5VLP/ 100mA
Silergy
D
Silergy D
SY8208CQNC +5VALW/6A SY8868QMC
Adaptor Converter QFN10_2X2 +1.05VS/5A
FOR SYSTEM Switch Mode
EC_ON EN PGOOD ALW_PWRGD
PAGE 39 FOR VDDR
SUSP# EN PGOOD

+3VLP/ 100mA
Silergy
SY8206BQNC ANPEC
Converter +3VALW/ 5A
APL5930KAI-TRG_SO8
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD
+1.5VSP/1A
PAGE 39 LDO
FOR VDDR
SUSP# EN PGOOD

TI +1.35V/12A
TPS51716RUKR
SYSON S5 WQFN20_3X3 Silergy
SUSP# S3 +0.675VS/2A
C
TI Switch Mode SY8089AAAC_SOT23-5
C

FOR DDR PGOOD +0.95VSP_VGA/2A


BQ24737RGRR Switch Mode
Battery Charger FOR VGA
EN PGOOD
Switch Mode
PAGE 46 Onsemi
CPU Core/14A/32A
NCP81101MNTXG
QFN28_4X4 ANPEC
Switch Mode APL5930KAI-TRG_SO8
VR_ON +1.8VSP_VGA/1A
SMBus EN FOR CPU Core PGOOD VGATE
LDO
PGOOD_NB
FOR VGA
EN PGOOD

Battery Interisl
B
Li-ion ISL62771HRTZ B

4S1P/41WH TQFN40_5X5 +VGA_CORE/31A


VIDs
Switch Mode
NVDD_PWR_EN EN FOR GPU VDDC PGOOD VGA_PWRGD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Power Diagram


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 50 of 59
5 4 3 2 1
5 4 3 2 1

+3VL
VCCRTC
VIN

2
PL706 RTC_VCC PD703
JDCIN1 PF101 HCB2012KF-121T50_0805 RB751V-40_SOD323-2
1 APDIN 1 2 APDIN1 1 2
1 2

1
2 3 7A_24VDC_429007.WRML PL708
3

470P_0402_50V7K

470P_0402_50V7K
4 HCB2012KF-121T50_0805
4

1000P_0402_50V7K

1000P_0402_50V7K
5 1 2 JRTC1
5 ADAPTER_ID 44,53 PR9400 PD704

1
PC101

PC102

PC103

PC104
D ACES_50299-00501-003 For EMI request 2 1 1 2 BAT_D 2 1 D
ME@

2
1K_0603_5% RB751V-40_SOD323-2
@ @ FDK_ML1220-TT28 change to 1K SD01310018J

53 737_ACP 737_ACN 53

+1.05VS

PC1257 +1.05VS

1
2 1 PR9406
C 10K_0402_5% C

1
0.1U_0402_25V6 PC1256
+5VALW 0.1U_0402_25V6 PR9405 @
PC1258 @ 10K_0402_5% 5,44,52 H_PROCHOT#

2
2 1 PR368
@
PR369 2 1 H_PROCHOT#
PU1208 @

2
2

0.1U_0402_25V6 @ 10 9 2 1
PR367 CSN PROCHOT# 0_0402_5% @
0_0402_5% 1 8 0_0402_5%
@ CSP RESET PR9409 @
2 7 1 2
+3VALW
1

PR9403 VCC OVSET PR9410 +3VALW

1
1 2 3 6 1 2 2.94K_0402_1%
+3VALW ILIM UVSET
2

PC1259@ PC1260

GND

1
0.1U_0402_25V6 35.7K_0402_1% 2 1 4 5 24K_0402_1% PR9413 set OVP
EN TMER 10K_0402_1%
1

2
@ 0.1U_0402_25V6 PR9411
@ @

11

2
1

1
10K_0402_1%
1

@ @ PR9412 RT9553AGQW_WDFN10_3X3

2
PR9404 10K_0402_5% PR9407
PR9417 10K_0402_1% 124K_0402_1%

1
30K_0402_1% @ @
2

2
375K for 15uS
2

+3VALW
@ 124K for 5uS
@ @
1

PQ204 @ D
2
44 EC_ADAPTER G

2N7002KW_SOT323-3 S 45W current limit 2.8A


3

65W current limit 3.6A


B @ B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 DCIN / RTC


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 51 of 59
5 4 3 2 1
5 4 3 2 1

VMB2
VMB For KB930 --> Keep PU1 circuit
JBATT1 PF201 PL201 PH201 under CPU botten side : (Vth = 0.825V)
1 8A_24V_F1206HI8000V024T C8BBPH403025-1TAPING_2P
1 2 1 2 1 2 CPU thermal protection at 92+-3 degree C
2 3 EC_SMCA
BATT+ For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206
3 4 EC_SMDA Recovery at 56 +-3 degree C PH201, PR205,PR211,PQ201,PR208,PR212
4 5
5 6
6

1
7

1
7 8 PC201 PC202

100_0402_1%

100_0402_1%
GND1 9 1000P_0402_50V7K 0.01U_0402_25V7K

PR201

PR202

2
GND2
+5VLP
SUYIN_200082GR007G232ZR
+3VL

2
44,53 ADP_I

2
D D
PC203

1
0.1U_0603_25V7-M PR205
@ 4.42K_0402_1% PR206 PR207

1
@ 13.7K_0402_1% 21.5K_0402_1%
+3VS @ @

1
PU201

2
1 8 NTC_V_1
EC_SMB_CK1 44,53 VCC TMSNS1

2
2 7 OTP_N_002 2 1
GND RHYST1
EC_SMB_DA1 44,53

1
PR208 3 6 Turbo_V_1 PR209
5,44,51 H_PROCHOT# 100K_0402_1% OT1 TMSNS2
PR203 10K_0402_1% PH201
1 2 +3VALW @ 4 5 ADP_OCP_2 1 2 @

1
100K_0402_1% @ OT2 RHYST2 100K_0402_1%_NCP15WF104F03RC

2
D G718TM1U_SOT23-8 PR210

0_0402_5%

10K_0402_1%

2
PQ201 2ADP_OCP_1 57.6K_0402_1% PR213

PR211

PR212
G

OTP_N_003
PR204 2N7002KW_SOT323-3 @ 0_0402_5%
BATT_TEMP_IN 1 2
10K_0402_5%
BATT_TEMP 44,53 A/D S

1
@ @
@ PR214
1 2
MAINPWON 44
0_0402_5%

Turbo_V

44

44
NTC_V
PR215
1 2
44 PROCHOT#
0_0402_5% @
3

+3VALW
VMB2
+5VALW
+3VALW
JBATT2
1 PR109

2
1 2 PD305 0_0402_5%
2

2
C 3 EC_SMCA AZC199-02S.R7G_SOT23-3 PR105 +5VALW 2 1 H_PROCHOT# C
3 4 EC_SMDA @ PR108 PR110
4 10K_0402_1%
5 VMB2

UVP_1
BATT_TEMP_IN 221K_0402_1% 430K_0402_1% @
5 6
1

1
6 7 @ @

1
7 8 Reverse PD305 For EMI request

499K_0402_1%
1

3
GND1 9 @ PR106 D PQ101B
GND2
1

@ 1 2 5 2N7002KDWH_SOT363-6

PR103
PD306 G
1

SUYIN_200082GR007G232ZR 1.78M_0402_1%
S

4
@ @

2N7002KDWH_SOT363-6
2

12.5V PU202B PQ101A

6
1 PR9416 2 5 D @

P
2

1
AZ5215-01F_DFN1006P2E2 @ +_2 7 2 D
20K_0402_1% 6 O2 G 2 PQ205

180K_0402_1%
1
-_2

G
G 2N7002KW_SOT323-3
@

1
PC107 AS393MTR-G1_SO8 S

PR114

430K_0402_1%
220P_0402_50V7K

1
S

PR116
0.1U_0402_25V6

3
1
@

PC1268
2

2
@ @
@ 1 2
VIN
PR353

1
+5VALW 1M_0402_5%

1M_0402_5%
@

PR352
@
@
+3VALW +3VALW

2
VMB2
1

PC207
100K_0402_1%
2

100K_0402_1%

0.01U_0402_25V7K
PR221

PR223
2

PR228
1

B B
PR226 10M_0402_5%
1

280K_0402_1% 1 2 PR366
BATT_OUT 53
PR222 1 2
10K_0402_1% @ 0_0603_5%
8

1 2 PU202A @ +VSBP
2

3 D PQ996B PQ202
P

+_1 1 5 2N7002KDWH_SOT363-6 TP0610K-T1-E3_SOT23-3


2 O1 G PJ201
1

-_1
G

JUMP_43X39
1

PC108 PR224 AS393MTR-G1_SO8 S 3 1 1 2


B+ +20VSB
4

49.9K_0402_1% 1 2
0.1U_0402_25V6
+3VALW

0.22U_0603_25V7K
2

1
@

100K_0402_1%
2

2
PR216

PC204
@
PC205
2
100K_0402_1%

PR225 0.1U_0603_25V7-M

1
100K_0402_1%
PR227

2
1 2 +3VL
PR217
1
VSBP_2 2 VSBP_3
1
2

2N7002KDWH_SOT363-6

PR230 PR229 PQ996A


6

100K_0402_1% 10K_0402_1% D 22K_0402_1%


1 2 2
44 BATT_LEN# G
1

S @ PR219
1

1
0_0402_5% PQ203 D
1 2 VSBP_1 2
54 ALW_PWRGD G

1 S 2N7002KW_SOT323-3

3
PR220 PC206
1 2 1U_0402_6.3V6K
2

44,46 PCH_PWR_EN
1K_0402_1% @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 BATTERY CONN/OTP


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 52 of 59
5 4 3 2 1
5 4 3 2 1

B+ Charge Option() bit[8]=1

1000P_0402_50V7K

1000P_0402_50V7K
P2 P3

0.1U_0402_25V6

0.1U_0402_25V6
1

1
For EMI request

PC105

PC106

PC110

PC111
PQ301 PQ302
AO4407AL_SO8 SI4483ADY-T1-GE3_SO8 PR301

2
8 1 1 8 0.01_1206_1%
7 2 2 7 PL707
6 3 3 6 1 4 1 2 PQ303
VIN 5 5 AO4407AL_SO8 BATT+
2 3 C8BBPH403025-1TAPING_2P 1 8

0.1U_0603_25V7-M
2 7

2
3 6

PC109
PC301 PC302 PC303 5

2200P_0402_50V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
D D
PQ304 1 2 10U_0805_25V6K 10U_0805_25V6K

1
1

2
@ @

PC304

PC305

PC306

PC307
0.1U_0603_25V7-M

4
1
PR302 LTA044EUBFS8TL_UMT3F-3 100P_0402_50V8J For EMI request DISCHG_G
3

2
200K_0402_5% PR303 @

1
200K_0402_1%

PC308
PR304
2

1
2 @ 1 2 VIN

2
1P2_G2

47K_0402_1%

2ACOFF-1
2
51 737_ACP 51 737_ACN

1SS355_SOD323-2
PR305

DISCHG_G-1
10K_0402_1%
1

2
PD301
P2-1 PR306

1
2 200K_0402_1%

1
PQ305
LTC015EUBFS8TL_UMT3F-3 PR356

1
20K_0402_1% PC310 PC311 PQ308B
P2_G1

P2 2 1 2 1 2N7002KDWH_SOT363-6
3

3
D PD302
2

0.1U_0603_25V7-M 0.1U_0603_25V7-M 5PACIN_N 1 2 PACIN_P


2N7002KDWH_SOT363-6

G
6

PQ307A D PR308 PC312


1SS355_SOD323-2
6

2 PR307 D PQ990A 2 1 2 1 BQ24737_VDD S

4
G 68K_0402_1% 2 BATT_OUT 52 10_1206_5%
G PC314 0.1U_0603_25V7-M PC315

6
S 1U_0603_25V6M 1U_0603_25V6M D

1M_0402_5%
1

1
S 2N7002KDWH_SOT363-6 2 1 737_VCC 1 2 PC313 2 PACIN

PR347
1

0.1U_0603_25V7-M G
VIN

2
P2-2

PD303 S PQ308A

1
2 RB751V-40_SOD323-2 AO4466L_SO8 2N7002KDWH_SOT363-6
2 1
3

5
6
7
8
PR309 D PQ307B PR310

20

14
2

3
PACIN 1 2 5 2N7002KDWH_SOT363-6 390K_0402_1% PQ309
G

VCC

ACN

GND
CMPOUT
ACP
PACIN_G

47K_0402_1%
1

C S PR311 PR312 PC317 C


4

1 2 737_ACDET 6 17 BST_CHG 1 2 2 1 4
59K_0402_1% ACDET BTST 2.2_0603_5%
PC316 0.047U_0603_16V7K
1 2 ACPRN 5 16
ACOK REGN

3
2
1
0.1U_0402_25V6 PR313 0_0402_5% PU301
6

PR314 PQ998A D 44,52 EC_SMB_CK1 1 2 737_SCL 9 18 DH_CHG PR316


1 2ACOFF-1 2 SCL HIDRV 0.01_1206_1%
44 ACOFF G PR315 0_0402_5% BQ24737RGRR_VQFN20_3P5X3P5 PL302 BATT+
0_0402_5% 44,52 EC_SMB_DA1 1 2 737_SDA 8 19 LX_CHG 1 2 CHG 1 4
S SDA PHASE
1

4.7UH_PCMB063T-4R7MS_5.5A_20% 2 3

5
6
7
8

1
44,52 ADP_I ADP_I 7 15
1

PR349 2N7002KDWH_SOT363-6 IOUT LODRV PQ311 PR317

CMPIN
2

1M_0402_5% 4.7_1206_5%

SRN
BM#

SRP
PC318 ILIM 21 AO4466L_SO8

10U_0805_25V6K

10U_0805_25V6K
PAD @
100P_0402_50V8J
1

1
DL_CHG 4
2

11

10

SRN_1 12

SRP_1 13

PC319

PC320
16251_SN

2
BM#

PR318 @

3
2
1
3

PQ990B D 10K_0402_5% PC321


BATT_OUT 5 1 2 1 680P_0402_50V7K

10_0603_5%
6.8_0603_5%

+3VS
1

G @
PR320

2
PR321
PR319

2N7002KDWH_SOT363-6 S 2 1 737_ILIM
4

2
2

PR345 100K_0402_1% 1
316K_0402_1%

0_0402_5% PC324
2

@ 0.1U_0603_25V7-M
2

PC322 @
PR324
1

1 2 737_SRP

0.1U_0603_25V7-M
1

B B
737_SRN
2

+3VALW PC323
44,52 BATT_TEMP 0.1U_0603_25V7-M
1

+3VALW VIN

BQ24737_VDD
1

PR322
750_0603_1% PR323 PR327

1
1M_0402_5% 1 2
ACIN 44
@ PR325 PR326
2

47K_0402_1% 10K_0402_1% 10K_0402_1%


2

2
PACIN

1
PQ998B PR333
2

3
D PQ995A D 12K_0402_1%
PR336 2 ADAPTER_ID_ON#_G ACPRN 5
0_0402_5% G G

2
S 2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6 S
1

4
@

ADAPTER_ID 44,51
1

D
680P_0402_50V7K

5 ADAPTER_ID_ON# 44
1

PR328 G
PD304 1M_0402_5%
1
0.1U_0402_25V6

@ S PQ995B @
PC1267

A AZ5425-01F_DFN1006P2E2 A
2

4
1

2N7002KDWH_SOT363-6
PC1266
2

@ PR334
0_0402_5%
2

ACPRN 1 2 ACIN#
ACIN# 8,44
@

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 CHARGER


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Friday, December 20, 2013 Sheet 53 of 59
5 4 3 2 1
5 4 3 2 1

D D

B+ PU904
PJ302
2 1
1.5A +3V_VIN 7 2 +3V_PWRGD
2 1 EN2 PG

1M_0402_5%
0.1U_0402_25V6

10U_0805_25V6K
1

SY8206BQNC_QFN10_3X3
PC1048 +3VALW

PR335
JUMP_43X79 8 6 +3VBS 1 2

PC1046

PC1047
IN BS
4A

2
@ 0.1U_0603_25V7-M PL303 PJ303

2
9 10 +3VLX 1 2 +3VALW_P 2 1
GND LX 2.2UH_PCMB063T-2R2MS_8A_20% 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PR337 3V_GND

1
1 2 +3VALW_EN 1 4 +3VALW_P JUMP_43X79
44 EC_ON EN1 OUT PR338

PC1049

PC1050

PC1051

PC1052
0_0402_5%
100mA +3VLP 4.7_1206_5%
@

2
+3VALW_FB 3 5 @
FB LDO

1 2
4.7U_0603_6.3V6K
1

1
@ PC1054 PR339 PC1106

PC1055
0.1U_0402_25V6 1M_0402_5% 1000P_0402_50V9-J
2

2
@
@ PTP1
2

PAD
3V_GND
3V_GND 3V_GND
@

PC1057
PR341
1 2 1 2

PJ1 0.01U_0402_25V7K 1K_0402_1%


1 2
+3VL
C JUMPER +3VLP change 470P to 10nf for soft start time 2ms C
PJ304
@ 2 1
2 1
3V_GND
JUMP_43X39

+3VALW

2
PR342
100K_0402_5%

PR343 @

1
+3V_PWRGD 1 2
ALW_PWRGD 52
B+ PU905
0_0402_5% @

PJ305 PR344
2 1
2.5A +5V_VIN 8 2 +5V_PWRGD 1 2
2 1 IN PG
10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1

SY8208CQNC_QFN10_3X3

PC1061 0_0402_5% @ +5VALW


PC1060

PC1059

JUMP_43X79 9 6 +5VBS 1 2
PC1058

GND BS
5A
2

@ PC1062 0.1U_0603_25V7-M PL304 PJ306


1 2+5VVCC 5 10 +5VLX 1 2 +5VALW_P 2 1
VCC LX PR351 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PR346 1U_0603_25V6M 0_0402_5% 3.3UH_PCMB063T-3R3MS_6.5A_20%

1
EC_ON 1 2 5V_GND +5VALW_EN 1 4 2 1+5VALW_P JUMP_43X79
EN OUT PR340

PC1063

PC1080

PC1090

PC1091
100mA +5VLP
B 4.7_1206_5% B
0_0402_5% @

2
+5VFB 3 7 @
FB LDO
1 2
1M_0402_5%

4.7U_0603_6.3V6K
1

1
1

PC1107
PR348

PC1070

@ PC1069 1000P_0402_50V9-J
2

0.1U_0402_25V6 @
2

5V_GND

5V_GND 5V_GND

PC1072 PR350
1 2 1 2

6800P_0402_25V7-K 1K_0402_1%
PJ2
1 2

JUMPER

@ 6800pf soft start 2ms


5V_GND 47nf soft start 7ms

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 PWR_3VALW/5VALW


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 54 of 59
5 4 3 2 1
A B C D

1 1

1
PC1102 @
0.1U_0402_10V7K

2
1k for 500K
12k for 670K PR9350 0_0402_5%
+3VALW @ 1 2 SUSP# 35,44,46,56,57,58
1.35V_GND 1.35V_GND PR377 0_0402_5%
2 1
CPU_DRAMPG_CNTL 5 2A

S3_1.35V
10K_0402_1%
PJ309

PR375
PR376 0_0402_5% 1.35V_B+ 2 1

63.4K_0402_1%
2 1 B+

1
2 1

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
SYSON 44

1
PR9415

PC1064
PR9414

1
S5_1.35V

PC857

PC856
1K_0402_1% JUMP_43X79

1
2 1

2
44 VDDQ_PGOOD
@

2
PC1101 0.1U_0402_10V7K @
@

5
20

19

18

17

16
PU1207

AON6414AL_DFN8-5
PGOOD

MODE

TRIP

S3

S5
21 PR380 PC1081
PAD

PQ997
0_0603_5% 0.1U_0603_25V7-M
1 15 1
BST_1.35V 2 2 1 4 PJ317
VTTSNS VBST 2
2 1
1 12A
PR381 0_0402_5%
2

+1.35V
2A 2
VLDOIN DRVH
14 2 1 UG_1.35V PL307 @ JUMP_43X118 2

2A

3
2
1
0.47UH_PCMC063T-R47MN_17.5A_20% PJ316
22U_0805_6.3V6M

22U_0805_6.3V6M

+0.675VSP 3 13 LX_1.35V 1 2 2 1
VTT SW 2 1
+1.35V
1

1
PC1099

PC1100

TPS51716RUKR_WQFN20_3X3
@ JUMP_43X118

22U_0805_6.3V6M
1

1
4 12
2

VTTGND V5IN
+5VALW

1
PQ43 PR378 + PC1105

1
4.7_1206_5%

PC1053
@ @ 330U_2.5V_M

VDDQSNS

AON6554_DFN
5 11 PC1104

2
VTTREF DRVL 1U_0603_25V6M @ 2

2
REFIN
1

PGND
VREF

1.35V_SN
GND
+VTT_REFP PC1264 LG_1.35V 4
1U_0402_6.3V6K
2

10

1
VREF

3
2
1
PR374
30K_0402_1%

1.35V_GND PC1103
2

PJ315 1000P_0402_50V9-J
REFIN

2
2 1 @
+0.675VSP 2 1 +0.675VS
PC1265 1.35V_GND
1

0.1U_0402_25V6
JUMP_43X79
1

@ 1.35V_GND
1
1

PR379
+1.35VP
PC1263 93.1K_0402_1%
Vout=1.367V
2

0.01U_0402_25V7K
2

3 3

1.35V_GND 1.35V_GND

PJ4
1 2

JUMPER

@
1.35V_GND

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 1.35VS/+0.675VS


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 55 of 59
A B C D
A B C D

1 1

+5VALW

+3VALW
+1.5VSP +1.5VS

1
PC615 500mA
1U_0603_25V6M

2
2
500mA 2

PU602
PJ604 6 PJ603
2 1 5 VCNTL 3 2 1
2 1 9 VIN1 VOUT1 4 2 1
4.7U_0603_6.3V6K

VIN2 VOUT2
1

1
PR614
JUMP_43X39 1 2EN_1_5VSP 8 JUMP_43X39 @
PC616

35,44,46,55,57,58 SUSP# EN

1
7 2 PR613

GND
2

@ 0_0402_5% POK FB 21.5K_0402_1% PC728 PC617

1
220P_0402_50V7K 10U_0603_6.3V6M

2
PC618 APL5930KAI-TRG_SO8

1
.1U_0402_10V6-K @

1
@ PR616
100K_0402_5%

1
@
PR615

2
24K_0402_1%

2
+3VS
VFB=0.8V

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 +1.5VS/+1.8VGS


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 56 of 59
A B C D
5 4 3 2 1

+3VS

2
PR701
10K_0402_5%

1_05VS_PG1
5A

22U_0805_6.3V6M
22U_0805_6.3V6M

9
PJ704 PU701 PL701 PJ702 +1.05VS
2 1 1_05VS_PVIN 1 2 1_05VS_LX 1 2 2 1

PG
+5VALW

0.1U_0402_25V6
2 1 VIN LX1 2 1

1
PC1066
D D
5 0.68UH_PCMC063T-R68MN_15.5A_20%

PC702

PC701

1
JUMP_43X79 LX2 JUMP_43X79

2
6 PR703
@ LX3 4.7_1206_5%
@ @

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
4 10 @ 1
@ PR704 EN OUT

PC703

PC704

PC705

PC706
1SNB_1_05VS 2
1 2 1_05VS_EN + PC707

2
35,44,46,55,56,58 SUSP# 0_0402_5% 8 7 330U_D2_2V_Y

GND
SS FB

2
PR994 2 @

47K_0402_5%
1 2

PR705
44 SUS_VCCP

3
1

1
SY8868QMC_QFN10_2X2
0_0402_5% PC709 PC711
.1U_0402_10V6-K 0.01U_0402_25V7K PC710
1

2
@ 680P_0402_50V7K

2
@ @

VFB=0.6V PR706
1_05VS_FB 2 1
75K_0402_1%

1
PR707
100K_0402_1%
2 1 PC712
220P_0402_50V7K

2
+0.95VSP_VGA

C 1A 2A C
PX@
PU702
PJ703 PL702 PJ709
+3VALW 2 1 1.05VMP_VIN 4 3 1.05VMP_LX 1 2 2 1
+0.95VGS
2 1 IN LX 1UH_PH041H-1R0MS_3.8A_20% 2 1
JUMP_43X79 2 PX@ JUMP_43X79

68P_0402_50V8J
22U_0805_6.3V6M

22U_0805_6.3V6M

GND
1

1
59K_0402_1%
4.7_1206_5%

1
5 1
PC713

PC714

PR710

PR711
@ FB EN @

PX@

PC715
2

2
SY8089AAAC_SOT23-5

22U_0805_6.3V6M

22U_0805_6.3V6M
2

1
PX@
FB=0.6Volt
PX@ PX@ @

PC716

PC717
1

2
PC718
PD701 680P_0402_50V7K

2
1 2 @ @

PR712
2 1 EN_1.05VMP 1.05VMP_FB
4,23,58 PXS_PWREN 47K_0402_5% PX@ PX@

1
PX@
1

PR714
1

PR713 PC719 100K_0402_1%


1M_0402_5% .1U_0402_10V6-K PX@
PR715
2

2
SUSP# 2 1 PX@ PX@
2

0_0402_5%
@

B B
+5VALW

+3VALW
+1.8VGSP +1.8VGS
1

PC623 500mA
1U_0603_25V6M
2

500mA
PX@ PU603
PJ606 6 PJ605
2 1 1.8VGS_VIN 5 VCNTL 3 2 1
2 1 9 VIN1 VOUT1 4 2 1
4.7U_0603_6.3V6K

VIN2 VOUT2
15K_0402_1%

220P_0402_50V7K

JUMP_43X39 JUMP_43X39
PC729 @

PX@ 8
PC619

PR9418

22U_0805_6.3V6M
1

1
EN
PX@

7 2 @
GND
2

@ POK FB @ PC624

PC720
10U_0603_6.3V6M
2

2
1

PC625 APL5930KAI-TRG_SO8 PX@


1

PD705 .1U_0402_10V6-K PX@


1
2

1 2 PR621
1

100K_0402_5%
12K_0402_1%
PR9419

PR722 @
PX@
2

PXS_PWREN 2 1 EN_1.8VMP
120K_0402_5%
2

PX@
+3VS

PR723
SUSP# 2 1
0_0402_5%
@

A A

VFB=0.8V

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 +1.05VS/+1.05VS_VGA


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. G(Haswell)
Date: Tuesday, December 17, 2013 Sheet 57 of 59
5 4 3 2 1
5 4 3 2 1

+VGA_B+
D D

PJ707
1.5A 2
2 1
1
B+
JUMP_43X79

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
@

1
PC1224

PC1225

PC1226
5

AON6414AL_DFN8-5

2
1

33K_0402_5%
1

1
0_0402_5%

10K_0402_5%

10K_0402_5%
PR9344

PQ991
PR9342

PR9398

PR9399
PX@ PX@ PX@

@
VGA_UGATE1 4
+VDDIO_GPU

2
2

2
PX@ PX@ PX@
PX@

3
2
1
PR9329
1

1
PC730 PC1269 PL704
.1U_0402_10V6-K 1U_0402_6.3V6K 2 1 VGA_PHASE1 1 2 +VGA_CORE
@ PX@
2

2
0_0402_5% 0.36UH_PCMB063T-R36MS_20A_20%

5
PR9369 PC1228 PQ992 PX@

40

39

38

37

36

35

34

33

32

31

1
PU1204 VGA_BOOT1 1 2 1 2

AON6554_DFN
PR9371

ISUMP_NB

ISUMN_NB

VSEN_NB

FB_NB

COMP_NB

PGOOD_NB

LGATE_NB

PHASE_NB

UGATE_NB

BOOT_NB
+3VGS

330U_D2_2V_Y

330U_D2_2V_Y
2.2_0603_5% 0.22U_0603_16V7K 4.7_1206_5% 1 1

2
PX@ PX@ @ PR9396
1

PC1229

PC1230
PR9355 PX@ 100K_0402_1% VGA_LGATE1 4 10_0402_1% + +

2
1 2 1 30 VGA_BOOT2 PR9372
NTC_NB BOOT2 PX@
PR9397 PR9359 PX@ 100K_0402_1% PR9373 3.65K_0402_1%

1
2.2K_0402_1% 1 2 2 29 VGA_UGATE2 10K_0402_1% 2 2

1
IMON_NB UGATE2

1
PX@ PC1231 PX@
2

3
2
1
3 28 VGA_PHASE2 PX@ 680P_0402_50V7K PX@

1
20 GPU_SVC SVC PHASE2

VSUM+

VSUM-
@

2
PR9357 2 PX@ 1 0_0402_5% VRHOT_L 4 27 VGA_LGATE2

ISEN1
PX@ PX@
20 GPU_HOT# VR_HOT_L LGATE2 PR9360
C C
5 26 62771_VDDP 2 1
20 GPU_SVD SVD VDDP +5VS
PR9362 PX@
6 25 62771_VDD 1 2 0_0402_5% +VGA_B+
+VDDIO_GPU VDDIO VDD
ISL62771HRTZ_TQFN40_5X5 1_0603_5%
7 24 VGA_LGATE1
20 GPU_SVT SVT LGATE1

1
4,23,57 PXS_PWREN
PR9364 2 PX@ 1 150K_0402_5% 8
ENABLE
PX@
PHASE1
23 VGA_PHASE1 PC1222 PC1223 1.5A
1U_0603_25V6K 1U_0603_25V6K

2
PR9365 2 PX@ 10_0402_5% 9 22 VGA_UGATE1 PX@ PX@
PD801 19 GPU_PWROK PWROK UGATE1
1

10U_0805_25V6K
@

10U_0805_25V6K
0.1U_0402_25V6
1 2 PC727 VGA_IMON 10 21 VGA_BOOT1
44 VGA_IMON IMON BOOT1
.1U_0402_10V6-K
2

1
PC1238

PC1239

PC1236
AON6414AL_DFN8-5
PGOOD
ISUMN
ISUMP

COMP
ISEN2

ISEN1

VSEN
RB751V-40_SOD323-2 PX@
NTC

RTN

FB

TP

2
PR9328 PR9368 PX@
2

PQ993
2 1 2 1
+3VGS
11

12

13

14

15

16

17

18

19

20

41
2

35,44,46,55,56,57 SUSP# VGA_UGATE2 4 PX@ PX@


0_0402_5% @ PR9295 PR9367 PC1227 100K_0402_1% PX@
1000P_0402_50V7K

62771_COMP
133K_0402_1%

VGA_VSS_SEN
1.91K_0402_1%

VGA_CORE_SEN
1

62771_FB
PX@ PX@ PX@
1

VGA_PWRGD 9,19,44
PX@
1

3
2
1
+3VGS PL705
VGA_PHASE2 1 2

0.36UH_PCMB063T-R36MS_20A_20%

5
PR9387 PC1247 PX@ PQ994 PX@

1
VGA_BOOT2 1 2 1 2

AON6554_DFN
PR9388

330U_D2_2V_Y

330U_D2_2V_Y
2.2_0603_5% 0.22U_0603_16V7K 4.7_1206_5% 1 1

2
PX@ @

PC1248

PC1249
62771NTC VGA_LGATE2 4 PR9395 + +

2
10_0402_1%

2
+5VS
PX@

2
PR9392 2 2

1
1
PR9374 2 @ 1 10K_0402_5% PX@ PC1250 PR9391 3.65K_0402_1% @

3
2
1
B B
680P_0402_50V7K 10K_0402_1% PX@

VSUM-
@ PX@

VSUM+ 1
PX@

ISEN2 1
ISEN2

ISEN1
1

PC1232 PC1233 PC1234 PX@


PR9377 2 @ 110K_0402_5% 0.22U_0402_10V6K 1 2
0.22U_0402_10V6K PX@ PC1235 PX@ PR9378 PX@ PC1237 PX@ PR9379 @
2

PX@ 0.1U_0402_25V6 PR9394 PX@ 1 262771_FB_2 1 2 1 2 1 2


VSUM- 1 2
100P_0402_50V8J 499_0402_1% 47P_0402_50V8J 32.4K_0402_1%
1

1.3K_0402_1%
PX@ PR9380 PR9381 PR9382 PX@ PR9385 PX@ PC1242 PX@
PR9366

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
2.61K_0402_1% 3.9_0402_1% PR9384 @ PC1241 @ 1 2 1 26277_FB_11 2
1

330P_0402_50V8J

1 2 PX@ PX@ 2 1 1 2
1
PC1240

PR9383 1K_0402_1% 54.9K_0402_1% 150P_0402_50V8-J


2

1
10K_0402_1%_TSM0A103F34D1RZ

PC1079

PC1094

PC1093

PC1092

PC1183

PC1182

PC1150

PC1151

PC1184

PC1185
93.1K_0402_1% 11K_0402_1% 10K_0402_5% 0.22U_0402_10V6K
2
0.047U_0402_25V7K

0.047U_0402_25V7K

62771NTC PX@
2
2

PR9386
2

2
1

1
PX@
PH906

PC1246

PC1262

PX@ 2K_0402_1%
PH905
@
6277_NTC_1 2 1 @ PX@ PX@ @ PX@ @ PX@ @ PX@ PX@
2

1 6277_FB_3
1

470K_0402_5%_TSM0B474J4702RE PX@ PX@


1

PX@ VSUM+
PR9370
10.5K_0402_1%
PX@
20 VGA_CORE_SEN
1
2

330P_0402_50V8J

PC1244
1
PC1255

680P_0402_50V7K
2

@
2

A PX@ A

20 VGA_VSS_SEN
1

PC1251
0.1U_0402_25V6
2

PX@

Security Classification
Security Classification LC Future Center Secret Data Title
Issued Date 2013/08/08 Deciphered Date 2013/08/05 PWR-VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Friday, December 20, 2013 Sheet 58 of 59
5 4 3 2 1
5 4 3 2 1

CORE_GND CORE_GND

470P_0402_50V7K
1

1
PR9334

PC1157

220K_0402_5%_TSM0B224J4702RE
27.4K_0402_1%

2
2
1 PR9337 2 B+
44 VR_IMVP_IMON
165K_0402_1%

68P_0402_50V8J
330P_0402_50V7K
1

1
75K_0402_1%

2
PR9346

PH901
PR9338

PC1159

PC1158
2 1
+5VALW 0_0402_5%

68U_25V_M
1

1
@

2
PJ708 +

PC989
1
D D
PR9335 JUMP_43X79
2

2
1 2 CPU_PH
@ 3A

2
140K_0603_1%

2 PR9401 1CPU_CORE
CPU_B+ @

1 CSCOMP

CPU_CSREF
CORE_GND
1

1
PC1065 PC100 PC99 PC98 PC113

68U_25V_M
10_0402_1%
+

CSCOMP
PR9333

PC988
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
PR9345 16.5K_0402_1%

2
CSSUM

2
2 @ 1 CORE_GND PR9340

0.1U_0402_25V6
1
0_0402_5% 102K_0402_1% PC1171 2

2
1000P_0402_50V7K

5
PQ40

CPU_CSREF

AON6414AL_DFN8-5
1
PR3 PC1153 PC1181 PC1172 CORE_GND @

2
49.9_0402_1% 330P_0402_50V7K 10P_0402_50V8J CORE_GND 2.2U_0603_6.3V6K
1 2 1 2 1 2 PR365
PR9341

2
1 2 CPU_HG_R 1 2CPU_HG 4 CPU_CORE
+5VALW

1
PR9330 PC1152 @ PR2 PR1 0_0402_5% 0_0603_5%
1K_0402_1% 2200P_0402_50V7K 4.02K_0402_1% 16.2K_0402_1% PR9332 32A

21
20
19
18
17
16
15
1 2 1 2 1 2 69.8K_0402_1% PL9

3
2
1
1 2 CPU_PH 1 2

PVCC
IOUT

CSREF
CSCOMP

IMAX
ILIM

CSSUM
CORE_GND

2
PR362
0_0402_5% PC1156 0.22UH_SPS-06CZ-R22M-V1_23A_20%

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
5

1
1 2 22 14 0.01U_0402_25V7K PQ39

1
23 ROSC VBOOT 13 TSENSE 1 2 PR617
COMP TSENSE CORE_GND

AON6554_DFN
24 12 CPU_LG 4.7_1206_5%

PC1073

PC1088

PC1089

PC1170

PC1148
25 FB LG 11

2
2 1 26 DIFFOUT PGND 10 CPU_PH
12 CPU_VSS_SENSE

2
27 VSN SW 9 CPU_HG_R PC97 CPU_LG 4
2

PR9402 PC1154 28 VSP HG 8 1 PR80 2 1 2

VR_HOT#
VCC BST

VR_RDY
ENABLE

ALERT#
C 0_0402_5% 1000P_0402_50V7K 2_0603_5% @ @ @ @ C

1
VRMP
29

SCLK
0.22U_0603_25V7K PC621

SDIO
1

GND 680P_0402_50V7K
10 CPU_VCC_SENSE

3
2
1
PR9145

2
PC1254 @ 1 2 PU908
+5VALW

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1
2
3
4
5
6
7
1 2 NCP81101MNTXG_QFN28_4X4
1

1
2.2_0603_5% PC242 CORE_GND
560P_0402_50V7-K 1U_0603_25V6M

PC1164

PC1149

PC1177

PC1139

PC1160

PC1116
PR9343 2 @ 1 PR9331 For EMI request
44 EC_VR_ON
2

2
0_0402_5% 1 2
CPU_B+
PR9146
2 1 CORE_GND 1K_0402_1% @
10 CPU_VR_ON
0_0402_5% 1 @ @
1

PC1155
PC620 0.01U_0402_25V7K
2

+1.05VSR .1U_0402_10V6-K
2

@ +3VS

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
2

CORE_GND CORE_GND 1

1
PR9265
499_0402_1% PR47

PC1167

PC1162

PC1165

PC1163

PC1174

PC1173
10K_0402_5%

2
1

44 VR_HOT# @
VR_CPU_PWROK 10,44
10 CPU_SVID_DAT

100K_0402_1%_TSM0B104F4251RZ
10 CPU_SVID_ALERT# PR9147
TSENSE 2 1
CORE_GND
10 CPU_SVID_CLK
0_0402_5% 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

.1U_0402_10V6-K
1

1
PR9098 PR31 + PC708

1
PR60 220U_D2_2.5VY_R6M

PC1176

PC1178

PC1180
1

75_0402_1% 130_0402_1% PR9339


PC622

PH902

2
+1.05VS +1.05VSR 54.9_0402_1% PC626 @ 2 3
59K_0402_1%
2

@ 10U_0603_6.3V6M
2

B B
2

2
PR9148 PR9149 @
2 1 2 1
0_0402_5% 0_0402_5%
PJ3
PR9347 PR9348 1 2
2 1 2 1
0_0402_5% 0_0402_5% JUMPER
@ @
@
CORE_GND

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 PWR_CPU Core


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ACLU1&ACLU2
Date: Thursday, December 19, 2013 Sheet 59 of 59
5 4 3 2 1

You might also like