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ABSTRACT
In this paper we have proposed efficient designs of major concern for low-power
power chip designers since it
low power high speed D-latch
latch designed using stacked was accounted for more than 90% of the total power
inverter and sleep transistor based on 32nm CMOS supplied to chip. As a result, many earlier proposed
technology. We have designed and simulated these techniques, such as frequency and voltage scaling,
circuits in HSpice simulation tool. In this simulation dedicated on dynamic power reduction. Although,
Alth as
we have modified W/L ratio of each transistor in the the feature size reduces, e.g., to 0.09µ and 0.065µ,
circuit. We have taken power supply of 0.9V. We static power becomes a challenge for current and
have calculated average power consumed propagation future technologies.
delay and power delay product.
Designers have limited scope of control. The designer
Keywords: CMOS, Clock, Latch, Power Delay cannot modify the threshold voltage at will. Vt to a
Product, MOSFET high degree or extent is dependent on doping of the
substrate material, the thickness of the gate oxide and
1. INTRODUCTION the potential in the substrate. The physical parameters
that cannot be modified by the circuit designer are
In past few decades an unprecedented growth is
decided by the process designers are doping in the
experienced by electronics industry and the credit
substrate
trate and the oxide thickness. The designer can
goes to the intelligent use integrated circuits in
willfully vary the substrate potential thereby
computation purpose, telecommunications and
influencing the Vt via a process known as the body
consumer electronics.
ctronics. We have come a long way
effect. It is risky to tamper with substrate potential,
since the single transistor era in 1958 to the existing
and for digital design the majority connection is
ULSI (Ultra Large Scale Integration) systems with
invariably
riably shorted to VSS in case of NMOS and VDD
approximately 50 million or more transistors on a
in case of PMOS.
single chip. For the modern CMOS features sizes 𝝁𝜺 𝑾
(e.g., 90nm and 65nm),
5nm), a dominant concern for VLSI equation = 𝒐𝒙
As can be seen from the equation,𝜷 , the
𝒕𝒐𝒙 𝑳
circuit designers has become leakage power designer has no control over the coefficient
𝝁𝜺𝒐𝒙
, as
dissipation. International technology roadmap for 𝒕𝒐𝒙
semiconductors (ITRS) has reported that leakage the carrier mobility (µn or µp) is constant in
power dissipation may dominate total power semiconductor (only influenced
fluenced by process), εox is a
consumption. Power consumption in CMOS consists constant physical parameter and tox is determined by
of static and dynamic components. Static power is process. Thereby, the designer is left with two
consumed irrespective of transistor switching and dimensional parameters, W and L. In general W and L
dynamic power is consumed while transistors are in can be varied together at will by the chip designer, on
switching condition. Dynamic power consumption condition that they
hey remain within the design rule for
was earlier (at 0.18µ technology and above) the only the minimum dimensions of any feature. Nevertheless
4. SLEEP TRANSISTOR
Fig-4: D-latch
latch based on stacked inverter
When clock (CLK) is high, M3, M4 conducts and Fig-5: Output for D-latch
latch (stacked inverter)
input D passes to the output. This output also goes to
M7, M8, M9, M10 and gets inverted. Now if the clock
is low, inverted data switches on M11, M13 (if D =
‘1’) & M12, M14 (if D = ‘0’) and keeps the previous
data at the output terminal. This
his is how the circuit
Fig-6: D-atch
atch based on sleep transistor
@ IJTSRD | Available Online @ www.ijtsrd.com | Volume – 2 | Issue – 4 | May-Jun 2018 Page: 1418