SEQUENTIAL LOGIC SEQUENTIAL LOGIC

UNIT 6: SEQUENTIAL LOGIC 6.1 INTRODUCTION TO LATCH

Sequential switching circuits have the property that the output depends not only on the
INTRODUCTION
present output but also on the past sequence inputs, In the effect, these circuits must be
able to remember something about the past history of the inputs in order to produce the
Sequential logic is a new type of digital circuitry because it is controlled by and is used
present output. Latches and flip-flops are memory devices which can assume one of two
for controlling other circuitry in a specific sequence dictated by a control clock or enable/
stable output states and which have one or more inputs that can cause the output state
disable control signals. The simplest form of storage is the SR flip-flop. These circuits
to change.
are called transparent latches because the output responds immediately to changes at
the input, and the input state will be remembered, or latches onto. The latches
sometimes have an enable input, and the input state will be remembered, or latched
6.2 SET-RESET (SR) FLIP-FLOP
onto. The latch will sometimes have an enable input, which is used to control the latch to
accept or ignore the SR input states. Most sophisticated flip-flops use a clock The SR flip-flop is a data storage circuit that can be constructed using the basic gates
covered in the previous chapters. Using a cross-coupling scheme with two NOR gates,
we can form the flip-flop as shown below.
LEARNING OBJECTIVES
Two version of SR latches.
The objectives of this unit are to:
1. Understand S-R flip-flops.
2. Understand J-K and D flip-flops
3. Introduce to shift register
4. Introduce to universal shift register.
LEARNING OUTCOMES
• Logic symbol
After completing the unit, students should be able to:
1. Explain the internal circuit operation of S-R flip-flop
2. Sketch the operation of D flip-flops using timing diagrams.
3. Sketch the operation of JK flip-flops using timing diagrams.
4. Use timing diagrams to illustrate the synchronous and asynchronous operation of
J-K flip-flops.
5. Understand and evaluate the function of shift register and timer.
For Set condition, Q should have output 1 and Q should have output 0. A HIGH on the
Set will make the output of the upper NOR equal 0 and that 0 is fed down to the lower
NOR, which together with a LOW on the Reset input will cause the lower NOR’s output
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to equal a 1. Now when the 1 is removed from the Set input, the flip-flop should
remember that it is Set. Latch Start RESET (Q=0) Latch Start SET (Q=1)
• Two Possibilities for the RESET Operation (High on Both Input)
The flip-flop would be able to Reset by making S = 0, R = 1. With R= 1, the lower NOR
will output a 0, placing a 0 -0 on the upper NOR, making its output 1, thus the flip-flop
flips to its reset state. In conclusion, the explanation above show the operation of active
low version of flip-flop as shown in Table below. Operation of the active high input NOR
gate latch is similar but requires the use of opposite logic levels.
No change condition
6.2.1 SR Flip-Flop Operation
Truth table for an active – LOW input S R latch.
Inputs Outputs Comments
S R Q Q’
1 1 NC NC No change. Latch remains in present
0 1 1 0 Latch SET
1 0 0 1 Latch RESET
Invalid Condition
0 0 1 1 Invalid condition
Example 6.1 :
Given the input of the waveform as the input, for the SR flip-flop shown below, sketch the
Q output waveform.
S
Latch Start RESET (Q=0) Latch Start SET (Q=1)
• Two Possibilities for the SET Operation R
Solution:
Q
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6.3 D FLIP-FLOP Example 6.2 :
Given the waveform in the figure below for the D input and the clock, determine the Q
The addition of an inverter to an S – R flip flop creates a basic D flip – flop. The output output waveform if the flip-flop starts out RESET.
always takes on the states of the D input at the moment of a rising clock edge or at the
moment of the falling clock edge but not both at the falling and rising edges and never at
any other times. It is called the D flip for this reason, since the output takes the value of CLK
the D input or Data input, and delays it by one clock count. The D flip-flop can be
interpreted as a primitive memory cell, zero-order hold or delay line. D flip – flop is useful
D
when a single data bit (1 or 0) is to be stored.
Solution :
D Flip-Flop Truth Table
Q
Clock D Q Qprev
X
Rising Edge 0 0
The Q output goes to the state of the D input at the time of the positive going clock edge.
Rising Edge 1 1 X The resultant output is shown in figure above
Non rising X constant
6.4 JK FLIP FLOP
‘X’ denotes a don't care condition, meaning the signal is irrelevant
JK flip flop is versatile and is widely used type flip – flop. The difference between J – K
These flip-flops are very useful as they form the basis for shift registers, which are an and S – R is that J – K flip – flop has no invalid state as does S – R flip – flop. The JK
essential part of many devices. The advantages of the D flip-flop over the D type latch is flip-flop augments the behaviour of the SR flip-flop (J=set, K = Reset) by interpreting the
that it captures the signal at the moment the clock goes high and subsequent changes of S=R=1 condition as a flip or toggle command. Specifically the combination J= 1, K= 0 is
the data line do not influence Q until the next rising clock edge. An exception is that a command to set the flip-flop; the combination J=K= 1 is a command to toggle the flip-
some flip-flop has a reset signal input, which will rest Q (to zero), and may be either flop, i.e. change its output to the logical complement of its current value. Setting J=K=0
asynchronous or synchronous with the clock. does NOT result in a D flip-flop, simply set K equal to the complement of J. The JK flip-
flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-
flop or a D flip-flop. Note that the flip-flop is positive edge triggered (clock pulse) as seen
in the timing diagram.
D Flip flop symbol
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• JK Flip-Flop Truth Table
Inputs Outputs Comments
J K CL Q
0 0 ↑ Qo Qo No change
0 1 ↑ 0 1 RESET
1 0 ↑ 1 0 SET
JK timing diagram
0 1 ↑ Qo Toggle
Qo
The following is the JK flip-flop develop using the combinational logic and its symbol ↑ = clock transition LOW to HIGH
Qo = output level prior to clocktransition
Example 6.3 :
The waveforms in figure below are applied to the JK and clock input as indicated.
Determine the Q output, assuming that the flip-flop is initially RESET.
• Transitions illustrating the toggle operation when
J = 1 and K = 1.
CLK 1 2 3 4 5
J
K
Solution :
Q
No
Toggle Reset Set Set
change
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Since it is a –ve edge triggered flip-flop, as indicated by the bubble at the clock input, the
Parallel in / parallel out (PIPO)
Q output will change only on the –ve-going edge of the clock pulse.
Serial in / serial out (SISO)

Parallel in / serial out (PISO)
At the first clock pulse, both J and K are HIGH; because this is ogle condition, Q goes
Serial in / parallel out (SIPO
HIGH.
6.5.1 SERIAL DATA VS PARALLEL DATA MOVEMENT
At clock pulse 2, a no-change condition exists on the inputs, keeping Q at a HIGH level.
When clock pulse 3 occurs, J is LOW and K is HIGH, resulting in a RESET condition, Q SERIAL PARALLEL
goes LOW. • Movement of N-bit •Require only one
At clock pulse 4, J is HIGH and K is LOW, resulting in a SET condition; Q goes HIGH. data require N CLK pulse to
A SET condition still exist on J and K when clock pulse , so Q will remain HIGH. number of CLK transfer all N-bit of
pulses. Thus, the data. Thus,
operation is slow. operation is faster
6.5 SHIFT REGISTER than serial.
•Only one FF is •Required N number
Shift registers are constructed using several flip-flop, connected in such a way to STORE required to be of connection to the
and TRANSFER digital data. connected at the output terminal,
output terminal, thus which is
Basically, D flip-flop is used. The input data (either ‘0’ or ‘1’) is applied to the only one wire is proportional to the
terminal and the data will be stored at Q during positive/negative-edge transition of the required. number of bit. Thus,
clock pulse too many
connection is
required.
D
1 1
Q
Q
Positive edge transition of CLK
One D FF is used to store 1-bit of data. Thus, the number of flip-flops used is the same
with the number of bit stored. Shift register mean that the data in each FF can be
transferred/move to other FF upon edge triggering of the clock signal. Four types of data
movement in shift register are:-
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6.5.2 TYPES OF SHIFT REGISTER
Serial in / serial out (SISO)
Flip-flop connection for SIPO.
• SIPO data movement. Binary data 10111 is transferred!
Flip-flop connection for SISO
• SISO data movement. Binary data 10111 is transferred!
Parallel in / serial out (PISO)
Serial in / parallel out (SIPO)
Flip-flop connection for PISO.
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• PISO data movement.
CLK
Data
Input
Qo
Q1
Q2
Q3
Q4
Solution :
Example 6.4 :
The first data bit (1) is entered into register on the first closck pulse and then shifted from
Show the states of the 5-bit register in figure below for the specified data input and clock left to right as the remaining bits entered and shifted. The register contains 11010 after
waveform. Assume that the register is initially cleared (all 0s) five clock pulse.
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6.5.3 UNIVERSAL SHIFT REGISTER
A universal shift register has both serial and parallel input and output capability.
• 74164 is a 8-bit SIPO shift register
• 74165 is a 8-bit PISO register
• 74195 can be used as a 4-bit PIPO register
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• 74194 is a 4-bit universal bidirectional shift register
Parallel loading which, is synchronous with positive transition of the clock, is
accomplished by applying the four bits of data to the parallel inputs and HIGH to the S0
and S1 inputs. Shift right is accomplished synchronously with the positive edge of the
clock when S0 is HIGH and S1 is LOW. Serial data in this mode are entered at the shift
right serial input (SR SER). When S0 is LOW S1 is HIGH, data bits shift left
synchronously with clock, and new data entered at the shift-left serial (SL SER).
6.6 555 TIMERS
The 555 timer is an extremely versatile integrated circuit which can be used to build lots
of different circuits. The 555 timer can be use effectively without understanding the
function of each pin in detail.
The 555 timer is frequently used in astable mode to generate a continuous series of
pulses, but the 555 timer can also be use to make a one-shot or monostable circuit. The
555 can source or sink 200 mA of output current, and is capable of driving wide range of
output devices.
The 555 has three operating modes:
1. Monostable mode: in this mode, the 555 functions as a "one-shot". Applications
include timers, missing pulse detection, bouncefree switches, touch switches,
Frequency Divider, Capacitance Measurement, Pulse Width Modulation (PWM)
etc.
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2. Astable - Free Running mode: the 555 can operate as an oscillator. Uses include
LED and lamp flashers, pulse generation, logic clocks, tone generation, security
alarms, pulse position modulation, etc.
3. Bistable mode or Schmitt trigger: the 555 can operate as a flip-flop, if the DIS pin
is not connected and no capacitor is used. Uses include bouncefree latched
switches, etc.
Asynchronous (Ripple) Counters
In an asynchronous counter, each flip-flop output drives the CLK input of the next flip-
flop. This counter arrangement is called asynchronous counters because the flip-flop do
not change states in exact synchronous with the applied clock pulse; only flip-flop A
Two-bit asynchronous binary counter
responds. A two-bit asynchronous counter is shown below. The external clock is
Below is a three-bit asynchronous binary counter and its timing diagram for one cycle. It
connected to the clock input of the first flip-flop (FF0) only. So, FF0 changes state at the
works exactly the same way as a two-bit asynchronous binary counter mentioned above,
falling edge of each clock pulse, but FF1 changes only when triggered by the falling edge
except it has eight states due to the third flip-flop.
of the Q output of FF0. Because of the inherent propagation delay through a flip-flop, the
transition of the input clock pulse and a transition of the Q output of FF0 can never occur
at exactly the same time. Therefore, the flip-flops cannot be triggered simultaneously,
producing an asynchronous operation. Note that for simplicity, the transitions of Q0, Q1
and CLK in the timing diagram above are shown as simultaneous even though this is an
asynchronous counter. Actually, there is some small delay between the CLK, Q0 and Q1
transitions.
Usually, all the CLEAR inputs are connected together, so that a single pulse can clear all
the flip-flops before counting starts. The clock pulse fed into FF0 is rippled through the
other counters after propagation delays, like a ripple on water, hence the name Ripple
Counter.
The 2-bit ripple counter circuit above has four different states, each one corresponding to
a count value. Similarly, a counter with n flip-flops can have 2 to the power n states. The
number of states in a counter is known as its mod (modulo) number. Thus a 2-bit counter
Three-bit asynchronous binary counter
is a mod-4 counter.
A mod-n counter may also describe as a divide-by-n counter. This is because the most
significant flip-flop (the furthest flip-flop from the original clock pulse) produces one pulse
for every n pulses at the clock input of the least significant flip-flop (the one triggers by
the clock pulse). Thus, the above counter is an example of a divide-by-4 counter.
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6.7 UNIT’s SUMMARIZED NOTES
In this unit we have studied that:
1. The SR flip-flop is a single bit data storage circuit that can be constructed using
basic gates.
2. The D flip-flop operates similar to the SR flip-flop except it has only a single data
input, D.
3. The JK flip-flop differs from the SR flip-flop because it can also perform a toggle
operation. Toggling means that Q flips to its opposite state.
4. The basic types of registers, classified by the input and output
i. Serial in/ serial out
ii. Serial in/ parallel out
iii. Parallel in/serial out
iv. Parallel in/ parallel out.
5. 555Timers
6. Asynchronous and Synchronous Counters
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