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An 80mV Startup Voltage Fully Electrical DC–DC Converter,

for Flexible Thermoelectric Generators
Carlo Veri1,2, Luca Francioso2, Mirko PAsca1, Chiara De Pascali2, Pietro Siciliano2, Stefano D’Amico1,2
1
Department of Innovation Engineering – University of Salento, Lecce, Italy
2
Institute of Microelectronics and Microsystems – CNR – IMM, Lecce, Italy
1
[name.surname]@unisalento.it – 2[name.surname]@le.imm.cnr.it

Abstract— This paper presents a fully electrical DC–DC the direct conversion of heat into electrical power by using
converter designed for thermoelectric generator (TEG) for solid state devices characterized by extended maintenance –
energy harvesting applications. The proposed flexible free durability and noiseless operation without moving parts.
thermoelectric generator has been achieved by screen printing
Furthermore the flexibility property is a key point for
technology on 80µm thick common paper and thin Kapton foil
and integrates 280 thermocouples, for an output voltage of about developing wearable TEG integrated with the tissues of the
75mV with 5K of thermal gradient. In order to step up the dresses and used to supply sensors for healthcare and
voltage at the output of the thin film flexible thermoelectric biometric parameters monitoring [2].
generator, a DC–DC converter has been designed. This latter A thermoelectric generator is composed by an array of several
operates with an input voltage ranging from 80mV up to 370mV. thermocouples electrically connected in series and thermally
The proposed DC–DC converter achieves an automatic control
in parallel. The performance of a TEG is strongly influenced
based on pulse width modulation (PWM), ensuring 1V output
voltage. The control circuit includes two sections. The first one by temperature distribution inside the materials and thermal
provides a forward control operating in the 80mV to 150mV gradient which can be recovered between the hot and cold
input voltage range. The second one operates a feedback control, junctions of the thermocouples. The conversion efficiency and
as the output voltage of thermoelectric generator is higher than the output voltage of the TEG are limited by the reduced
150mV. The DC–DC converter is implemented in a 65nm CMOS thermal gradient existing between body heat and environment.
technology, achieving a 73% peak efficiency.
For this reason, the implementation of a step up DC–DC
Index Terms— Energy Harvesting, Thermoelectric Generator,
converter is needed to increase and regulate the TEG output
Flexible, Thin Film, DC-DC Converter, Low Startup Voltage, voltage making it usable to supply sensor nodes. During the
High Efficiency, Wearable Application. last years, the main goal in the DC–DC design is reducing the
voltage, which converters start to operate. In [3] a batteryless
interface circuit is proposed. It presents a startup voltage of
I. INTRODUCTION 35mV, but it needs of a mechanical switch to start the step up
process. In [4] a 20mV interface circuit is presented. Its
I N recent years, the interest of scientific community and
caregivers towards solutions for energy autonomous and
control circuitry is supplied by a pre–charged output capacitor
and this aspect makes it less attractive for wearable health
wearable biometric monitoring sensors for elderly assistance
monitoring applications. In [5] integrated transformers
has grown very fast. In order to extend the life-time of
operating at high frequency were adopted for the
traditional batteries, intensive research is currently focused on
implementation of a 85mV input voltage boost converter.
the development of portable power generator able to harvest
Although startup voltage is very low, using integrated
energy from different environmental sources and convert it
transformers causes a very low efficiency. Generally, when
into electricity [1]. Vibrations, heat and light are some of the
input voltage is less than 100mV the conversion efficiency
most frequently exploited energy sources. The thermoelectric
drops, so the challenge is to achieve boost converter with low
generation is a particularly interesting technology providing
startup voltage and a great conversion efficiency.
This paragraph of the first footnote will contain the date on which you In this work, the design of a batteryless 80mV input voltage
submitted your paper for review. It will also contain support information, DC–DC converter is discussed. The paper is organized as
including sponsor and financial support acknowledgment. For example, “This follows. Section II includes experimental aspects of
work was supported in part by the U.S. Department of Commerce under Grant
BS123456”. fabrication and characterization of a screen printed
The next few paragraphs should contain the authors’ current affiliations, thermoelectric generator, whose electrical performance were
including current address and e-mail. For example, F. A. Author is with the taken as starting point for the DC-DC converter design
National Institute of Standards and Technology, Boulder, CO 80305 USA (e-
mail: author@ boulder.nist.gov). presented in this work.
S. B. Author, Jr., was with Rice University, Houston, TX 77005 USA. He Afterwards, in section III, the detailed circuit implementation
is now with the Department of Physics, Colorado State University, Fort of the proposed DC–DC converter is given. Sections IV and V
Collins, CO 80523 USA (e-mail: author@lamar.colostate.edu).
T. C. Author is with the Electrical Engineering Department, University of
show experimental results and concluding remarks,
Colorado, Boulder, CO 80309 USA, on leave from the National Research respectively.
Institute for Metals, Tsukuba, Japan (e-mail: author@nrim.go.jp).

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II. THE PROPOSED THERMOELECTRIC GENERATOR metrology review [14]. The real temperature difference was
The flexible TEG presented in this work has an area of verified by a high resolution LWIR thermal infrared camera
105mm×105mm and consists of 280 thermocouples of Bi 2Te3 (Gobi-640-GigE, Xenics). Figure 2 shows two high resolution
and Sb2Te3 alloys deposited by screen-printing technology. thermal images (18mm lens, 30μm of pixel pitch) of the
Screen printing is a relatively simple, versatile and n–type legs array, on the ends of which is kept a thermal
cost-effective deposition process, which is especially gradient of 4°C (Fig. 2.(a)) and 18°C(Fig. 2.(b)).
convenient for fabricating flexible devices. Screen printable
Bi2Te3 and Sb2Te3 alloys possess the highest figure of merit
near to room temperature, which is in the range of 0.1-0.6
[11,12,13]. For near room temperature applications, the
conversion efficiency of a TEG based on such thermoelectric
materials is reasonably in the range of 0.07%-0.2%, when a
temperature difference of 5K is recovered at the hot/cold
thermocouple junctions. For the TEG design, the
thermoelectric generation performance of the single
thermocouple was evaluated in terms of output power and
thermal efficiency. An estimation of the maximum number of
thermocouples which can be integrated on the available area (a)
as function of the length and width of the legs was performed.
Films of p-Sb2Te3/n-Bi2Te3 with 20µm thickness were screen
printed on both 80µm thick common paper and 25µm thick
Kapton foil substrates (Fig. 1). In order to reduce the internal
resistance of the generator and to increase the total output
current, the TEG was configured as parallel of 2 blocks, each
of which containing 140 thermocouples connected in series
electrically. A TEG internal resistance of about 37.5kΩ was
found. With a thermal gradient of 5K between the hot/cold
thermocouple junctions, an open circuit voltage of about
75mV was measured at the output terminals of TEG.

(b)
Fig. 2. Thermal camera images of the n-type array, on the ends of which is
kept a thermal gradient of (a) 4°C and (b) 18°C.

A Seebeck coefficient of about 104µV/K for pristine n–type

Fig. 1. Flexible TEG realized by screen printing technique on paper (left) and paste was calculated by linear interpolation of the measured
Kapton substrates (right). 6” silicon wafer has been used as carrier substrate voltage as a function of the thermal gradient. In figure 3, a
for film printing. It occupies an area of 105mm x 105mm.
comparison between experimental data and linear fit is shown.
The Seebeck coefficient of pristine n-type screen printed
semiconductor legs was experimentally obtained by
acquisition of generated voltage, keeping the hot and cold side
of different thermolegs in thermal contact with two aluminum
masses with PID temperature control. To this aim, one end of
each leg was heated at controlled higher temperature while the
other end was kept in contact with a thermal mass at room
temperature (300K). The thermal gradient between the legs
ends was monitored by using two commercial miniaturized
thin film platinum thermometer (PT1000) placed onto both
ends of semiconductor regions at different temperatures and
read by a Keithley 2700 multimeter. Experimental data were
acquired with resolution of 0.001K and temperature accuracy
of ±0.01K. The experimental procedure for Seebeck Fig. 3. Generated voltage vs thermal gradient imposed between the ends of
calculation is the typical differential method reported in n-legs.

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The Seebeck coefficient for p/n complete thermocouple is III. THE PROPOSED DC-DC CONVERTER
estimated to be about 200 µV/K. Figure 5 shows the architecture of the proposed DC–DC
Data reported in Fig. 3 are average values collected by twin converter. It is composed by five functional blocks:
PT1000 measurements of different legs at hot and cold
thermocouples ends. The screen printed silver paste electrical  the ultra–low voltage local oscillator;
paths shown in Fig. 1 help to correctly align the thermometers
with semiconductors borders.  the boost converter circuit;
Figure 4(a) shows the package of the TEG optimized to  the feedforward control circuit;
enhance the thermal gradient exploited for the energy
scavenging: the thermoelectric module (realized on Kapton  the feedback control circuit;
substrate, in the reported image) was coupled to a  the analog multiplexer;
polydimethylsiloxane (PDMS) layer, which was opportunely
molded to thermally insulate thermocouples cold junctions and A. The ultra-low voltage local oscillator
maximize the thermal gradient for the Seebeck generation.
The local oscillator defines the startup voltage of the DC–DC
In figure 4(b) the thermoelectric alloys legs spanning between converter. For this reason, it is the most critical component to
the hot site of the package (the valley region) and the cold site be designed. In Figure 6, the proposed circuit solution is
(on the sine wave peaks) are visible. Metal contact pads were shown.
realized on each section of the thermoelectric module, in order
to allow electrical testing of single partitions of the array. CLK VIN CLK_INV
L1 L2
SINGLE SINGLE
CELL CELL

N
N
M1 M2

L3 CS1 L4
CS2

Fig. 6. Schematic of the local oscillator.

It consists of an LC resonant circuit made by inductors L1&L2

and the capacitive load represented by the input capacitance of
the following charge pump, an NMOS cross coupled
(a)
architecture, and source degenerations made by inductors
L3&L4 and capacitors CS1&CS2 in parallel. The L1, L2, L3, and
L4 inductors and CS1&CS2 are off-chip components. This
oscillator topology has been preferred because it permits the
operation at very low voltage. With respect to a simple LC
oscillator, the minimum operation voltage is reduced thanks to
the source degeneration impedances [6]. The local oscillator
startup condition is given by the following relationship:
(b)
Fig. 4. (a) Photograph of the TEG and (b) cross section schematic of
packaging for thermoelectric generator.
FEEDBACK CONTROL CIRCUIT

INPUT COMPARATORS
Del_1 R1 REF2 OUT_150
CMP1
REFERENCES REFERENCE R2 CLK/2
GENERATOR 1 CMP2 Del_2 PWM VOSC_2 CLK/2N
GENERATOR 2 REF1 EN1
TEG GENERATOR
CMP3 Del_3 HYSTERESIS
CLK/2N COMPARATOR
CLK/2 CMP4 OUT_150
VIN EN2
LBOOST VOUT
CLK/64N

M8
Del_1

CLK/2N
Del_2

CLK/64
Del_3

CLK/2

CLK
CLK_INV CLK CHARGE VCHARGE EN COUT RLOAD
CLK_INV IN1 M7
PUMP VOSC
PROGRAMMABLE OUT
DUTY CYCLE VOSC_1
LOCAL OSCILLATOR CLK IN2
MODULATOR
MUX BOOST CONVERTER
FEEDFORWARD CONTROL CIRCUIT
Fig. 5. Schematic of the DC – DC converter.

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(1)
| |
where gm is the transconductance of the NMOS transistors, 𝜔o
is the resonance frequency, and Q1 is the quality factor of
inductors L1 and L2. At very low input voltage, the NMOS
transistors operate in weak inversion, and its transconductance
is equal to:
(2)
being n the slope factor of M1 and M2, Vt is the thermal
voltage, Is is the reverse saturation current. The oscillation
frequency (200kHz) depends on inductors L1&L2 values and
input capacitance of the charge pump, where the output nodes
of the oscillator are connected. The relationship is:
𝜔 (3)
√ √
where N is the number of stages of charge pump, C0 is the
input capacitances of each stage of the charge pump and CPAR
is representative of the parasitic capacitances caused by
parasitic ground capacitance of C0, interconnection lines and
pads. Figure 8 shows the architecture of the single cell of the
charge pump including C0 and CPAR. However, the value of
CPAR has been estimated to be lower than 1/10 of C0, so it can
be neglected. Combining the relationships (1), (2) and (3), the
minimum input voltage allowing the local oscillator to operate
is given by:
(4)
√
( )
( )
The L3&L4 inductors are used to fix at ground the sources of
the NMOS transistors at the startup. The CS1 and CS2
capacitances play an important role. Increasing their value, the
minimum supply voltage of the local oscillator is reduced, as
figure 7 shows.
105
100
95
VDD,MIN [mV]
90
85
80
75
1 2 3 4 5 6
CS [pF]
Fig. 7. VDD,MIN versus CS1. A minimum value of 2pF ensures a startup voltage
of the local oscillator equal to 78mV.
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4
Over the value of 2pF the effect of CS1 on the startup voltage
is limited. The startup voltage of the local oscillator calculated
by (4) is 78mV, which is in good agreement with 80mV
measured experimentally. Table 1 reports the dimensions of
L1÷L4 inductors, CS1 and CS2 capacitors and transistors MOS.
COMPONENTS VALUE
L1, L2 5mH
L3, L4 2µH
CS1, CS2 2pF
W = 9µm
M1, M2 L = 300nm
(native) Finger = 5
Multiplier = 110
Tab. 1. Dimensioning of the components of the local oscillator.
B. The boost converter
In figure 5, it is possible to note the schematic of boost
converter. It consists of two MOS transistors M7 and M8 that
are switched by PWM clock signal. The values of the LBOOST
inductor (off–chip), and COUT (off–chip) output capacitor are
560µH and 47µF, respectively. Boost converter operates in
continuous conduction mode (CCM), so the relationship
between input voltage and steady state output voltage is:
(5)
where D is duty cycle of PWM clock signal. As it possible to
note by equation (5), the voltage gain depends on PWM clock
signal. Therefore a lower value of VIN needs of an higher duty
cycle value to achieve the same VOUT.
C. The feedforward control circuit
The feedforward control circuit provides a PWM clock signal
(VOSC_1), which drives the boost converter for low VIN
(80mV–150mV range). During the normal operation, reducing
the power consumption of the DC – DC converter improves
the efficiency. For this reason, the feedback control circuit is
off, when the feedforward control circuit operates.
The feedforward control circuit is composed by:
 a charge pump [7] (fig. 9);
 a programmable duty cycle modulator (fig. 10):
 a references generator (fig.5, reference generator 1).
 4 input comparators (fig. 5, CMP1, CMP2, CMP3, CMP4);
The amplitude value of VOSC must be higher than threshold
voltage of M7, to switch on the transistor. For this reason, a
charge pump with 25 stages is used in order to step up VIN. At
the minimum input voltage (80mV) it is possible to reach a
voltage at the output of the charge pump (VCHARGE) 10 times
higher than VIN, as calculated as follows:
( ) (6)
Where VCLK, equal to 160mV at 80mV input voltage, is the
peak voltage of the waveform provided by the LC local
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oscillator, which allows to obtain a peak value of the After the division, the clock signal (CLK/64) is shifted by the
waveform higher than the supply voltage. ROUT is the output programmable delay circuit, which is composed by 5
resistance of each stage, while IOUT is the current consumed by programmable delay cells, as figure 11(a) shows. Each cell,
the following programmable duty cycle modulator. As whose schematic is shown in figure 11(b), includes a capacitor
VCHARGE grows, a clipping circuit, made by two series diodes array that regulates the delay produced on the divided clock.
VCHARGE
D1 and D2, limits amplitude at 1.2V, in order to prevent the
break-down of M7 and M8 MOS transistors for high input DELAY DELAY CLK/64SHIFTED
CLK/64
CELL CELL
voltage. Figure 8 shows the architecture of the charge pump. VCHARGE
Del_1
CLK Del_2
Del_3 R CLK/64SHIFTED
VIN SINGLE SINGLE VCHARGE (a) C1 C2 C3
CLK/64
CELL CELL D1 COUT IOUT C Del_1 Del_2 Del_3
VCLK
D2 CLK
CLK_INV 0 (b)
(a) C0 CPAR M
M0 2 Fig. 11. (a) Schematic of programmable delay circuit and (b) programmable
VIN delay single cell.
VCHARGE

The following NAND gate has the divided clock and its
M1 C 0 M3
CPAR delayed copy (CLK/64SHIFTED) at its inputs, generating PWM
VCLK CLK_INV
0
clock signal with a duty cycle depending on the delay set by
(b)
the programmable delay circuit. Table 2 reports the achieved
Fig. 8. (a) Architecture of the charge pump and (b) schematic of single cell.
PWM duty cycle of according to the value of the input
The integrated output capacitor of the charge pump, COUT, is voltage, VIN, and the corresponding code coming from the
100pF. The programmable duty cycle modulator is supplied input comparators feeding the capacitor arrays.
by VCHARGE. This circuit provides an high duty cycle clock DUTY
VIN RANGE DEL_1 DEL_2 DEL_3
signal according to the input voltage value VIN. Figure 9 shows CYCLE
the schematic of the programmable duty cycle modulator. 80mV÷100mV 92% 0 0 0
VCHARGE 100mV÷115mV 90% 1 0 0
Del_1
Del_2
Del_3

D3 M5 115mV÷130mV 88% 1 1 0
D4 FREQUENCY CLK/64SHIFTED 130mV÷150mV 85% 1 1 1
VOSC_1
M4 CLK DIVIDER Tab. 2. VIN vs duty cycle and corresponding code for various input voltage
M6 DELAY To MUX
range.
CLK/2 CLK/2N CLK/64N CLK/64

Fig. 9. Schematic of the programmable duty cycle modulator. The input comparators are supplied by the output voltage,
VOUT. They are used to set the capacitor array of the
The oscillator positive output, CLK, is directly connected to
programmable delay single cell, according to the value of the
the gate of the M6 transistor. The M4 NMOS transistor is
input voltage. For VIN less than 100mV, as VOUT is not
always off, therefore only the leakage current flows in the
sufficient to supply the input comparators, their output are set
series connected diodes D3 and D4. This branch is used as
to the ground, enabling the minimum delay.
voltage reference in order to fix the polarization of M5 PMOS
VOUT VOUT
transistor, whose gate is connected to the node between the VIN VIN
series diodes. In order to improve the efficiency, the clock 90mV Del_1 120mV Del_3
100mV CMP1 130mV CMP3
frequency is divided by a 64 factor thanks to the frequency CLK/2 CLK/2
divider. The latter is composed by 6 divider cells, which CLK/2N VOUT CLK/2N VOUT
VIN VIN
consist of a positive edge-triggered D latch (fig. 10).
105mV Del_2 140mV OUT_150m
VCHARGE 115mV CMP2 150mV CMP4
CLK/2 CLK/2 CLK/2
CLK/64 CLK/2N CLK/2N
CLK CLK DIVIDER Q CLK DIVIDER Q CLK DIVIDER Q
CELL QN CELL QN CELL QN
(a)
CLK/64N CLK/2
CLK/2N VIN
(a) PLUS OA1
OUT
1 REFH MINUS
CLK R
2 CLK/2N SR NOR OUT
5
Q QN
CLK/2N LATCH
QN S
6 MINUS
3 OUT
REFL PLUS OA2
4
CLK/2

(b) (b)
Fig. 10. (a) Architecture of the frequency divider and (b) schematic of the Fig. 12. (a) Schematic of the input comparators and (b) schematic of single
divider cell. hysteresis comparator.

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VOUT
M21 M22
REF4
M20 M19
BIAS

M23 M24
VOUT
R15
M9 M10 M11 M12 M13 M14 M15 M16 M17 M18
(a) 90mV 100mV 105mV 115mV 120mV 130mV 140mV 150mV REF1
OA3 BIAS CM
R3 R4 R5 R6 R7 R8 R9 R10 R11 R12
R13
R14 R16

REFERENCE REFERENCE
GENERATOR 1 GENERATOR 2

(b)
Fig. 13. (a) Schematic of the operational amplifier in the (b) schematic of the reference generators.

Each comparator has an hysteresis behavior (fig. 12(a)), R18

receiving a low REFL (90mV for CMP1, 105mV for CMP2, C6 VOUT CLK/2
120mV for CMP3 and 140mV for CMP4) and an high REFH CM1
R3 REF3
(100mV for CMP1, 115mV for CMP2, 130mV for CMP3 and R4 VOSC_2
CLK/64 VM R17 To MUX
150mV for CMP4) provided by reference generator 1 ( fig. 5). DAC VP INT OUTP

The 10mV difference between the low and the high thresholds CLK/2N
CLK/64N R19
EN2
of the input comparators is useful to make the design more REF4
C5
robust against kickback noise due to LBOOST inductor, as they
R20
are directly supplied by the input voltage (VIN) on the input
Fig. 14. Schematic of the PWM generator.
node where also LBOOST inductor is connected. As figure 12(b)
shows, the input comparators are composed by two single

OUTP [V]
0.6
ended dynamic latched comparators [8] (OA1 and OA2), and an VOUT 0.4
CLK/64 M28 CLK/64N 0.2
SR NOR latch. This structure has been preferred because of its M27
0.5 0.6 0.7
i
ultra–low power characteristics. The reference generator 1 [9] REF4 M25 M26 REF4
VP - VM [V]
0.2
provides the voltage references to the input comparators. VP R21 R22 VM 0
-0.2
Figure 13 shows the circuit. It is an ultra–low voltage bandgap 0.5 0.6 0.7
(a) ii
CLK/64N [V]

reference with minimum supply voltage of 950mV, ensuring a 1

good robustness of the voltage references against the supply 0.5
0
voltage variations. 0.5 0.6
iii
0.7

D. The feedback control circuit
The feedback control circuit is enabled, as the output
voltage, VOUT, reaches 1V and VIN is higher than 150mV. The
feedback control circuit provides a PWM clock signal (VOSC_2)
to the boost converter, with a feedback control of duty cycle
that improves the output voltage accuracy. The feedback
control circuit is composed by:
 the PWM generator (fig. 14);
 the hysteresis comparator;
 the reference generator (fig.5, reference generator 2).
The PWM generator consists of a DAC, an integrator and a
dynamic latched comparator. At first the DAC receives two
square waveforms (CLK/64 & CLK/64N) which are derived
from the main clock, CLK, dividing by 64 its frequency. This
operation is performed by the frequency divider included in
the programmable duty cycle modulator of the feedforward
control circuit. The REF4 reference is provided by the
reference generator 1. Figures 14 and 15(a) show the
schematics of the PWM generator and the DAC, respectively.
Time [ms]
(b)
Fig. 15.(a) Schematic of the DAC and (b) simulation with variable VOUT. In
(b.i) the OUTP waveform represents the output of the integrator.
The task of the DAC is to produce a differential square
waveforms (VP - VM), with a peak voltage value robust against
the supply voltage (VOUT) variation. Figure 15(b) shows a
transient simulation with a variable supply voltage VOUT,
between 920mV and 1.2V. The peak voltage of VP - VM
(fig. 15(b.ii)), remains constant around 0.3V.
The architecture of the integrator circuit is shown in figure 16.
This architecture was preferred because it operates at low
supply voltage [10]. It uses two common mode circuits (one
for the input stage and one for the output stage). The common
mode of the OUTP is centered around the half of the supply
voltage (i.e. VOUT/2) to maximize the output swing, while the
common mode voltage at the input is set close to the ground
voltage, as the voltage swing at the input node is limited
thanks to the virtual ground. In this way it is guaranteed a
sufficient overdrive voltage to the input MOS transistors
(M27&M28) at low voltage supply.

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VOUT CURRENT SOURCES

M53 M56 M57

EN2 M46 REF5 M59 M52 +
From M55
M54 M58
BIAS Circuit
M60 R26

M34 M33 M35 M41

CM1 M36
CTRL1
M42 CTRL2 M43
M37 M38 OUTN M27 M28 M47
+ OUTP M48
CTRL2 CTRL1
R24 M32 M29 M31 M44 M45 M50
M40 M30 R25 M49
M39
REF5 M51
From
R23 INPUT CMFB
OUTPUT CMFB BIAS Circuit

Fig. 16. Schematic of the operational amplifier of the integrator.

The drawback is the presence of a DC current that flows robust against the disturbs on the output voltage of boost
through R18 resistor, which is absorbed by the current sources converter, VOUT. Figure 17 shows the architecture of the
circuit, internal of the integrator. hysteresis comparator.
The following low power comparator makes a comparison CMP CLK/2N
between triangle waveform coming from integrator and REF3, VOUT REF2 5
IN2
which is a partition of VOUT on R4 resistor ( fig. 14). It has a OUT5
dynamic latched architecture, receiving two clock signals from R1 REF1 IN1 S
the frequency divider (CLK/2 & CLK/2N). The comparator SR NAND Q EN1
CLK/2 LATCH
provides a PWM clock signal depending on VOUT. R2 R
IN2 1
The hysteresis comparator (fig. 5) makes a comparison OUT6
between a partition of VOUT on R2 resistor, REF2, and the REF1
IN1
voltage reference, REF1, provided by reference generator 2, in HYSTERESIS
CLK/2N COMPARATOR
order to set its output, as VOUT reaches 1V. CMP6
The hysteresis behavior is useful to make the DC–DC more Fig. 17. Schematic of the hysteresis comparator.

SR NAND
EN1
VOUT
LATCH
2 M62 M61
OUT5

M64 M63 REFL REFH

R26 R27
M65 M67 M68 VOUT
M66 (b)
1.2
Voltage [V]

VOUT V
CLK/2N OUT
0.8
OUT
M69 0.4
5
OUT
6
M70 M71
0.5 0.6 0.7 0.8 0.9 1 1.1
OUTM OUTP
i
M72 M75
Voltage [V]

1.2
M73 M74 S
0.8
R
0.4
VOUT
0.5 0.6 0.7 0.8 0.9 1 1.1
M77 CLK/2 M76 ii
Voltage [V]

1.2
REF1 M78 M79 0.8
REFH REFL REFH REFL
REF2 0.4
DYNAMIC M80
CLK/2 0.5 0.6 0.7 0.8 0.9 1 1.1
LATCHED Time [ms]
COMPARATOR
iii
(a) (c)
Fig. 18. (a) Schematic of the CMP5 and CMP6, (b) hysteresis behavior and (c) transient of the hysteresis comparator: (c.i) transient simulation with triangle
waveform VOUT (full line) and output waveforms of the CMP5 (OUTP5 – dashes line) and the CMP6 (OUTP6 – dots line); (c.ii) input waveforms to SR NAND
latch 1 (S (Set) – dashes line, R (Reset) – dots line); (c.iii) the output of the hysteresis comparator EN1 with two reference REFH and REFL.

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The structure of the hysteresis comparator consists of two
single ended dynamic comparators (CMP5 and CMP6), a
buffer, an inverter stages and an SR NAND latch 1.
Each CMP5 and CMP6 comparator is composed by a dynamic
latched architecture and an SR NAND latch 2, shown in figure
18(a). Simulations results are shown in order to explain the
operation mode of the hysteresis comparator. Figure 18(c)
shows a transient with a variable VOUT, varying as a triangle
waveform between 0V and 1.2V. As the voltage reference
REF1 is always greater than REF2, the comparators output
voltages (OUT5/6) is set. For this reason, the outputs of the
comparators (OUT5/6), have the same transient behavioral of
VOUT ( fig 18(c.i)). OUT5/6 are close to VOUT, however their
value depends on R26 and R27, which pulls a certain amount of
current by the comparators output, determining the voltage
drop on them. The value of R26&R27 for CMP5 is 45kΩ and the
value of R26&R27 for CMP6 is 29kΩ. Between the output of
the comparators CMP5 and CMP6 and the inputs of the SR
NAND latch 1, an inverting and not inverting buffer are
placed, respectively. The inverting buffer is done by a single
NOT gate, while the on inverting buffer is done by a cascade
of two NOT gates. As them outputs are set, they follows the
behavior of the VOUT, that supplies them. The waveforms at
the output of the buffers are shown in figures 18(c.ii). At the
output of the hysteresis comparators, the SR NAND latch 1
receives the waveforms shown in figure 18(c.ii). By varying
the value of R26 & R27, the values of REFH and REFL change,
as figure 18(c.iii) shows.
E. The analog multiplexer
The analog multiplexer has in input two signals, VOSC_1 and
VOSC_2, corresponding to the output voltages of feedforward
control circuit and feedback control circuit respectively.
Figure 19 shows the structure of the multiplexer:
IV. EXPERIMENTAL RESULTS ON
THE PROPOSED DC – DC CONVERTER
The proposed low input voltage DC–DC converter for
thermoelectric energy harvesting applications is implemented
in a standard 65nm CMOS process. To characterize electrical
properties of the DC–DC converter, the thermoelectric
generator is modeled by an ideal voltage source, ranging from
80mV to 370mV and 37.5kΩ equivalent series resistance, RS.
A 4F of input capacitance (CIN) has been added, in order to
keep the voltage at the output of the thermoelectric generator,
and reduce the kickback noise due to LBOOST inductor. Figure
20 shows the schematic of the measurements test bench.
RS
DC–DC
Converter
VIN
CIN
THERMOELECTRIC
GENERATOR
Fig. 20. Schematic of the test bench.
Figure 21 shows die photograph of the fabricated circuit. The
occupied chip area is 0.51mm2. As it is possible to note the
charge pump circuit occupied the largest area in the chip.
675µm

IN1
OUT
745µm
IN2

EN

Fig. 19. Schematic of the multiplexer.

The multiplexer enables one of the two input signals in order

to drive the gates of M7 and M8 MOS transistors of the boost
converter according to the control bit provided by AND gate
of the feedback control circuit ( fig. 5). The AND gate
receives the CMP4 comparator’s output (OUT_150) which is
set as VIN is higher than 150mV, and the output of the
hysteresis comparator. In practical, VOSC_1 is enabled as VIN is
in the range from 80mV to 150mV, while VOSC_2 is enabled as
VIN is higher than 150mV and VOUT reaches 1V.
Fig. 21. Die photograph.
The proposed DC–DC converter starts working with 80mV
input voltage, VIN. Figure 22 shows the waveforms, CLK and
CLK_INV, at the output of the local oscillator measured for
VIN equal to 80mV. Frequency oscillation is 200kHz and the
zero to peak voltage is around 160mV.

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CLK As regards the efficiency, it was evaluated by:

CLK INV
160 (7)

120 where POUT is the output power provided by the DC–DC

VOUT [mV]

converter to RLOAD and PIN is the input power, provided by

80 TEG. Figure 25 shows peak efficiency with different RLOAD.
As the latter increases, peak efficiency drops because output
40 power decreases, with the same input power. The proposed
converter reaches a peak at 73%, when RLOAD is 1.5KΩ and
0 VIN is 370mV.
0.5 3
5.5 8 10.5
Time [us] 70
Fig. 22. Waveforms at the output of the local oscillator for an 80mV of input

Peak Efficiency [%]

voltage (VIN). 60

In figure 23, the transient of VOUT is shown when VIN steps 50

from 0V up to 80mV. At 80mV VIN, the output voltage of the
40
DC–DC converter reaches a steady state value of 700mV, in
12ms. 30

0,7 20
VIN
VOUT
0,5 0 10 20 30 40 50 60 70
RLOAD [k]
[V]
OUT

Fig. 25. Peak efficiency vs RLOAD.

0,3
V

Figure 26 shows efficiency versus VIN.

0,1
0 70
0.19 0.2 0.21 0.22 0.23
Efficiency [%]

Time [s] 60
Fig. 23. Transients of the input voltage provided by TEG (VIN – red line) and
the output voltage of the DC – DC converter. (VOUT – black line). 50

Figure 24 shows VOUT versus VIN for various RLOAD. By 40

varying the input voltage from 80mV to 370mV, the output
voltage of boost converter is kept around 1V. It is worth
30
noting that 1.5kΩ is the minimum value of R LOAD, which the
DC–DC converter is able to supply with a significative peak 100 150 200 250 300 350
efficiency. VIN [mV]
1,2 Fig. 26. Efficiency versus VIN.

1,1 Table 3 reports the state of the art comparison. Among fully
electrical architectures, it has the lowest startup voltage, with
1
regulated output voltage and a good efficiency.
VOUT [V]

0,9 Rload = 1.5k ISSCC JSSCC ESSCIRC THIS

Rload = 10k [3] [4] [5] WORK
0,8 Rload = 100K STARTUP
35mV 20mV 85mV 80mV
VOLTAGE
0,7
OUTPUT 1V 0.7V – 1V
1.8V 0.4V – 1.2V
VOLTAGE reg. reg.
0.1 0.15 0.2 0.25 0.3 0.35
VIN [V] EFF. 58% 46% <3% 73%
STARTUP Mech. Ext. Fully Fully
Fig. 24. Output voltage (VOUT) vs input voltage (VIN), for various RLOAD values.
MECH. Switch Battery Electrical Electrical
Feedback control circuit achieves a more accurate control of CHIP 0.1mm2
1.6mm2 105µm2 (No 0.51mm2
the output voltage of boost converter in VIN range from 150mV AREA Transformer)
to 370mV. It is better than the 13%. TECH. 0.35µm 0.13µm 65nm 65nm
Tab. 3. State of the art.

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V. CONCLUSIONS
In this paper the electrical performance of a thin film flexible
TEG were presented and used as starting point for the design
of a fully electrical DC-DC converter. The TEG was realized
by screen printing technology on 80µm thick common paper
and 25µm thick Kapton foil and it integrates 280
thermocouples, electrically connected as parallel of two
blocks, each of which containing 140 thermocouples. The
thermoelectric module has an internal resistance of about
37.5kΩ and produces an open circuit output voltage of about
75mV at 5K of thermal gradient between the thermocouples
junctions. The proposed DC–DC converter has a startup
voltage of 80mV. The fully electrical characteristic of the
feedforward control circuit enables to the DC–DC converter
for an input voltage as low as 80mV, avoiding using bulky
external mechanical switch [2] or pre-charged battery [3]. This
makes the integration of converter with thermoelectric
generator in embedded system more attractive for wearable
health monitoring applications. Furthermore, by means
feedback control circuit, the output voltage is kept around 1V
in a wide range of VIN (80mV - 370mV) yielding a 73% peak
efficiency.
REFERENCES
[1] Y. Manoli, “Energy Harvesting – from Devices to Systems”, ESSCIRC,
Sep. 2010.
[2] V. Leonov, “Thermoelectric Energy Harvesting of Human Body Heat
for Wearable Sensors”, IEEE Sensors Journal, June 2013.
[3] Y. K. Ramadass, A. P. Chandrakasan, “A Batteryless Thermoelectric
Energy – Harvesting Interface Circuit with 35mV start-up Voltage”,
IEEE ISSCC Dig. Tech. Papers , Feb 2010.
[4] E. Carlson, K. Strunz, B. Otis, “20mV Input Boost Converter With
Efficent Digital control for Thermoelectric Energy Harvesting” IEEE
JSSC, Avr. 2010.
[5] H. Fuketa, et. al.“An 85-mV Input, 50µs Startup Fully Integrated
Voltage Multiplier with Passive Clock Boost Using On-Chip
Transformers for Energy Harvesting”, ESSCIRC, Sept 2014.
[6] R. E. Rottava, et al., “Ultra-low-power, ultra-low-voltage 2.12 GHz
colpitts oscillator using inductive gate degeneration,” in IEEE
International Conference on New Circuits and Systems (NEWCAS),
2013.
[7] R. Pelliconi, et. al. ”Power efficient charge pump in deep sub – micron
standard CMOS technology”, IEEE JSSC, 2003.
[8] Y. Lin, et al., “A dynamic latched comparator for low supply voltages
down to 0.45V in 65nm CMOS”, in IEEE International Symposium on
Circuits and Systems (ISCAS), 2014.
[9] F. Maloberti, “Current and Voltage Sources” in Analog Design for
CMOS VLSI Systems, Dordrecht, The Netherlands, K.A.P., 2001, pp.
205 – 211.
[10] M. De Matteis et al. “A 0.55V, 6dB – DR Fourth Ordere Analog
Baseband Filter” IEEE JSSC, Sept. 2009
[11] A. Chen et al., “Dispenser-printed planar thick-film thermoelectric
energy generators”, J. Micromech. Microeng. 21 (2011) 104006 (8pp).
[12] S.J. Kim et al., “Thermoelectric properties of P-type Sb2Te3 thick film
processed by a screen-printing technique and a subsequent annealing
process”, Journal of Alloys and Compounds 582 (2014) 177–180.
[13] S.J. Kim et al., “A wearable thermoelectric generator fabricated on a
glass fabric”, Environ. Sci., 2014, 7,1959.
[14] Thermoelectrics handbook: macro to nano / edited by D.M. Rowe
(2006),CRC press, ISBN 0-8493-2264-2.
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10
Carlo Veri was born in Lecce, Italy, in
1985. He received the B.Sc. degree in
information engineering at the University
of Salento (2010), discussing a thesis on
the design of integrated circuits for AM
LOW IF receivers in 180nm CMOS
technology. Afterwards, he received the
M.Sc. degree in telecommunications engineering at the
University of Salento (2013), discussing a thesis on the design
of a very low startup voltage DC-DC converter in 65nm
CMOS technology for thermoelectric energy harvesting
applications. Now he is a Ph.D. student at the same university.
He works on high efficiency DC-DC converters in CMOS
technology. Currently, he collaborates with the Institute of
Microelectronics and Microsystems of Lecce (CNR-IMM), in
order to develop flexible thermoelectric generator system.
Luca Francioso received the M.Sc. in
Physics 2001 at the University of Lecce.
Since 2001 he joined the Institute for
Microelectronic and Microsystems of the
Italian National of Research Council
(C.N.R.-I.M.M.) in Lecce (Italy), Sensors
and Microsytems group, working in the
field of silicon micromachined systems and
solid state thin film chemical sensors. Since
2002 he is in the position of researcher
devoted to silicon technology and
integration of sol-gel process into MEMS
sensors. In 2005, he was hosted as visiting researcher at CNM-
CSIC (Centro Nacional de Microelectronica) in Barcelona in
the framework of the Short Term Mobility Program of Italian
National Research Council (CNR), with an activity on
fabrication of low power consumption micromachined gas
sensors.In 2006 he takes the PhD degree with a thesis on
application of miniaturized gas sensors for combustion and
cabine air quality control in the automotive field; from 2008
he gained a researcher permanent position in the same
institute, working in the field of MEMS technology, FEA
simulation and sensors engineering and wearable energy
scavenging devices. Main activity is actually focused on
thermoelectric wearable generators for chemical sensing and
plasma actuators design and fabrication for aeronautical flow
control. He co-authored of more than 78 peer-reviewed papers
on national and international journals, 1 book chapters and
several Communications to national and International
Congresses as regular and invited talks.
Mirko Pasca was born in Trento, Italy, in
1984. He received the B.Sc. degree in
electronics engineering and the M.Sc.
degree in telecommunications engineering
from the University of Salento, Lecce,
Italy, in 2009 and 2012 respectively,
where he is currently working toward the
Ph.D. degree. He works on DC-DC and
RF-DC power converters in CMOS technology for energy
harvesting applications. His research interests includes
radiofrequency integrated circuits for UWB applications.
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Chiara De Pascali received the first Microelectronics, specialized in analog design service. He
level Laurea degree in Information authored more than 130 papers in journals and international
Engineering at the University of Lecce conferences, 7 book chapters, and 4 international patents in
(2005), discussing a thesis on the the field of low-power integrated circuits design, with
optimization of metallic contacts for particular emphasis on low-power continuous-time analog
quantum dots lasers. In 2009, she filters and A/D converters. Prof. D'Amico is a member of the
received the second level Laurea degree technical committees of several international IEEE
in Telecommunication Engineering (with Honour) at the conferences (ICICDT, PRIME, ICM 2013, Spie
University of Salento, discussing a thesis on the fabrication Microtechnologies 2015).
and electrical-functional characterization of gas sensors based
on titania nanometric strips using Impedance Spectroscopy. In
November 2013, she got the Ph.D. in Energetic Systems and
Environment at the same University, discussing a thesis on the
design and fabrication of a flexible MEMS thermoelectric
generator for Energy Harvesting applications. At present her
activity is mainly focused on FEM modelling, design and
fabrication of MEMS devices for energy harvesting
applications in wearable electronics.

Pietro Siciliano, physicist, senior

researcher, received his degree in
physics in 1985 from the University of
Lecce. He took his PhD in physics in
1989 at the University of Bari. During
the first years of activities he was
involved in research in the field of
electrical characterisation of semiconductors devices. He is
currently a senior member of the National Council of Research
in Lecce, where he has been working for many years in the
field of preparation and characterisation of thin film for gas
sensor, being in charge of the sensors group. He is author of
about 180 scientific papers, on national and international
journals, and a lot of communication, some invited, to
International Conferences. He is responsible for several
national and international projects at IMM-CNR in field of
sensors and microsystems, mainly for environmental
automotive and agro-food applications. He has been organiser
and chairman of international conferences and director of
international schools on sensors and microsystems. He is
member of the Steering Committee of AISEM, the Italian
Association on Sensors and Microsystems. At the moment he
is director of IMM-CNR in the Department of Lecce.

Stefano D’Amico received the MS

degree in Electrical Engineering from
the Politecnico di Bari (Bari, Italy), in
2001, and the Ph.D. degree from the
Istituto Superiore Universitario per la
Formazione Interdisciplinare (ISUFI)
(Lecce, Italy), in 2005. In 2007, he
joined the Department of Innovation
Engineering at the University of Salento
(Lecce, Italy) as Assistant Professor in Analog Electronics.
From 2015 he is serving as Associate Professor at the same
University. He is now leading the Electronics Laboratory at
the Department of Innovation Engineering at the University of
Salento. He collaborate with several companies
(STMicroelectronics, Infineon Technologies, Dialog
Semiconductors, Sondrel) and research centers (IMEC,
CERN, INFN, CNR). He co-founded a start-up, Thetis

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