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BS Computer Engineering Friday 07:00am – 10:00am
1. Load Electric.
3. Create new facet NOR_sch in library Exercise with schematic as the facet view.
Draw the NOR schematic in Figure 3-a.
Note: Lp, Ln = 0.35μm; Wp = 3.2μm; Wn = 0.8μm
Figure 3-b. Schematic diagram for the transient analysis of a NOR gate.
Note: loadcap = 100fF
SPICE card for DC → DC 3.3
SPICE card for Input A → PULSE(0 3.3 0 1n 1n 100n 200n)
SPICE card for Input B → PULSE(0 3.3 50n 1n 1n 100n 200n)
SPICE card for Transient Analysis→ 5p 500n 0 5p
9. Create a SPICE netlist of your circuit. Simulate the circuit using WinSpice. Verify if the
circuit is working properly by referring to the truth table of a NOR gate (Table 3-a).
Va Vb Vout(NOR) Vout(NAND)
0 0 1 1
0 1 0 1
1 0 0 1
1 1 0 0
Table 3-a. NOR and NAND gate truth table.
Wp = 3.2 μm
Wp = 1.6 μm
Wp = 0.80 μm
10.Fill-up the table below. Round off your answers to two decimal places.
WN WP τPHL τPLH
0.80μm 3.20μm 0.71ns 0.45ns
0.80μm 1.60μm 0.65ns 0.82ns
11.Repeat procedures 3 - 9 for a NAND gate (Figure 3-c and 3-d). Verify if the circuit is
working properly by referring to the truth table of a NAND gate (Table 3-a).
Note: Lp, Ln = 0.35μm; Wp = 3.2μm; Wn = 1.6μm
Figure 3-d. Schematic diagram for the transient analysis of a NAND gate.
Wp = 3.20 μm
Wp = 1.60 μm
Wp = 0.80 μm
12.Fill-up the table below. Round off your answers to two decimal places.
WN WP τPHL τPLH
1.60μ 3.20μ 0.46ns 0.33ns
1.60μ 1.60μm 0.40ns 0.55ns
1.60μ 0.80μ 0.37ns 1.07ns
Note: Refer to Exercise 2 for the determination of the τPHL and τPLH.